1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _FABRIC_XLATE_H 27 #define _FABRIC_XLATE_H 28 29 #include <fm/fmd_api.h> 30 #include <sys/fm/protocol.h> 31 #include <sys/nvpair.h> 32 #include <sys/types.h> 33 #include <sys/pcie.h> 34 #include <sys/fm/io/pci.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #define STRCMP(s1, s2) (strcmp((const char *)s1, (const char *)s2) == 0) 41 /* 42 * These values are used for the xxx_tgt_trans value in fab_data_t. They are 43 * originally set in pcie_fault.c and originally defined in pcie_impl.h. 44 */ 45 #define PF_ADDR_DMA (1 << 0) 46 #define PF_ADDR_PIO (1 << 1) 47 #define PF_ADDR_CFG (1 << 2) 48 49 extern fmd_xprt_t *fab_fmd_xprt; /* FMD transport layer handle */ 50 extern char fab_buf[]; 51 52 /* PCI-E config space data for error handling and fabric ereports */ 53 typedef struct fab_data { 54 /* Original ereport NVL */ 55 nvlist_t *nvl; 56 57 /* Device Information */ 58 uint16_t bdf; 59 uint16_t device_id; 60 uint16_t vendor_id; 61 uint8_t rev_id; 62 uint16_t dev_type; 63 uint16_t pcie_off; 64 uint16_t pcix_off; 65 uint16_t aer_off; 66 uint16_t ecc_ver; 67 68 /* Ereport Information */ 69 uint32_t remainder; 70 uint32_t severity; 71 72 /* Error Registers */ 73 uint16_t pci_err_status; /* pci status register */ 74 uint16_t pci_cfg_comm; /* pci command register */ 75 76 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 77 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 78 79 uint16_t pcix_command; /* pcix command register */ 80 uint32_t pcix_status; /* pcix status register */ 81 82 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 83 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 84 85 uint16_t pcix_ecc_control_0; /* pcix ecc control status reg */ 86 uint16_t pcix_ecc_status_0; /* pcix ecc control status reg */ 87 uint32_t pcix_ecc_fst_addr_0; /* pcix ecc first address reg */ 88 uint32_t pcix_ecc_sec_addr_0; /* pcix ecc second address reg */ 89 uint32_t pcix_ecc_attr_0; /* pcix ecc attributes reg */ 90 uint16_t pcix_ecc_control_1; /* pcix ecc control status reg */ 91 uint16_t pcix_ecc_status_1; /* pcix ecc control status reg */ 92 uint32_t pcix_ecc_fst_addr_1; /* pcix ecc first address reg */ 93 uint32_t pcix_ecc_sec_addr_1; /* pcix ecc second address reg */ 94 uint32_t pcix_ecc_attr_1; /* pcix ecc attributes reg */ 95 96 uint16_t pcie_err_status; /* pcie device status register */ 97 uint16_t pcie_err_ctl; /* pcie error control register */ 98 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 99 100 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 101 uint32_t pcie_ue_status; /* pcie ue error status reg */ 102 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 103 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 104 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 105 uint32_t pcie_ce_status; /* pcie ce error status reg */ 106 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 107 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 108 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 109 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from SAER Logs */ 110 boolean_t pcie_ue_no_tgt_erpt; /* Don't send target ereports */ 111 112 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 113 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 114 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 115 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 116 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 117 uint32_t pcie_sue_tgt_trans; /* Fault trans type from AER Logs */ 118 uint64_t pcie_sue_tgt_addr; /* Fault addr from AER Logs */ 119 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 120 121 uint32_t pcie_rp_status; /* root complex status register */ 122 uint16_t pcie_rp_ctl; /* root complex control register */ 123 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 124 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 125 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 126 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 127 } fab_data_t; 128 129 typedef struct fab_erpt_tbl { 130 const char *err_class; /* Final Ereport Class */ 131 uint32_t reg_bit; /* Error Bit Mask */ 132 /* Pointer to function that prepares the ereport body */ 133 const char *tgt_class; /* Target Ereport Class */ 134 } fab_erpt_tbl_t; 135 136 typedef struct fab_err_tbl { 137 fab_erpt_tbl_t *erpt_tbl; /* ereport table */ 138 uint32_t reg_offset; /* sts reg for ereport table offset */ 139 uint32_t reg_size; /* size of the status register */ 140 /* Pointer to function that prepares the ereport body */ 141 int (*fab_prep)(fmd_hdl_t *, fab_data_t *, nvlist_t *, 142 fab_erpt_tbl_t *); 143 } fab_err_tbl_t; 144 145 extern void fab_setup_master_table(); 146 147 /* Main functions for converting "fabric" ereports */ 148 extern void fab_xlate_pcie_erpts(fmd_hdl_t *, fab_data_t *); 149 extern void fab_xlate_fabric_erpts(fmd_hdl_t *, nvlist_t *, const char *); 150 extern void fab_xlate_fire_erpts(fmd_hdl_t *, nvlist_t *, const char *); 151 extern void fab_xlate_epkt_erpts(fmd_hdl_t *, nvlist_t *, const char *); 152 153 /* Common functions for sending translated ereports */ 154 extern int fab_prep_basic_erpt(fmd_hdl_t *, nvlist_t *, nvlist_t *, boolean_t); 155 extern void fab_send_tgt_erpt(fmd_hdl_t *, fab_data_t *, const char *, 156 boolean_t); 157 extern void fab_send_erpt(fmd_hdl_t *hdl, fab_data_t *data, fab_err_tbl_t *tbl); 158 159 /* Misc Functions */ 160 extern void fab_pr(fmd_hdl_t *, fmd_event_t *, nvlist_t *); 161 extern boolean_t fab_get_rcpath(fmd_hdl_t *hdl, nvlist_t *nvl, char *rcpath); 162 extern char *fab_find_rppath_by_df(fmd_hdl_t *, nvlist_t *, uint8_t); 163 extern char *fab_find_rppath_by_devbdf(fmd_hdl_t *, nvlist_t *, pcie_req_id_t); 164 extern char *fab_find_addr(fmd_hdl_t *hdl, nvlist_t *nvl, uint64_t addr); 165 extern char *fab_find_bdf(fmd_hdl_t *hdl, nvlist_t *nvl, pcie_req_id_t bdf); 166 extern boolean_t fab_hc2dev(fmd_hdl_t *, const char *, char **); 167 extern boolean_t fab_hc2dev_nvl(fmd_hdl_t *, nvlist_t *, char **); 168 169 #ifdef __cplusplus 170 } 171 #endif 172 173 #endif /* _FABRIC_XLATE_H */ 174