1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NIAGARAREGS_H 28 #define _SYS_NIAGARAREGS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Niagara SPARC Performance Instrumentation Counter 38 */ 39 #define PIC0_MASK (((uint64_t)1 << 32) - 1) /* pic0 in bits 31:0 */ 40 #define PIC1_SHIFT 32 /* pic1 in bits 64:32 */ 41 42 /* 43 * Niagara SPARC Performance Control Register 44 */ 45 46 #define CPC_NIAGARA_PCR_PRIVPIC 0 47 #define CPC_NIAGARA_PCR_SYS 1 48 #define CPC_NIAGARA_PCR_USR 2 49 50 #define CPC_NIAGARA_PCR_PIC0_SHIFT 4 51 #define CPC_NIAGARA_PCR_PIC1_SHIFT 0 52 #define CPC_NIAGARA_PCR_PIC0_MASK UINT64_C(0x7) 53 #define CPC_NIAGARA_PCR_PIC1_MASK UINT64_C(0) 54 55 #define CPC_NIAGARA_PCR_OVF_MASK UINT64_C(0x300) 56 #define CPC_NIAGARA_PCR_OVF_SHIFT 8 57 58 /* 59 * Niagara DRAM performance counters 60 */ 61 #define NIAGARA_DRAM_BANKS 0x4 62 63 #define NIAGARA_DRAM_PIC0_SEL_SHIFT 0x4 64 #define NIAGARA_DRAM_PIC1_SEL_SHIFT 0x0 65 66 #define NIAGARA_DRAM_PIC0_SHIFT 0x20 67 #define NIAGARA_DRAM_PIC0_MASK 0x7fffffff 68 #define NIAGARA_DRAM_PIC1_SHIFT 0x0 69 #define NIAGARA_DRAM_PIC1_MASK 0x7fffffff 70 71 /* 72 * Niagara JBUS performance counters 73 */ 74 #define NIAGARA_JBUS_PIC0_SEL_SHIFT 0x4 75 #define NIAGARA_JBUS_PIC1_SEL_SHIFT 0x0 76 77 #define NIAGARA_JBUS_PIC0_SHIFT 0x20 78 #define NIAGARA_JBUS_PIC0_MASK 0x7fffffff 79 #define NIAGARA_JBUS_PIC1_SHIFT 0x0 80 #define NIAGARA_JBUS_PIC1_MASK 0x7fffffff 81 82 83 /* 84 * Hypervisor FAST_TRAP API function numbers to get/set DRAM and 85 * JBUS performance counters 86 */ 87 #define HV_NIAGARA_GETPERF 0x100 88 #define HV_NIAGARA_SETPERF 0x101 89 90 91 /* 92 * DRAM/JBUS performance counter register numbers for HV_NIAGARA_GETPERF 93 * and HV_NIAGARA_SETPERF 94 */ 95 #define HV_NIAGARA_JBUS_CTL 0x0 96 #define HV_NIAGARA_JBUS_COUNT 0x1 97 #define HV_NIAGARA_DRAM_CTL0 0x2 98 #define HV_NIAGARA_DRAM_COUNT0 0x3 99 #define HV_NIAGARA_DRAM_CTL1 0x4 100 #define HV_NIAGARA_DRAM_COUNT1 0x5 101 #define HV_NIAGARA_DRAM_CTL2 0x6 102 #define HV_NIAGARA_DRAM_COUNT2 0x7 103 #define HV_NIAGARA_DRAM_CTL3 0x8 104 #define HV_NIAGARA_DRAM_COUNT3 0x9 105 106 /* 107 * prototypes for hypervisor interface to get/set DRAM and JBUS 108 * performance counters 109 */ 110 #ifndef _ASM 111 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val); 112 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val); 113 #endif 114 115 #ifdef __cplusplus 116 } 117 #endif 118 119 #endif /* _SYS_NIAGARAREGS_H */ 120