1*1ae08745Sheppo /*
2*1ae08745Sheppo * CDDL HEADER START
3*1ae08745Sheppo *
4*1ae08745Sheppo * The contents of this file are subject to the terms of the
5*1ae08745Sheppo * Common Development and Distribution License (the "License").
6*1ae08745Sheppo * You may not use this file except in compliance with the License.
7*1ae08745Sheppo *
8*1ae08745Sheppo * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*1ae08745Sheppo * or http://www.opensolaris.org/os/licensing.
10*1ae08745Sheppo * See the License for the specific language governing permissions
11*1ae08745Sheppo * and limitations under the License.
12*1ae08745Sheppo *
13*1ae08745Sheppo * When distributing Covered Code, include this CDDL HEADER in each
14*1ae08745Sheppo * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*1ae08745Sheppo * If applicable, add the following below this CDDL HEADER, with the
16*1ae08745Sheppo * fields enclosed by brackets "[]" replaced with your own identifying
17*1ae08745Sheppo * information: Portions Copyright [yyyy] [name of copyright owner]
18*1ae08745Sheppo *
19*1ae08745Sheppo * CDDL HEADER END
20*1ae08745Sheppo */
21*1ae08745Sheppo
22*1ae08745Sheppo /*
23*1ae08745Sheppo * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
24*1ae08745Sheppo * Use is subject to license terms.
25*1ae08745Sheppo */
26*1ae08745Sheppo
27*1ae08745Sheppo #pragma ident "%Z%%M% %I% %E% SMI"
28*1ae08745Sheppo
29*1ae08745Sheppo #include <sys/promif_impl.h>
30*1ae08745Sheppo #include <sys/machsystm.h>
31*1ae08745Sheppo #include <sys/hypervisor_api.h>
32*1ae08745Sheppo #include <sys/lpad.h>
33*1ae08745Sheppo
34*1ae08745Sheppo extern int (*prom_cif_handler)(void *);
35*1ae08745Sheppo extern int cif_cpu_mp_ready;
36*1ae08745Sheppo
37*1ae08745Sheppo int
promif_set_mmfsa_traptable(void * p)38*1ae08745Sheppo promif_set_mmfsa_traptable(void *p)
39*1ae08745Sheppo {
40*1ae08745Sheppo cell_t *ci = (cell_t *)p;
41*1ae08745Sheppo uint64_t rtba;
42*1ae08745Sheppo caddr_t tba;
43*1ae08745Sheppo uint64_t mmfsa_ra;
44*1ae08745Sheppo int rv, ret;
45*1ae08745Sheppo
46*1ae08745Sheppo ASSERT(ci[1] == 2);
47*1ae08745Sheppo
48*1ae08745Sheppo /*
49*1ae08745Sheppo * We use the same trap table for the rtba as well.
50*1ae08745Sheppo */
51*1ae08745Sheppo rtba = va_to_pa(p1275_cell2ptr(ci[3]));
52*1ae08745Sheppo
53*1ae08745Sheppo /*
54*1ae08745Sheppo * if cif_cpu_mp_ready is not set the prom is still
55*1ae08745Sheppo * setting the mmfsa and trap table. Set the rtba
56*1ae08745Sheppo * after the prom cif call.
57*1ae08745Sheppo */
58*1ae08745Sheppo if (!cif_cpu_mp_ready) {
59*1ae08745Sheppo ret = (*prom_cif_handler)(p);
60*1ae08745Sheppo if ((rv = hv_cpu_set_rtba(&rtba)) != H_EOK)
61*1ae08745Sheppo panic("hv_cpu_set_rtba failed: %d\n", rv);
62*1ae08745Sheppo return (ret);
63*1ae08745Sheppo }
64*1ae08745Sheppo
65*1ae08745Sheppo tba = p1275_cell2ptr(ci[3]);
66*1ae08745Sheppo mmfsa_ra = (uint64_t)p1275_cell2ptr(ci[4]);
67*1ae08745Sheppo
68*1ae08745Sheppo if (tba != (caddr_t)KERNELBASE)
69*1ae08745Sheppo return (-1);
70*1ae08745Sheppo
71*1ae08745Sheppo (void) set_tba(tba);
72*1ae08745Sheppo
73*1ae08745Sheppo if ((rv = hv_mmu_fault_area_conf(&mmfsa_ra)) != H_EOK) {
74*1ae08745Sheppo panic("hv_mmu_fault_area_conf failed: %d\n", rv);
75*1ae08745Sheppo }
76*1ae08745Sheppo
77*1ae08745Sheppo if ((rv = hv_cpu_set_rtba(&rtba)) != H_EOK) {
78*1ae08745Sheppo panic("hv_cpu_set_rtba failed: %d\n", rv);
79*1ae08745Sheppo }
80*1ae08745Sheppo
81*1ae08745Sheppo return (0);
82*1ae08745Sheppo }
83*1ae08745Sheppo
84*1ae08745Sheppo int
promif_start_cpu(void * p)85*1ae08745Sheppo promif_start_cpu(void *p)
86*1ae08745Sheppo {
87*1ae08745Sheppo cell_t *ci = (cell_t *)p;
88*1ae08745Sheppo int cpuid;
89*1ae08745Sheppo caddr_t pc;
90*1ae08745Sheppo int arg;
91*1ae08745Sheppo uint64_t rtba = 0;
92*1ae08745Sheppo int rv;
93*1ae08745Sheppo uint64_t *lpp;
94*1ae08745Sheppo
95*1ae08745Sheppo ASSERT(ci[1] == 3);
96*1ae08745Sheppo
97*1ae08745Sheppo cpuid = p1275_cell2int(ci[3]);
98*1ae08745Sheppo pc = p1275_cell2ptr(ci[4]);
99*1ae08745Sheppo arg = p1275_cell2int(ci[5]);
100*1ae08745Sheppo
101*1ae08745Sheppo if (!cif_cpu_mp_ready)
102*1ae08745Sheppo return ((*prom_cif_handler)(p));
103*1ae08745Sheppo
104*1ae08745Sheppo rtba = va_to_pa(&trap_table);
105*1ae08745Sheppo
106*1ae08745Sheppo lpp = lpad_setup(cpuid, (uint64_t)pc, (uint64_t)arg);
107*1ae08745Sheppo
108*1ae08745Sheppo ASSERT(lpp);
109*1ae08745Sheppo
110*1ae08745Sheppo pc = (caddr_t)lpp;
111*1ae08745Sheppo
112*1ae08745Sheppo rv = hv_cpu_start(cpuid, va_to_pa(pc), rtba, cpuid);
113*1ae08745Sheppo
114*1ae08745Sheppo if (rv != H_EOK) {
115*1ae08745Sheppo panic("promif_start_cpu: failed to start cpu %d (%d)\n",
116*1ae08745Sheppo cpuid, rv);
117*1ae08745Sheppo }
118*1ae08745Sheppo
119*1ae08745Sheppo ci[6] = p1275_int2cell(rv);
120*1ae08745Sheppo
121*1ae08745Sheppo return (0);
122*1ae08745Sheppo }
123