1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/machasi.h> 35#include <sys/machparam.h> 36#include <sys/hypervisor_api.h> 37#include <io/px/px_ioapi.h> 38 39#if defined(lint) || defined(__lint) 40 41/*ARGSUSED*/ 42int64_t 43hv_cnputchar(uint8_t ch) 44{ return (0); } 45 46/*ARGSUSED*/ 47int64_t 48hv_cngetchar(uint8_t *ch) 49{ return (0); } 50 51/*ARGSUSED*/ 52uint64_t 53hv_tod_get(uint64_t *seconds) 54{ return (0); } 55 56/*ARGSUSED*/ 57uint64_t 58hv_tod_set(uint64_t seconds) 59{ return (0);} 60 61/*ARGSUSED*/ 62uint64_t 63hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 64{ return (0); } 65 66/*ARGSUSED*/ 67uint64_t 68hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 69{ return (0); } 70 71/*ARGSUSED*/ 72uint64_t 73hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 74{ return (0); } 75 76/*ARGSUSED*/ 77uint64_t 78hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 79{ return (0); } 80 81#ifdef SET_MMU_STATS 82/*ARGSUSED*/ 83uint64_t 84hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 85{ return (0); } 86#endif /* SET_MMU_STATS */ 87 88/*ARGSUSED*/ 89uint64_t 90hv_cpu_qconf(int queue, uint64_t paddr, int size) 91{ return (0); } 92 93/*ARGSUSED*/ 94uint64_t 95hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 96 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 102 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data) 103{ return (0); } 104 105/*ARGSUSED*/ 106uint64_t 107hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 108{ return (0); } 109 110/*ARGSUSED*/ 111uint64_t 112hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 113{ return (0); } 114 115/*ARGSUSED*/ 116uint64_t 117hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 118{ return (0); } 119 120/*ARGSUSED*/ 121uint64_t 122hvio_intr_getstate(uint64_t sysino, int *intr_state) 123{ return (0); } 124 125/*ARGSUSED*/ 126uint64_t 127hvio_intr_setstate(uint64_t sysino, int intr_state) 128{ return (0); } 129 130/*ARGSUSED*/ 131uint64_t 132hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 133{ return (0); } 134 135/*ARGSUSED*/ 136uint64_t 137hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 138{ return (0); } 139 140/*ARGSUSED*/ 141uint64_t 142hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 143 pages_t pages, io_attributes_t io_attributes, 144 io_page_list_t *io_page_list_p, pages_t *pages_mapped) 145{ return (0); } 146 147/*ARGSUSED*/ 148uint64_t 149hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 150 pages_t pages, pages_t *pages_demapped) 151{ return (0); } 152 153/*ARGSUSED*/ 154uint64_t 155hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 156 io_attributes_t *attributes_p, r_addr_t *r_addr_p) 157{ return (0); } 158 159/*ARGSUSED*/ 160uint64_t 161hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 162 io_attributes_t io_attributes, io_addr_t *io_addr_p) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 168 uint64_t *data_p) 169{ return (0); } 170 171/*ARGSUSED*/ 172uint64_t 173hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 174 r_addr_t ra2, uint32_t *rdbk_status) 175{ return (0); } 176 177/*ARGSUSED*/ 178uint64_t 179hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 180 int io_sync_direction, size_t *bytes_synched) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 186 uint_t msiq_rec_cnt) 187{ return (0); } 188 189/*ARGSUSED*/ 190uint64_t 191hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 192 uint_t *msiq_rec_cnt_p) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 198 pci_msiq_valid_state_t *msiq_valid_state) 199{ return (0); } 200 201/*ARGSUSED*/ 202uint64_t 203hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 204 pci_msiq_valid_state_t msiq_valid_state) 205{ return (0); } 206 207/*ARGSUSED*/ 208uint64_t 209hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 210 pci_msiq_state_t *msiq_state) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 216 pci_msiq_state_t msiq_state) 217{ return (0); } 218 219/*ARGSUSED*/ 220uint64_t 221hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 222 msiqhead_t *msiq_head) 223{ return (0); } 224 225/*ARGSUSED*/ 226uint64_t 227hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 228 msiqhead_t msiq_head) 229{ return (0); } 230 231/*ARGSUSED*/ 232uint64_t 233hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 234 msiqtail_t *msiq_tail) 235{ return (0); } 236 237/*ARGSUSED*/ 238uint64_t 239hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 240 msiqid_t *msiq_id) 241{ return (0); } 242 243/*ARGSUSED*/ 244uint64_t 245hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 246 msiqid_t msiq_id, msi_type_t msitype) 247{ return (0); } 248 249/*ARGSUSED*/ 250uint64_t 251hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 252 pci_msi_valid_state_t *msi_valid_state) 253{ return (0); } 254 255/*ARGSUSED*/ 256uint64_t 257hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 258 pci_msi_valid_state_t msi_valid_state) 259{ return (0); } 260 261/*ARGSUSED*/ 262uint64_t 263hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 264 pci_msi_state_t *msi_state) 265{ return (0); } 266 267/*ARGSUSED*/ 268uint64_t 269hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 270 pci_msi_state_t msi_state) 271{ return (0); } 272 273/*ARGSUSED*/ 274uint64_t 275hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 276 msiqid_t *msiq_id) 277{ return (0); } 278 279/*ARGSUSED*/ 280uint64_t 281hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 282 msiqid_t msiq_id) 283{ return (0); } 284 285/*ARGSUSED*/ 286uint64_t 287hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 288 pcie_msg_valid_state_t *msg_valid_state) 289{ return (0); } 290 291/*ARGSUSED*/ 292uint64_t 293hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 294 pcie_msg_valid_state_t msg_valid_state) 295{ return (0); } 296 297uint64_t 298hv_cpu_yield(void) 299{ return (0); } 300 301/*ARGSUSED*/ 302uint64_t 303hv_service_recv(uint64_t s_id, uint64_t buf_pa, uint64_t size, 304 uint64_t *recv_bytes) 305{ return (0); } 306 307/*ARGSUSED*/ 308uint64_t 309hv_service_send(uint64_t s_id, uint64_t buf_pa, uint64_t size, 310 uint64_t *send_bytes) 311{ return (0); } 312 313/*ARGSUSED*/ 314uint64_t 315hv_service_getstatus(uint64_t s_id, uint64_t *vreg) 316{ return (0); } 317 318/*ARGSUSED*/ 319uint64_t 320hv_service_setstatus(uint64_t s_id, uint64_t bits) 321{ return (0); } 322 323/*ARGSUSED*/ 324uint64_t 325hv_service_clrstatus(uint64_t s_id, uint64_t bits) 326{ return (0); } 327 328/*ARGSUSED*/ 329uint64_t 330hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 331{ return (0); } 332 333/*ARGSUSED*/ 334uint64_t 335hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 336{ return (0); } 337 338/*ARGSUSED*/ 339uint64_t 340hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 341{ return (0); } 342 343/*ARGSUSED*/ 344uint64_t 345hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 346{ return (0); } 347 348/*ARGSUSED*/ 349uint64_t 350hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 351{ return (0); } 352 353/*ARGSUSED*/ 354uint64_t 355hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 356{ return (0); } 357 358/*ARGSUSED*/ 359uint64_t 360hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 361{ return (0); } 362 363/*ARGSUSED*/ 364uint64_t 365hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 366{ return (0); } 367 368/*ARGSUSED*/ 369uint64_t 370hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 371{ return (0); } 372 373/*ARGSUSED*/ 374uint64_t 375hv_ncs_request(int cmd, uint64_t realaddr, size_t sz) 376{ return (0); } 377 378#else /* lint || __lint */ 379 380 /* 381 * %o0 - character 382 */ 383 ENTRY(hv_cnputchar) 384 mov CONS_WRITE, %o5 385 ta FAST_TRAP 386 tst %o0 387 retl 388 movnz %xcc, -1, %o0 389 SET_SIZE(hv_cnputchar) 390 391 /* 392 * %o0 pointer to character buffer 393 * return values: 394 * 0 success 395 * hv_errno failure 396 */ 397 ENTRY(hv_cngetchar) 398 mov %o0, %o2 399 mov CONS_READ, %o5 400 ta FAST_TRAP 401 brnz,a %o0, 1f ! failure, just return error 402 mov 1, %o0 403 404 cmp %o1, H_BREAK 405 be 1f 406 mov %o1, %o0 407 408 cmp %o1, H_HUP 409 be 1f 410 mov %o1, %o0 411 412 stb %o1, [%o2] ! success, save character and return 0 413 mov 0, %o0 4141: 415 retl 416 nop 417 SET_SIZE(hv_cngetchar) 418 419 ENTRY(hv_tod_get) 420 mov %o0, %o4 421 mov TOD_GET, %o5 422 ta FAST_TRAP 423 retl 424 stx %o1, [%o4] 425 SET_SIZE(hv_tod_get) 426 427 ENTRY(hv_tod_set) 428 mov TOD_SET, %o5 429 ta FAST_TRAP 430 retl 431 nop 432 SET_SIZE(hv_tod_set) 433 434 /* 435 * Map permanent address 436 * arg0 vaddr (%o0) 437 * arg1 context (%o1) 438 * arg2 tte (%o2) 439 * arg3 flags (%o3) 0x1=d 0x2=i 440 */ 441 ENTRY(hv_mmu_map_perm_addr) 442 mov MAP_PERM_ADDR, %o5 443 ta FAST_TRAP 444 retl 445 nop 446 SET_SIZE(hv_mmu_map_perm_addr) 447 448 /* 449 * Unmap permanent address 450 * arg0 vaddr (%o0) 451 * arg1 context (%o1) 452 * arg2 flags (%o2) 0x1=d 0x2=i 453 */ 454 ENTRY(hv_mmu_unmap_perm_addr) 455 mov UNMAP_PERM_ADDR, %o5 456 ta FAST_TRAP 457 retl 458 nop 459 SET_SIZE(hv_mmu_unmap_perm_addr) 460 461 /* 462 * Set TSB for context 0 463 * arg0 ntsb_descriptor (%o0) 464 * arg1 desc_ra (%o1) 465 */ 466 ENTRY(hv_set_ctx0) 467 mov MMU_TSB_CTX0, %o5 468 ta FAST_TRAP 469 retl 470 nop 471 SET_SIZE(hv_set_ctx0) 472 473 /* 474 * Set TSB for context non0 475 * arg0 ntsb_descriptor (%o0) 476 * arg1 desc_ra (%o1) 477 */ 478 ENTRY(hv_set_ctxnon0) 479 mov MMU_TSB_CTXNON0, %o5 480 ta FAST_TRAP 481 retl 482 nop 483 SET_SIZE(hv_set_ctxnon0) 484 485#ifdef SET_MMU_STATS 486 /* 487 * Returns old stat area on success 488 */ 489 ENTRY(hv_mmu_set_stat_area) 490 mov MMU_STAT_AREA, %o5 491 ta FAST_TRAP 492 retl 493 nop 494 SET_SIZE(hv_mmu_set_stat_area) 495#endif /* SET_MMU_STATS */ 496 497 /* 498 * CPU Q Configure 499 * arg0 queue (%o0) 500 * arg1 Base address RA (%o1) 501 * arg2 Size (%o2) 502 */ 503 ENTRY(hv_cpu_qconf) 504 mov CPU_QCONF, %o5 505 ta FAST_TRAP 506 retl 507 nop 508 SET_SIZE(hv_cpu_qconf) 509 510 /* 511 * arg0 - devhandle 512 * arg1 - pci_device 513 * arg2 - pci_config_offset 514 * arg3 - pci_config_size 515 * 516 * ret0 - status 517 * ret1 - error_flag 518 * ret2 - pci_cfg_data 519 */ 520 ENTRY(hvio_config_get) 521 mov HVIO_CONFIG_GET, %o5 522 ta FAST_TRAP 523 brnz %o0, 1f 524 movrnz %o1, -1, %o2 525 brz,a %o1, 1f 526 stuw %o2, [%o4] 5271: retl 528 nop 529 SET_SIZE(hvio_config_get) 530 531 /* 532 * arg0 - devhandle 533 * arg1 - pci_device 534 * arg2 - pci_config_offset 535 * arg3 - pci_config_size 536 * arg4 - pci_cfg_data 537 * 538 * ret0 - status 539 * ret1 - error_flag 540 */ 541 ENTRY(hvio_config_put) 542 mov HVIO_CONFIG_PUT, %o5 543 ta FAST_TRAP 544 retl 545 nop 546 SET_SIZE(hvio_config_put) 547 548 /* 549 * arg0 - devhandle 550 * arg1 - devino 551 * 552 * ret0 - status 553 * ret1 - sysino 554 */ 555 ENTRY(hvio_intr_devino_to_sysino) 556 mov HVIO_INTR_DEVINO2SYSINO, %o5 557 ta FAST_TRAP 558 brz,a %o0, 1f 559 stx %o1, [%o2] 5601: retl 561 nop 562 SET_SIZE(hvio_intr_devino_to_sysino) 563 564 /* 565 * arg0 - sysino 566 * 567 * ret0 - status 568 * ret1 - intr_valid_state 569 */ 570 ENTRY(hvio_intr_getvalid) 571 mov %o1, %o2 572 mov HVIO_INTR_GETVALID, %o5 573 ta FAST_TRAP 574 brz,a %o0, 1f 575 stuw %o1, [%o2] 5761: retl 577 nop 578 SET_SIZE(hvio_intr_getvalid) 579 580 /* 581 * arg0 - sysino 582 * arg1 - intr_valid_state 583 * 584 * ret0 - status 585 */ 586 ENTRY(hvio_intr_setvalid) 587 mov HVIO_INTR_SETVALID, %o5 588 ta FAST_TRAP 589 retl 590 nop 591 SET_SIZE(hvio_intr_setvalid) 592 593 /* 594 * arg0 - sysino 595 * 596 * ret0 - status 597 * ret1 - intr_state 598 */ 599 ENTRY(hvio_intr_getstate) 600 mov %o1, %o2 601 mov HVIO_INTR_GETSTATE, %o5 602 ta FAST_TRAP 603 brz,a %o0, 1f 604 stuw %o1, [%o2] 6051: retl 606 nop 607 SET_SIZE(hvio_intr_getstate) 608 609 /* 610 * arg0 - sysino 611 * arg1 - intr_state 612 * 613 * ret0 - status 614 */ 615 ENTRY(hvio_intr_setstate) 616 mov HVIO_INTR_SETSTATE, %o5 617 ta FAST_TRAP 618 retl 619 nop 620 SET_SIZE(hvio_intr_setstate) 621 622 /* 623 * arg0 - sysino 624 * 625 * ret0 - status 626 * ret1 - cpu_id 627 */ 628 ENTRY(hvio_intr_gettarget) 629 mov %o1, %o2 630 mov HVIO_INTR_GETTARGET, %o5 631 ta FAST_TRAP 632 brz,a %o0, 1f 633 stuw %o1, [%o2] 6341: retl 635 nop 636 SET_SIZE(hvio_intr_gettarget) 637 638 /* 639 * arg0 - sysino 640 * arg1 - cpu_id 641 * 642 * ret0 - status 643 */ 644 ENTRY(hvio_intr_settarget) 645 mov HVIO_INTR_SETTARGET, %o5 646 ta FAST_TRAP 647 retl 648 nop 649 SET_SIZE(hvio_intr_settarget) 650 651 /* 652 * arg0 - devhandle 653 * arg1 - tsbid 654 * arg2 - pages 655 * arg3 - io_attributes 656 * arg4 - io_page_list_p 657 * 658 * ret1 - pages_mapped 659 */ 660 ENTRY(hvio_iommu_map) 661 save %sp, -SA(MINFRAME64), %sp 662 mov %i0, %o0 663 mov %i1, %o1 664 mov %i2, %o2 665 mov %i3, %o3 666 mov %i4, %o4 667 mov HVIO_IOMMU_MAP, %o5 668 ta FAST_TRAP 669 brnz %o0, 1f 670 mov %o0, %i0 671 stuw %o1, [%i5] 6721: 673 ret 674 restore 675 SET_SIZE(hvio_iommu_map) 676 677 /* 678 * arg0 - devhandle 679 * arg1 - tsbid 680 * arg2 - pages 681 * 682 * ret1 - pages_demapped 683 */ 684 ENTRY(hvio_iommu_demap) 685 mov HVIO_IOMMU_DEMAP, %o5 686 ta FAST_TRAP 687 brz,a %o0, 1f 688 stuw %o1, [%o3] 6891: retl 690 nop 691 SET_SIZE(hvio_iommu_demap) 692 693 /* 694 * arg0 - devhandle 695 * arg1 - tsbid 696 * 697 * 698 * ret0 - status 699 * ret1 - io_attributes 700 * ret2 - r_addr 701 */ 702 ENTRY(hvio_iommu_getmap) 703 mov %o2, %o4 704 mov HVIO_IOMMU_GETMAP, %o5 705 ta FAST_TRAP 706 brnz %o0, 1f 707 nop 708 stx %o2, [%o3] 709 st %o1, [%o4] 7101: 711 retl 712 nop 713 SET_SIZE(hvio_iommu_getmap) 714 715 /* 716 * arg0 - devhandle 717 * arg1 - r_addr 718 * arg2 - io_attributes 719 * 720 * 721 * ret0 - status 722 * ret1 - io_addr 723 */ 724 ENTRY(hvio_iommu_getbypass) 725 mov HVIO_IOMMU_GETBYPASS, %o5 726 ta FAST_TRAP 727 brz,a %o0, 1f 728 stx %o1, [%o3] 7291: retl 730 nop 731 SET_SIZE(hvio_iommu_getbypass) 732 733 /* 734 * arg0 - devhandle 735 * arg1 - r_addr 736 * arg2 - size 737 * 738 * ret1 - error_flag 739 * ret2 - data 740 */ 741 ENTRY(hvio_peek) 742 mov HVIO_PEEK, %o5 743 ta FAST_TRAP 744 brnz %o0, 1f 745 nop 746 stx %o2, [%o4] 747 st %o1, [%o3] 7481: 749 retl 750 nop 751 SET_SIZE(hvio_peek) 752 753 /* 754 * arg0 - devhandle 755 * arg1 - r_addr 756 * arg2 - sizes 757 * arg3 - data 758 * arg4 - r_addr2 759 * 760 * ret1 - error_flag 761 */ 762 ENTRY(hvio_poke) 763 save %sp, -SA(MINFRAME64), %sp 764 mov %i0, %o0 765 mov %i1, %o1 766 mov %i2, %o2 767 mov %i3, %o3 768 mov %i4, %o4 769 mov HVIO_POKE, %o5 770 ta FAST_TRAP 771 brnz %o0, 1f 772 mov %o0, %i0 773 stuw %o1, [%i5] 7741: 775 ret 776 restore 777 SET_SIZE(hvio_poke) 778 779 /* 780 * arg0 - devhandle 781 * arg1 - r_addr 782 * arg2 - num_bytes 783 * arg3 - io_sync_direction 784 * 785 * ret0 - status 786 * ret1 - bytes_synched 787 */ 788 ENTRY(hvio_dma_sync) 789 mov HVIO_DMA_SYNC, %o5 790 ta FAST_TRAP 791 brz,a %o0, 1f 792 stx %o1, [%o4] 7931: retl 794 nop 795 SET_SIZE(hvio_dma_sync) 796 797 /* 798 * arg0 - devhandle 799 * arg1 - msiq_id 800 * arg2 - r_addr 801 * arg3 - nentries 802 * 803 * ret0 - status 804 */ 805 ENTRY(hvio_msiq_conf) 806 mov HVIO_MSIQ_CONF, %o5 807 ta FAST_TRAP 808 retl 809 nop 810 SET_SIZE(hvio_msiq_conf) 811 812 /* 813 * arg0 - devhandle 814 * arg1 - msiq_id 815 * 816 * ret0 - status 817 * ret1 - r_addr 818 * ret1 - nentries 819 */ 820 ENTRY(hvio_msiq_info) 821 mov %o2, %o4 822 mov HVIO_MSIQ_INFO, %o5 823 ta FAST_TRAP 824 brnz 1f 825 nop 826 stx %o1, [%o4] 827 stuw %o2, [%o3] 8281: retl 829 nop 830 SET_SIZE(hvio_msiq_info) 831 832 /* 833 * arg0 - devhandle 834 * arg1 - msiq_id 835 * 836 * ret0 - status 837 * ret1 - msiq_valid_state 838 */ 839 ENTRY(hvio_msiq_getvalid) 840 mov HVIO_MSIQ_GETVALID, %o5 841 ta FAST_TRAP 842 brz,a %o0, 1f 843 stuw %o1, [%o2] 8441: retl 845 nop 846 SET_SIZE(hvio_msiq_getvalid) 847 848 /* 849 * arg0 - devhandle 850 * arg1 - msiq_id 851 * arg2 - msiq_valid_state 852 * 853 * ret0 - status 854 */ 855 ENTRY(hvio_msiq_setvalid) 856 mov HVIO_MSIQ_SETVALID, %o5 857 ta FAST_TRAP 858 retl 859 nop 860 SET_SIZE(hvio_msiq_setvalid) 861 862 /* 863 * arg0 - devhandle 864 * arg1 - msiq_id 865 * 866 * ret0 - status 867 * ret1 - msiq_state 868 */ 869 ENTRY(hvio_msiq_getstate) 870 mov HVIO_MSIQ_GETSTATE, %o5 871 ta FAST_TRAP 872 brz,a %o0, 1f 873 stuw %o1, [%o2] 8741: retl 875 nop 876 SET_SIZE(hvio_msiq_getstate) 877 878 /* 879 * arg0 - devhandle 880 * arg1 - msiq_id 881 * arg2 - msiq_state 882 * 883 * ret0 - status 884 */ 885 ENTRY(hvio_msiq_setstate) 886 mov HVIO_MSIQ_SETSTATE, %o5 887 ta FAST_TRAP 888 retl 889 nop 890 SET_SIZE(hvio_msiq_setstate) 891 892 /* 893 * arg0 - devhandle 894 * arg1 - msiq_id 895 * 896 * ret0 - status 897 * ret1 - msiq_head 898 */ 899 ENTRY(hvio_msiq_gethead) 900 mov HVIO_MSIQ_GETHEAD, %o5 901 ta FAST_TRAP 902 brz,a %o0, 1f 903 stx %o1, [%o2] 9041: retl 905 nop 906 SET_SIZE(hvio_msiq_gethead) 907 908 /* 909 * arg0 - devhandle 910 * arg1 - msiq_id 911 * arg2 - msiq_head 912 * 913 * ret0 - status 914 */ 915 ENTRY(hvio_msiq_sethead) 916 mov HVIO_MSIQ_SETHEAD, %o5 917 ta FAST_TRAP 918 retl 919 nop 920 SET_SIZE(hvio_msiq_sethead) 921 922 /* 923 * arg0 - devhandle 924 * arg1 - msiq_id 925 * 926 * ret0 - status 927 * ret1 - msiq_tail 928 */ 929 ENTRY(hvio_msiq_gettail) 930 mov HVIO_MSIQ_GETTAIL, %o5 931 ta FAST_TRAP 932 brz,a %o0, 1f 933 stx %o1, [%o2] 9341: retl 935 nop 936 SET_SIZE(hvio_msiq_gettail) 937 938 /* 939 * arg0 - devhandle 940 * arg1 - msi_num 941 * 942 * ret0 - status 943 * ret1 - msiq_id 944 */ 945 ENTRY(hvio_msi_getmsiq) 946 mov HVIO_MSI_GETMSIQ, %o5 947 ta FAST_TRAP 948 brz,a %o0, 1f 949 stuw %o1, [%o2] 9501: retl 951 nop 952 SET_SIZE(hvio_msi_getmsiq) 953 954 /* 955 * arg0 - devhandle 956 * arg1 - msi_num 957 * arg2 - msiq_id 958 * arg2 - msitype 959 * 960 * ret0 - status 961 */ 962 ENTRY(hvio_msi_setmsiq) 963 mov HVIO_MSI_SETMSIQ, %o5 964 ta FAST_TRAP 965 retl 966 nop 967 SET_SIZE(hvio_msi_setmsiq) 968 969 /* 970 * arg0 - devhandle 971 * arg1 - msi_num 972 * 973 * ret0 - status 974 * ret1 - msi_valid_state 975 */ 976 ENTRY(hvio_msi_getvalid) 977 mov HVIO_MSI_GETVALID, %o5 978 ta FAST_TRAP 979 brz,a %o0, 1f 980 stuw %o1, [%o2] 9811: retl 982 nop 983 SET_SIZE(hvio_msi_getvalid) 984 985 /* 986 * arg0 - devhandle 987 * arg1 - msi_num 988 * arg2 - msi_valid_state 989 * 990 * ret0 - status 991 */ 992 ENTRY(hvio_msi_setvalid) 993 mov HVIO_MSI_SETVALID, %o5 994 ta FAST_TRAP 995 retl 996 nop 997 SET_SIZE(hvio_msi_setvalid) 998 999 /* 1000 * arg0 - devhandle 1001 * arg1 - msi_num 1002 * 1003 * ret0 - status 1004 * ret1 - msi_state 1005 */ 1006 ENTRY(hvio_msi_getstate) 1007 mov HVIO_MSI_GETSTATE, %o5 1008 ta FAST_TRAP 1009 brz,a %o0, 1f 1010 stuw %o1, [%o2] 10111: retl 1012 nop 1013 SET_SIZE(hvio_msi_getstate) 1014 1015 /* 1016 * arg0 - devhandle 1017 * arg1 - msi_num 1018 * arg2 - msi_state 1019 * 1020 * ret0 - status 1021 */ 1022 ENTRY(hvio_msi_setstate) 1023 mov HVIO_MSI_SETSTATE, %o5 1024 ta FAST_TRAP 1025 retl 1026 nop 1027 SET_SIZE(hvio_msi_setstate) 1028 1029 /* 1030 * arg0 - devhandle 1031 * arg1 - msg_type 1032 * 1033 * ret0 - status 1034 * ret1 - msiq_id 1035 */ 1036 ENTRY(hvio_msg_getmsiq) 1037 mov HVIO_MSG_GETMSIQ, %o5 1038 ta FAST_TRAP 1039 brz,a %o0, 1f 1040 stuw %o1, [%o2] 10411: retl 1042 nop 1043 SET_SIZE(hvio_msg_getmsiq) 1044 1045 /* 1046 * arg0 - devhandle 1047 * arg1 - msg_type 1048 * arg2 - msiq_id 1049 * 1050 * ret0 - status 1051 */ 1052 ENTRY(hvio_msg_setmsiq) 1053 mov HVIO_MSG_SETMSIQ, %o5 1054 ta FAST_TRAP 1055 retl 1056 nop 1057 SET_SIZE(hvio_msg_setmsiq) 1058 1059 /* 1060 * arg0 - devhandle 1061 * arg1 - msg_type 1062 * 1063 * ret0 - status 1064 * ret1 - msg_valid_state 1065 */ 1066 ENTRY(hvio_msg_getvalid) 1067 mov HVIO_MSG_GETVALID, %o5 1068 ta FAST_TRAP 1069 brz,a %o0, 1f 1070 stuw %o1, [%o2] 10711: retl 1072 nop 1073 SET_SIZE(hvio_msg_getvalid) 1074 1075 /* 1076 * arg0 - devhandle 1077 * arg1 - msg_type 1078 * arg2 - msg_valid_state 1079 * 1080 * ret0 - status 1081 */ 1082 ENTRY(hvio_msg_setvalid) 1083 mov HVIO_MSG_SETVALID, %o5 1084 ta FAST_TRAP 1085 retl 1086 nop 1087 SET_SIZE(hvio_msg_setvalid) 1088 1089 /* 1090 * hv_cpu_yield(void) 1091 */ 1092 ENTRY(hv_cpu_yield) 1093 mov HV_CPU_YIELD, %o5 1094 ta FAST_TRAP 1095 retl 1096 nop 1097 SET_SIZE(hv_cpu_yield) 1098 1099 /* 1100 * hv_service_recv(uint64_t s_id, uint64_t buf_pa, 1101 * uint64_t size, uint64_t *recv_bytes); 1102 */ 1103 ENTRY(hv_service_recv) 1104 save %sp, -SA(MINFRAME), %sp 1105 mov %i0, %o0 1106 mov %i1, %o1 1107 mov %i2, %o2 1108 mov %i3, %o3 1109 mov SVC_RECV, %o5 1110 ta FAST_TRAP 1111 brnz %o0, 1f 1112 mov %o0, %i0 1113 stx %o1, [%i3] 11141: 1115 ret 1116 restore 1117 SET_SIZE(hv_service_recv) 1118 1119 /* 1120 * hv_service_send(uint64_t s_id, uint64_t buf_pa, 1121 * uint64_t size, uint64_t *recv_bytes); 1122 */ 1123 ENTRY(hv_service_send) 1124 save %sp, -SA(MINFRAME), %sp 1125 mov %i0, %o0 1126 mov %i1, %o1 1127 mov %i2, %o2 1128 mov %i3, %o3 1129 mov SVC_SEND, %o5 1130 ta FAST_TRAP 1131 brnz %o0, 1f 1132 mov %o0, %i0 1133 stx %o1, [%i3] 11341: 1135 ret 1136 restore 1137 SET_SIZE(hv_service_send) 1138 1139 /* 1140 * hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 1141 */ 1142 ENTRY(hv_service_getstatus) 1143 mov %o1, %o4 ! save datap 1144 mov SVC_GETSTATUS, %o5 1145 ta FAST_TRAP 1146 brz,a %o0, 1f 1147 stx %o1, [%o4] 11481: 1149 retl 1150 nop 1151 SET_SIZE(hv_service_getstatus) 1152 1153 /* 1154 * hv_service_setstatus(uint64_t s_id, uint64_t bits); 1155 */ 1156 ENTRY(hv_service_setstatus) 1157 mov SVC_SETSTATUS, %o5 1158 ta FAST_TRAP 1159 retl 1160 nop 1161 SET_SIZE(hv_service_setstatus) 1162 1163 /* 1164 * hv_service_clrstatus(uint64_t s_id, uint64_t bits); 1165 */ 1166 ENTRY(hv_service_clrstatus) 1167 mov SVC_CLRSTATUS, %o5 1168 ta FAST_TRAP 1169 retl 1170 nop 1171 SET_SIZE(hv_service_clrstatus) 1172 1173 /* 1174 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 1175 */ 1176 ENTRY(hv_cpu_state) 1177 mov %o1, %o4 ! save datap 1178 mov HV_CPU_STATE, %o5 1179 ta FAST_TRAP 1180 brz,a %o0, 1f 1181 stx %o1, [%o4] 11821: 1183 retl 1184 nop 1185 SET_SIZE(hv_cpu_state) 1186 1187 /* 1188 * HV state dump zone Configure 1189 * arg0 real adrs of dump buffer (%o0) 1190 * arg1 size of dump buffer (%o1) 1191 * ret0 status (%o0) 1192 * ret1 size of buffer on success and min size on EINVAL (%o1) 1193 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 1194 */ 1195 ENTRY(hv_dump_buf_update) 1196 mov DUMP_BUF_UPDATE, %o5 1197 ta FAST_TRAP 1198 retl 1199 stx %o1, [%o2] 1200 SET_SIZE(hv_dump_buf_update) 1201 1202 1203 /* 1204 * For memory scrub 1205 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 1206 * uint64_t *scrubbed_len); 1207 * Retun %o0 -- status 1208 * %o1 -- bytes scrubbed 1209 */ 1210 ENTRY(hv_mem_scrub) 1211 mov %o2, %o4 1212 mov HV_MEM_SCRUB, %o5 1213 ta FAST_TRAP 1214 retl 1215 stx %o1, [%o4] 1216 SET_SIZE(hv_mem_scrub) 1217 1218 /* 1219 * Flush ecache 1220 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 1221 * uint64_t *flushed_len); 1222 * Retun %o0 -- status 1223 * %o1 -- bytes flushed 1224 */ 1225 ENTRY(hv_mem_sync) 1226 mov %o2, %o4 1227 mov HV_MEM_SYNC, %o5 1228 ta FAST_TRAP 1229 retl 1230 stx %o1, [%o4] 1231 SET_SIZE(hv_mem_sync) 1232 1233 /* 1234 * TTRACE_BUF_CONF Configure 1235 * arg0 RA base of buffer (%o0) 1236 * arg1 buf size in no. of entries (%o1) 1237 * ret0 status (%o0) 1238 * ret1 minimum size in no. of entries on failure, 1239 * actual size in no. of entries on success (%o1) 1240 */ 1241 ENTRY(hv_ttrace_buf_conf) 1242 mov TTRACE_BUF_CONF, %o5 1243 ta FAST_TRAP 1244 retl 1245 stx %o1, [%o2] 1246 SET_SIZE(hv_ttrace_buf_conf) 1247 1248 /* 1249 * TTRACE_BUF_INFO 1250 * ret0 status (%o0) 1251 * ret1 RA base of buffer (%o1) 1252 * ret2 size in no. of entries (%o2) 1253 */ 1254 ENTRY(hv_ttrace_buf_info) 1255 mov %o0, %o3 1256 mov %o1, %o4 1257 mov TTRACE_BUF_INFO, %o5 1258 ta FAST_TRAP 1259 stx %o1, [%o3] 1260 retl 1261 stx %o2, [%o4] 1262 SET_SIZE(hv_ttrace_buf_info) 1263 1264 /* 1265 * TTRACE_ENABLE 1266 * arg0 enable/ disable (%o0) 1267 * ret0 status (%o0) 1268 * ret1 previous enable state (%o1) 1269 */ 1270 ENTRY(hv_ttrace_enable) 1271 mov %o1, %o2 1272 mov TTRACE_ENABLE, %o5 1273 ta FAST_TRAP 1274 retl 1275 stx %o1, [%o2] 1276 SET_SIZE(hv_ttrace_enable) 1277 1278 /* 1279 * TTRACE_FREEZE 1280 * arg0 enable/ freeze (%o0) 1281 * ret0 status (%o0) 1282 * ret1 previous freeze state (%o1) 1283 */ 1284 ENTRY(hv_ttrace_freeze) 1285 mov %o1, %o2 1286 mov TTRACE_FREEZE, %o5 1287 ta FAST_TRAP 1288 retl 1289 stx %o1, [%o2] 1290 SET_SIZE(hv_ttrace_freeze) 1291 1292 /* 1293 * MACH_DESC 1294 * arg0 buffer real address 1295 * arg1 pointer to uint64_t for size of buffer 1296 * ret0 status 1297 * ret1 return required size of buffer / returned data size 1298 */ 1299 ENTRY(hv_mach_desc) 1300 mov %o1, %o4 ! save datap 1301 ldx [%o1], %o1 1302 mov HV_MACH_DESC, %o5 1303 ta FAST_TRAP 1304 retl 1305 stx %o1, [%o4] 1306 SET_SIZE(hv_mach_desc) 1307 1308 /* 1309 * hv_ncs_request(int cmd, uint64_t realaddr, size_t sz) 1310 */ 1311 ENTRY(hv_ncs_request) 1312 mov HV_NCS_REQUEST, %o5 1313 ta FAST_TRAP 1314 retl 1315 nop 1316 SET_SIZE(hv_ncs_request) 1317#endif /* lint || __lint */ 1318