1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/machasi.h> 35#include <sys/machparam.h> 36#include <sys/hypervisor_api.h> 37 38#if defined(lint) || defined(__lint) 39 40/*ARGSUSED*/ 41uint64_t 42hv_mach_exit(uint64_t exit_code) 43{ return (0); } 44 45uint64_t 46hv_mach_sir(void) 47{ return (0); } 48 49/*ARGSUSED*/ 50uint64_t 51hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 52{ return (0); } 53 54/*ARGSUSED*/ 55uint64_t 56hv_cpu_stop(uint64_t cpuid) 57{ return (0); } 58 59/*ARGSUSED*/ 60uint64_t 61hv_cpu_set_rtba(uint64_t *rtba) 62{ return (0); } 63 64/*ARGSUSED*/ 65int64_t 66hv_cnputchar(uint8_t ch) 67{ return (0); } 68 69/*ARGSUSED*/ 70int64_t 71hv_cngetchar(uint8_t *ch) 72{ return (0); } 73 74/*ARGSUSED*/ 75uint64_t 76hv_tod_get(uint64_t *seconds) 77{ return (0); } 78 79/*ARGSUSED*/ 80uint64_t 81hv_tod_set(uint64_t seconds) 82{ return (0);} 83 84/*ARGSUSED*/ 85uint64_t 86hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 87{ return (0); } 88 89/*ARGSUSED */ 90uint64_t 91hv_mmu_fault_area_conf(void *raddr) 92{ return (0); } 93 94/*ARGSUSED*/ 95uint64_t 96hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 102{ return (0); } 103 104/*ARGSUSED*/ 105uint64_t 106hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 107{ return (0); } 108 109#ifdef SET_MMU_STATS 110/*ARGSUSED*/ 111uint64_t 112hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 113{ return (0); } 114#endif /* SET_MMU_STATS */ 115 116/*ARGSUSED*/ 117uint64_t 118hv_cpu_qconf(int queue, uint64_t paddr, int size) 119{ return (0); } 120 121/*ARGSUSED*/ 122uint64_t 123hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 124{ return (0); } 125 126/*ARGSUSED*/ 127uint64_t 128hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 129{ return (0); } 130 131/*ARGSUSED*/ 132uint64_t 133hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 134{ return (0); } 135 136/*ARGSUSED*/ 137uint64_t 138hvio_intr_getstate(uint64_t sysino, int *intr_state) 139{ return (0); } 140 141/*ARGSUSED*/ 142uint64_t 143hvio_intr_setstate(uint64_t sysino, int intr_state) 144{ return (0); } 145 146/*ARGSUSED*/ 147uint64_t 148hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 149{ return (0); } 150 151/*ARGSUSED*/ 152uint64_t 153hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 154{ return (0); } 155 156uint64_t 157hv_cpu_yield(void) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 168{ return (0); } 169 170/*ARGSUSED*/ 171uint64_t 172hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 173{ return (0); } 174 175/*ARGSUSED*/ 176uint64_t 177hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 178{ return (0); } 179 180/*ARGSUSED*/ 181uint64_t 182hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 183{ return (0); } 184 185/*ARGSUSED*/ 186uint64_t 187hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 198{ return (0); } 199 200/*ARGSUSED*/ 201uint64_t 202hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 203{ return (0); } 204 205/*ARGSUSED*/ 206uint64_t 207hv_ra2pa(uint64_t ra) 208{ return (0); } 209 210/*ARGSUSED*/ 211uint64_t 212hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 213{ return (0); } 214 215/*ARGSUSED*/ 216uint64_t 217hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 218{ return (0); } 219 220/*ARGSUSED*/ 221uint64_t 222hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 223{ return (0); } 224 225/*ARGSUSED*/ 226uint64_t 227hv_ldc_tx_get_state(uint64_t channel, 228 uint64_t *headp, uint64_t *tailp, uint64_t *state) 229{ return (0); } 230 231/*ARGSUSED*/ 232uint64_t 233hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 234{ return (0); } 235 236/*ARGSUSED*/ 237uint64_t 238hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 239{ return (0); } 240 241/*ARGSUSED*/ 242uint64_t 243hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 244{ return (0); } 245 246/*ARGSUSED*/ 247uint64_t 248hv_ldc_rx_get_state(uint64_t channel, 249 uint64_t *headp, uint64_t *tailp, uint64_t *state) 250{ return (0); } 251 252/*ARGSUSED*/ 253uint64_t 254hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 255{ return (0); } 256 257/*ARGSUSED*/ 258uint64_t 259hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 260{ return (0); } 261 262/*ARGSUSED*/ 263uint64_t 264hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 265{ return (0); } 266 267/*ARGSUSED*/ 268uint64_t 269hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 270 uint64_t raddr, uint64_t length, uint64_t *lengthp) 271{ return (0); } 272 273/*ARGSUSED*/ 274uint64_t 275hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 276{ return (0); } 277 278/*ARGSUSED*/ 279uint64_t 280hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 281{ return (0); } 282 283/*ARGSUSED*/ 284uint64_t 285hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 286{ return (0); } 287 288/*ARGSUSED*/ 289uint64_t 290hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 291{ return (0); } 292 293/*ARGSUSED*/ 294uint64_t 295hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 296{ return (0); } 297 298/*ARGSUSED*/ 299uint64_t 300hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 301{ return (0); } 302 303/*ARGSUSED*/ 304uint64_t 305hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 306{ return (0); } 307 308/*ARGSUSED*/ 309uint64_t 310hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 311{ return (0); } 312 313/*ARGSUSED*/ 314uint64_t 315hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 316{ return (0); } 317 318/*ARGSUSED*/ 319uint64_t 320hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 321 uint64_t *supported_minor) 322{ return (0); } 323 324/*ARGSUSED*/ 325uint64_t 326hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 327{ return (0); } 328 329#else /* lint || __lint */ 330 331 /* 332 * int hv_mach_exit(uint64_t exit_code) 333 */ 334 ENTRY(hv_mach_exit) 335 mov HV_MACH_EXIT, %o5 336 ta FAST_TRAP 337 retl 338 nop 339 SET_SIZE(hv_mach_exit) 340 341 /* 342 * uint64_t hv_mach_sir(void) 343 */ 344 ENTRY(hv_mach_sir) 345 mov HV_MACH_SIR, %o5 346 ta FAST_TRAP 347 retl 348 nop 349 SET_SIZE(hv_mach_sir) 350 351 /* 352 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 353 * uint64_t arg) 354 */ 355 ENTRY(hv_cpu_start) 356 mov HV_CPU_START, %o5 357 ta FAST_TRAP 358 retl 359 nop 360 SET_SIZE(hv_cpu_start) 361 362 /* 363 * hv_cpu_stop(uint64_t cpuid) 364 */ 365 ENTRY(hv_cpu_stop) 366 mov HV_CPU_STOP, %o5 367 ta FAST_TRAP 368 retl 369 nop 370 SET_SIZE(hv_cpu_stop) 371 372 /* 373 * hv_cpu_set_rtba(uint64_t *rtba) 374 */ 375 ENTRY(hv_cpu_set_rtba) 376 mov %o0, %o2 377 ldx [%o2], %o0 378 mov HV_CPU_SET_RTBA, %o5 379 ta FAST_TRAP 380 stx %o1, [%o2] 381 retl 382 nop 383 SET_SIZE(hv_cpu_set_rtba) 384 385 /* 386 * int64_t hv_cnputchar(uint8_t ch) 387 */ 388 ENTRY(hv_cnputchar) 389 mov CONS_PUTCHAR, %o5 390 ta FAST_TRAP 391 retl 392 nop 393 SET_SIZE(hv_cnputchar) 394 395 /* 396 * int64_t hv_cngetchar(uint8_t *ch) 397 */ 398 ENTRY(hv_cngetchar) 399 mov %o0, %o2 400 mov CONS_GETCHAR, %o5 401 ta FAST_TRAP 402 brnz,a %o0, 1f ! failure, just return error 403 nop 404 405 cmp %o1, H_BREAK 406 be 1f 407 mov %o1, %o0 408 409 cmp %o1, H_HUP 410 be 1f 411 mov %o1, %o0 412 413 stb %o1, [%o2] ! success, save character and return 0 414 mov 0, %o0 4151: 416 retl 417 nop 418 SET_SIZE(hv_cngetchar) 419 420 ENTRY(hv_tod_get) 421 mov %o0, %o4 422 mov TOD_GET, %o5 423 ta FAST_TRAP 424 retl 425 stx %o1, [%o4] 426 SET_SIZE(hv_tod_get) 427 428 ENTRY(hv_tod_set) 429 mov TOD_SET, %o5 430 ta FAST_TRAP 431 retl 432 nop 433 SET_SIZE(hv_tod_set) 434 435 /* 436 * Map permanent address 437 * arg0 vaddr (%o0) 438 * arg1 context (%o1) 439 * arg2 tte (%o2) 440 * arg3 flags (%o3) 0x1=d 0x2=i 441 */ 442 ENTRY(hv_mmu_map_perm_addr) 443 mov MAP_PERM_ADDR, %o5 444 ta FAST_TRAP 445 retl 446 nop 447 SET_SIZE(hv_mmu_map_perm_addr) 448 449 /* 450 * hv_mmu_fault_area_conf(void *raddr) 451 */ 452 ENTRY(hv_mmu_fault_area_conf) 453 mov %o0, %o2 454 ldx [%o2], %o0 455 mov MMU_SET_INFOPTR, %o5 456 ta FAST_TRAP 457 stx %o1, [%o2] 458 retl 459 nop 460 SET_SIZE(hv_mmu_fault_area_conf) 461 462 /* 463 * Unmap permanent address 464 * arg0 vaddr (%o0) 465 * arg1 context (%o1) 466 * arg2 flags (%o2) 0x1=d 0x2=i 467 */ 468 ENTRY(hv_mmu_unmap_perm_addr) 469 mov UNMAP_PERM_ADDR, %o5 470 ta FAST_TRAP 471 retl 472 nop 473 SET_SIZE(hv_mmu_unmap_perm_addr) 474 475 /* 476 * Set TSB for context 0 477 * arg0 ntsb_descriptor (%o0) 478 * arg1 desc_ra (%o1) 479 */ 480 ENTRY(hv_set_ctx0) 481 mov MMU_TSB_CTX0, %o5 482 ta FAST_TRAP 483 retl 484 nop 485 SET_SIZE(hv_set_ctx0) 486 487 /* 488 * Set TSB for context non0 489 * arg0 ntsb_descriptor (%o0) 490 * arg1 desc_ra (%o1) 491 */ 492 ENTRY(hv_set_ctxnon0) 493 mov MMU_TSB_CTXNON0, %o5 494 ta FAST_TRAP 495 retl 496 nop 497 SET_SIZE(hv_set_ctxnon0) 498 499#ifdef SET_MMU_STATS 500 /* 501 * Returns old stat area on success 502 */ 503 ENTRY(hv_mmu_set_stat_area) 504 mov MMU_STAT_AREA, %o5 505 ta FAST_TRAP 506 retl 507 nop 508 SET_SIZE(hv_mmu_set_stat_area) 509#endif /* SET_MMU_STATS */ 510 511 /* 512 * CPU Q Configure 513 * arg0 queue (%o0) 514 * arg1 Base address RA (%o1) 515 * arg2 Size (%o2) 516 */ 517 ENTRY(hv_cpu_qconf) 518 mov HV_CPU_QCONF, %o5 519 ta FAST_TRAP 520 retl 521 nop 522 SET_SIZE(hv_cpu_qconf) 523 524 /* 525 * arg0 - devhandle 526 * arg1 - devino 527 * 528 * ret0 - status 529 * ret1 - sysino 530 */ 531 ENTRY(hvio_intr_devino_to_sysino) 532 mov HVIO_INTR_DEVINO2SYSINO, %o5 533 ta FAST_TRAP 534 brz,a %o0, 1f 535 stx %o1, [%o2] 5361: retl 537 nop 538 SET_SIZE(hvio_intr_devino_to_sysino) 539 540 /* 541 * arg0 - sysino 542 * 543 * ret0 - status 544 * ret1 - intr_valid_state 545 */ 546 ENTRY(hvio_intr_getvalid) 547 mov %o1, %o2 548 mov HVIO_INTR_GETVALID, %o5 549 ta FAST_TRAP 550 brz,a %o0, 1f 551 stuw %o1, [%o2] 5521: retl 553 nop 554 SET_SIZE(hvio_intr_getvalid) 555 556 /* 557 * arg0 - sysino 558 * arg1 - intr_valid_state 559 * 560 * ret0 - status 561 */ 562 ENTRY(hvio_intr_setvalid) 563 mov HVIO_INTR_SETVALID, %o5 564 ta FAST_TRAP 565 retl 566 nop 567 SET_SIZE(hvio_intr_setvalid) 568 569 /* 570 * arg0 - sysino 571 * 572 * ret0 - status 573 * ret1 - intr_state 574 */ 575 ENTRY(hvio_intr_getstate) 576 mov %o1, %o2 577 mov HVIO_INTR_GETSTATE, %o5 578 ta FAST_TRAP 579 brz,a %o0, 1f 580 stuw %o1, [%o2] 5811: retl 582 nop 583 SET_SIZE(hvio_intr_getstate) 584 585 /* 586 * arg0 - sysino 587 * arg1 - intr_state 588 * 589 * ret0 - status 590 */ 591 ENTRY(hvio_intr_setstate) 592 mov HVIO_INTR_SETSTATE, %o5 593 ta FAST_TRAP 594 retl 595 nop 596 SET_SIZE(hvio_intr_setstate) 597 598 /* 599 * arg0 - sysino 600 * 601 * ret0 - status 602 * ret1 - cpu_id 603 */ 604 ENTRY(hvio_intr_gettarget) 605 mov %o1, %o2 606 mov HVIO_INTR_GETTARGET, %o5 607 ta FAST_TRAP 608 brz,a %o0, 1f 609 stuw %o1, [%o2] 6101: retl 611 nop 612 SET_SIZE(hvio_intr_gettarget) 613 614 /* 615 * arg0 - sysino 616 * arg1 - cpu_id 617 * 618 * ret0 - status 619 */ 620 ENTRY(hvio_intr_settarget) 621 mov HVIO_INTR_SETTARGET, %o5 622 ta FAST_TRAP 623 retl 624 nop 625 SET_SIZE(hvio_intr_settarget) 626 627 /* 628 * hv_cpu_yield(void) 629 */ 630 ENTRY(hv_cpu_yield) 631 mov HV_CPU_YIELD, %o5 632 ta FAST_TRAP 633 retl 634 nop 635 SET_SIZE(hv_cpu_yield) 636 637 /* 638 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 639 */ 640 ENTRY(hv_cpu_state) 641 mov %o1, %o4 ! save datap 642 mov HV_CPU_STATE, %o5 643 ta FAST_TRAP 644 brz,a %o0, 1f 645 stx %o1, [%o4] 6461: 647 retl 648 nop 649 SET_SIZE(hv_cpu_state) 650 651 /* 652 * HV state dump zone Configure 653 * arg0 real adrs of dump buffer (%o0) 654 * arg1 size of dump buffer (%o1) 655 * ret0 status (%o0) 656 * ret1 size of buffer on success and min size on EINVAL (%o1) 657 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 658 */ 659 ENTRY(hv_dump_buf_update) 660 mov DUMP_BUF_UPDATE, %o5 661 ta FAST_TRAP 662 retl 663 stx %o1, [%o2] 664 SET_SIZE(hv_dump_buf_update) 665 666 /* 667 * arg0 - timeout value (%o0) 668 * 669 * ret0 - status (%o0) 670 * ret1 - time_remaining (%o1) 671 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 672 */ 673 ENTRY(hv_mach_set_watchdog) 674 mov %o1, %o2 675 mov MACH_SET_WATCHDOG, %o5 676 ta FAST_TRAP 677 retl 678 stx %o1, [%o2] 679 SET_SIZE(hv_mach_set_watchdog) 680 681 /* 682 * For memory scrub 683 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 684 * uint64_t *scrubbed_len); 685 * Retun %o0 -- status 686 * %o1 -- bytes scrubbed 687 */ 688 ENTRY(hv_mem_scrub) 689 mov %o2, %o4 690 mov HV_MEM_SCRUB, %o5 691 ta FAST_TRAP 692 retl 693 stx %o1, [%o4] 694 SET_SIZE(hv_mem_scrub) 695 696 /* 697 * Flush ecache 698 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 699 * uint64_t *flushed_len); 700 * Retun %o0 -- status 701 * %o1 -- bytes flushed 702 */ 703 ENTRY(hv_mem_sync) 704 mov %o2, %o4 705 mov HV_MEM_SYNC, %o5 706 ta FAST_TRAP 707 retl 708 stx %o1, [%o4] 709 SET_SIZE(hv_mem_sync) 710 711 /* 712 * TTRACE_BUF_CONF Configure 713 * arg0 RA base of buffer (%o0) 714 * arg1 buf size in no. of entries (%o1) 715 * ret0 status (%o0) 716 * ret1 minimum size in no. of entries on failure, 717 * actual size in no. of entries on success (%o1) 718 */ 719 ENTRY(hv_ttrace_buf_conf) 720 mov TTRACE_BUF_CONF, %o5 721 ta FAST_TRAP 722 retl 723 stx %o1, [%o2] 724 SET_SIZE(hv_ttrace_buf_conf) 725 726 /* 727 * TTRACE_BUF_INFO 728 * ret0 status (%o0) 729 * ret1 RA base of buffer (%o1) 730 * ret2 size in no. of entries (%o2) 731 */ 732 ENTRY(hv_ttrace_buf_info) 733 mov %o0, %o3 734 mov %o1, %o4 735 mov TTRACE_BUF_INFO, %o5 736 ta FAST_TRAP 737 stx %o1, [%o3] 738 retl 739 stx %o2, [%o4] 740 SET_SIZE(hv_ttrace_buf_info) 741 742 /* 743 * TTRACE_ENABLE 744 * arg0 enable/ disable (%o0) 745 * ret0 status (%o0) 746 * ret1 previous enable state (%o1) 747 */ 748 ENTRY(hv_ttrace_enable) 749 mov %o1, %o2 750 mov TTRACE_ENABLE, %o5 751 ta FAST_TRAP 752 retl 753 stx %o1, [%o2] 754 SET_SIZE(hv_ttrace_enable) 755 756 /* 757 * TTRACE_FREEZE 758 * arg0 enable/ freeze (%o0) 759 * ret0 status (%o0) 760 * ret1 previous freeze state (%o1) 761 */ 762 ENTRY(hv_ttrace_freeze) 763 mov %o1, %o2 764 mov TTRACE_FREEZE, %o5 765 ta FAST_TRAP 766 retl 767 stx %o1, [%o2] 768 SET_SIZE(hv_ttrace_freeze) 769 770 /* 771 * MACH_DESC 772 * arg0 buffer real address 773 * arg1 pointer to uint64_t for size of buffer 774 * ret0 status 775 * ret1 return required size of buffer / returned data size 776 */ 777 ENTRY(hv_mach_desc) 778 mov %o1, %o4 ! save datap 779 ldx [%o1], %o1 780 mov HV_MACH_DESC, %o5 781 ta FAST_TRAP 782 retl 783 stx %o1, [%o4] 784 SET_SIZE(hv_mach_desc) 785 786 /* 787 * hv_ra2pa(uint64_t ra) 788 * 789 * MACH_DESC 790 * arg0 Real address to convert 791 * ret0 Returned physical address or -1 on error 792 */ 793 ENTRY(hv_ra2pa) 794 mov HV_RA2PA, %o5 795 ta FAST_TRAP 796 cmp %o0, 0 797 move %xcc, %o1, %o0 798 movne %xcc, -1, %o0 799 retl 800 nop 801 SET_SIZE(hv_ra2pa) 802 803 /* 804 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 805 * 806 * MACH_DESC 807 * arg0 OS function to call 808 * arg1 First arg to OS function 809 * arg2 Second arg to OS function 810 * arg3 Third arg to OS function 811 * ret0 Returned value from function 812 */ 813 814 ENTRY(hv_hpriv) 815 mov HV_HPRIV, %o5 816 ta FAST_TRAP 817 retl 818 nop 819 SET_SIZE(hv_hpriv) 820 821 /* 822 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 823 * uint64_t nentries); 824 */ 825 ENTRY(hv_ldc_tx_qconf) 826 mov LDC_TX_QCONF, %o5 827 ta FAST_TRAP 828 retl 829 nop 830 SET_SIZE(hv_ldc_tx_qconf) 831 832 833 /* 834 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 835 * uint64_t *nentries); 836 */ 837 ENTRY(hv_ldc_tx_qinfo) 838 mov %o1, %g1 839 mov %o2, %g2 840 mov LDC_TX_QINFO, %o5 841 ta FAST_TRAP 842 stx %o1, [%g1] 843 retl 844 stx %o2, [%g2] 845 SET_SIZE(hv_ldc_tx_qinfo) 846 847 848 /* 849 * hv_ldc_tx_get_state(uint64_t channel, 850 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 851 */ 852 ENTRY(hv_ldc_tx_get_state) 853 mov LDC_TX_GET_STATE, %o5 854 mov %o1, %g1 855 mov %o2, %g2 856 mov %o3, %g3 857 ta FAST_TRAP 858 stx %o1, [%g1] 859 stx %o2, [%g2] 860 retl 861 stx %o3, [%g3] 862 SET_SIZE(hv_ldc_tx_get_state) 863 864 865 /* 866 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 867 */ 868 ENTRY(hv_ldc_tx_set_qtail) 869 mov LDC_TX_SET_QTAIL, %o5 870 ta FAST_TRAP 871 retl 872 SET_SIZE(hv_ldc_tx_set_qtail) 873 874 875 /* 876 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 877 * uint64_t nentries); 878 */ 879 ENTRY(hv_ldc_rx_qconf) 880 mov LDC_RX_QCONF, %o5 881 ta FAST_TRAP 882 retl 883 nop 884 SET_SIZE(hv_ldc_rx_qconf) 885 886 887 /* 888 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 889 * uint64_t *nentries); 890 */ 891 ENTRY(hv_ldc_rx_qinfo) 892 mov %o1, %g1 893 mov %o2, %g2 894 mov LDC_RX_QINFO, %o5 895 ta FAST_TRAP 896 stx %o1, [%g1] 897 retl 898 stx %o2, [%g2] 899 SET_SIZE(hv_ldc_rx_qinfo) 900 901 902 /* 903 * hv_ldc_rx_get_state(uint64_t channel, 904 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 905 */ 906 ENTRY(hv_ldc_rx_get_state) 907 mov LDC_RX_GET_STATE, %o5 908 mov %o1, %g1 909 mov %o2, %g2 910 mov %o3, %g3 911 ta FAST_TRAP 912 stx %o1, [%g1] 913 stx %o2, [%g2] 914 retl 915 stx %o3, [%g3] 916 SET_SIZE(hv_ldc_rx_get_state) 917 918 919 /* 920 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 921 */ 922 ENTRY(hv_ldc_rx_set_qhead) 923 mov LDC_RX_SET_QHEAD, %o5 924 ta FAST_TRAP 925 retl 926 SET_SIZE(hv_ldc_rx_set_qhead) 927 928 /* 929 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 930 * uint64_t tbl_entries) 931 */ 932 ENTRY(hv_ldc_set_map_table) 933 mov LDC_SET_MAP_TABLE, %o5 934 ta FAST_TRAP 935 retl 936 nop 937 SET_SIZE(hv_ldc_set_map_table) 938 939 940 /* 941 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 942 * uint64_t *tbl_entries) 943 */ 944 ENTRY(hv_ldc_get_map_table) 945 mov %o1, %g1 946 mov %o2, %g2 947 mov LDC_GET_MAP_TABLE, %o5 948 ta FAST_TRAP 949 stx %o1, [%g1] 950 retl 951 stx %o2, [%g2] 952 SET_SIZE(hv_ldc_get_map_table) 953 954 955 /* 956 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 957 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 958 */ 959 ENTRY(hv_ldc_copy) 960 mov %o5, %g1 961 mov LDC_COPY, %o5 962 ta FAST_TRAP 963 retl 964 stx %o1, [%g1] 965 SET_SIZE(hv_ldc_copy) 966 967 968 /* 969 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 970 * uint64_t *perm) 971 */ 972 ENTRY(hv_ldc_mapin) 973 mov %o2, %g1 974 mov %o3, %g2 975 mov LDC_MAPIN, %o5 976 ta FAST_TRAP 977 stx %o1, [%g1] 978 retl 979 stx %o2, [%g2] 980 SET_SIZE(hv_ldc_mapin) 981 982 983 /* 984 * hv_ldc_unmap(uint64_t raddr) 985 */ 986 ENTRY(hv_ldc_unmap) 987 mov LDC_UNMAP, %o5 988 ta FAST_TRAP 989 retl 990 nop 991 SET_SIZE(hv_ldc_unmap) 992 993 994 /* 995 * hv_ldc_revoke(uint64_t raddr) 996 */ 997 ENTRY(hv_ldc_revoke) 998 mov LDC_REVOKE, %o5 999 ta FAST_TRAP 1000 retl 1001 nop 1002 SET_SIZE(hv_ldc_revoke) 1003 1004 1005 /* 1006 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1007 * uint64_t *cookie); 1008 */ 1009 ENTRY(hvldc_intr_getcookie) 1010 mov %o2, %g1 1011 mov VINTR_GET_COOKIE, %o5 1012 ta FAST_TRAP 1013 retl 1014 stx %o1, [%g1] 1015 SET_SIZE(hvldc_intr_getcookie) 1016 1017 /* 1018 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1019 * uint64_t cookie); 1020 */ 1021 ENTRY(hvldc_intr_setcookie) 1022 mov VINTR_SET_COOKIE, %o5 1023 ta FAST_TRAP 1024 retl 1025 nop 1026 SET_SIZE(hvldc_intr_setcookie) 1027 1028 1029 /* 1030 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1031 * int *intr_valid_state); 1032 */ 1033 ENTRY(hvldc_intr_getvalid) 1034 mov %o2, %g1 1035 mov VINTR_GET_VALID, %o5 1036 ta FAST_TRAP 1037 retl 1038 stuw %o1, [%g1] 1039 SET_SIZE(hvldc_intr_getvalid) 1040 1041 /* 1042 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1043 * int intr_valid_state); 1044 */ 1045 ENTRY(hvldc_intr_setvalid) 1046 mov VINTR_SET_VALID, %o5 1047 ta FAST_TRAP 1048 retl 1049 nop 1050 SET_SIZE(hvldc_intr_setvalid) 1051 1052 /* 1053 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1054 * int *intr_state); 1055 */ 1056 ENTRY(hvldc_intr_getstate) 1057 mov %o2, %g1 1058 mov VINTR_GET_STATE, %o5 1059 ta FAST_TRAP 1060 retl 1061 stuw %o1, [%g1] 1062 SET_SIZE(hvldc_intr_getstate) 1063 1064 /* 1065 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1066 * int intr_state); 1067 */ 1068 ENTRY(hvldc_intr_setstate) 1069 mov VINTR_SET_STATE, %o5 1070 ta FAST_TRAP 1071 retl 1072 nop 1073 SET_SIZE(hvldc_intr_setstate) 1074 1075 /* 1076 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1077 * uint32_t *cpuid); 1078 */ 1079 ENTRY(hvldc_intr_gettarget) 1080 mov %o2, %g1 1081 mov VINTR_GET_TARGET, %o5 1082 ta FAST_TRAP 1083 retl 1084 stuw %o1, [%g1] 1085 SET_SIZE(hvldc_intr_gettarget) 1086 1087 /* 1088 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1089 * uint32_t cpuid); 1090 */ 1091 ENTRY(hvldc_intr_settarget) 1092 mov VINTR_SET_TARGET, %o5 1093 ta FAST_TRAP 1094 retl 1095 nop 1096 SET_SIZE(hvldc_intr_settarget) 1097 1098 /* 1099 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1100 * uint64_t *minorp) 1101 * 1102 * API_GET_VERSION 1103 * arg0 API group 1104 * ret0 status 1105 * ret1 major number 1106 * ret2 minor number 1107 */ 1108 ENTRY(hv_api_get_version) 1109 mov %o1, %o3 1110 mov %o2, %o4 1111 mov API_GET_VERSION, %o5 1112 ta CORE_TRAP 1113 stx %o1, [%o3] 1114 retl 1115 stx %o2, [%o4] 1116 SET_SIZE(hv_api_get_version) 1117 1118 /* 1119 * hv_api_set_version(uint64_t api_group, uint64_t major, 1120 * uint64_t minor, uint64_t *supported_minor) 1121 * 1122 * API_SET_VERSION 1123 * arg0 API group 1124 * arg1 major number 1125 * arg2 requested minor number 1126 * ret0 status 1127 * ret1 actual minor number 1128 */ 1129 ENTRY(hv_api_set_version) 1130 mov %o3, %o4 1131 mov API_SET_VERSION, %o5 1132 ta CORE_TRAP 1133 retl 1134 stx %o1, [%o4] 1135 SET_SIZE(hv_api_set_version) 1136 1137#endif /* lint || __lint */ 1138