1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_LIB4V_H 28 #define _SYS_PX_LIB4V_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * SUN4V IO API - Version 1.11 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * The device handle uniquely identifies a SUN4V device. 42 * It consists of the lower 28-bits of the hi-cell of the 43 * first entry of the SUN4V device's "reg" property as 44 * defined by the SUN4V Bus Binding to Open Firmware. 45 */ 46 #define DEVHDLE_MASK 0xFFFFFFF 47 48 extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 49 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 50 extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 51 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 52 53 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 54 pages_t pages, io_attributes_t io_attributes, 55 io_page_list_t *io_page_list_p, pages_t *pages_mapped); 56 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 57 pages_t pages, pages_t *pages_demapped); 58 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 59 io_attributes_t *attributes_p, r_addr_t *r_addr_p); 60 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 61 io_attributes_t io_attributes, io_addr_t *io_addr_p); 62 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 63 size_t num_bytes, io_sync_direction_t io_sync_direction, 64 size_t *bytes_synched); 65 66 /* 67 * MSIQ Functions: 68 */ 69 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 70 r_addr_t ra, uint_t msiq_rec_cnt); 71 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 72 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 73 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 74 pci_msiq_valid_state_t *msiq_valid_state); 75 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 76 pci_msiq_valid_state_t msiq_valid_state); 77 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 78 pci_msiq_state_t *msiq_state); 79 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 80 pci_msiq_state_t msiq_state); 81 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 82 msiqhead_t *msiq_head); 83 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 84 msiqhead_t msiq_head); 85 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 86 msiqtail_t *msiq_tail); 87 88 /* 89 * MSI Functions: 90 */ 91 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 92 msiqid_t *msiq_id); 93 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 94 msiqid_t msiq_id, msi_type_t msitype); 95 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 96 pci_msi_valid_state_t *msi_valid_state); 97 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 98 pci_msi_valid_state_t msi_valid_state); 99 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 100 pci_msi_state_t *msi_state); 101 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 102 pci_msi_state_t msi_state); 103 104 /* 105 * MSG Functions: 106 */ 107 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 108 msiqid_t *msiq_id); 109 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 110 msiqid_t msiq_id); 111 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 112 pcie_msg_valid_state_t *msg_valid_state); 113 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 114 pcie_msg_valid_state_t msg_valid_state); 115 116 typedef struct px_config_acc_pvt { 117 dev_info_t *dip; 118 uint32_t raddr; 119 uint32_t vaddr; 120 } px_config_acc_pvt_t; 121 122 /* 123 * Peek/poke functionality: 124 */ 125 126 extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 127 uint32_t *status, uint64_t *data_p); 128 extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 129 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 130 131 #ifdef __cplusplus 132 } 133 #endif 134 135 #endif /* _SYS_PX_LIB4V_H */ 136