1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4V_H 27 #define _SYS_PX_LIB4V_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Fasttrap numbers for VPCI hypervisor functions. 37 */ 38 39 #define HVIO_IOMMU_MAP 0xb0 40 #define HVIO_IOMMU_DEMAP 0xb1 41 #define HVIO_IOMMU_GETMAP 0xb2 42 #define HVIO_IOMMU_GETBYPASS 0xb3 43 44 #define HVIO_CONFIG_GET 0xb4 45 #define HVIO_CONFIG_PUT 0xb5 46 47 #define HVIO_PEEK 0xb6 48 #define HVIO_POKE 0xb7 49 50 #define HVIO_DMA_SYNC 0xb8 51 52 #define HVIO_MSIQ_CONF 0xc0 53 #define HVIO_MSIQ_INFO 0xc1 54 #define HVIO_MSIQ_GETVALID 0xc2 55 #define HVIO_MSIQ_SETVALID 0xc3 56 #define HVIO_MSIQ_GETSTATE 0xc4 57 #define HVIO_MSIQ_SETSTATE 0xc5 58 #define HVIO_MSIQ_GETHEAD 0xc6 59 #define HVIO_MSIQ_SETHEAD 0xc7 60 #define HVIO_MSIQ_GETTAIL 0xc8 61 62 #define HVIO_MSI_GETVALID 0xc9 63 #define HVIO_MSI_SETVALID 0xca 64 #define HVIO_MSI_GETMSIQ 0xcb 65 #define HVIO_MSI_SETMSIQ 0xcc 66 #define HVIO_MSI_GETSTATE 0xcd 67 #define HVIO_MSI_SETSTATE 0xce 68 69 #define HVIO_MSG_GETMSIQ 0xd0 70 #define HVIO_MSG_SETMSIQ 0xd1 71 #define HVIO_MSG_GETVALID 0xd2 72 #define HVIO_MSG_SETVALID 0xd3 73 74 #ifndef _ASM 75 76 /* 77 * The device handle uniquely identifies a SUN4V device. 78 * It consists of the lower 28-bits of the hi-cell of the 79 * first entry of the SUN4V device's "reg" property as 80 * defined by the SUN4V Bus Binding to Open Firmware. 81 */ 82 #define DEVHDLE_MASK 0xFFFFFFF 83 84 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 85 #define PX_RA_BDF_SHIFT 8 86 87 #define PX_ADDR2PFN(addr, index, flags, i) \ 88 ((flags & MMU_MAP_PFN) ? \ 89 PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \ 90 hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i)))) 91 92 /* 93 * VPCI API versioning. 94 * 95 * Currently PX nexus driver supports VPCI API version 1.0 96 */ 97 #define PX_VPCI_MAJOR_VER_1 0x1ull 98 #define PX_VPCI_MAJOR_VER PX_VPCI_MAJOR_VER_1 99 100 #define PX_VPCI_MINOR_VER_0 0x0ull 101 #define PX_VPCI_MINOR_VER PX_VPCI_MINOR_VER_0 102 103 extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 104 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 105 extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 106 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 107 108 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 109 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, 110 pages_t *pages_mapped); 111 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 112 pages_t pages, pages_t *pages_demapped); 113 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 114 io_attributes_t *attr_p, r_addr_t *r_addr_p); 115 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 116 io_attributes_t attr, io_addr_t *io_addr_p); 117 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 118 size_t num_bytes, io_sync_direction_t io_sync_direction, 119 size_t *bytes_synched); 120 121 /* 122 * MSIQ Functions: 123 */ 124 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 125 r_addr_t ra, uint_t msiq_rec_cnt); 126 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 127 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 128 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 129 pci_msiq_valid_state_t *msiq_valid_state); 130 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 131 pci_msiq_valid_state_t msiq_valid_state); 132 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 133 pci_msiq_state_t *msiq_state); 134 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 135 pci_msiq_state_t msiq_state); 136 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 137 msiqhead_t *msiq_head); 138 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 139 msiqhead_t msiq_head); 140 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 141 msiqtail_t *msiq_tail); 142 143 /* 144 * MSI Functions: 145 */ 146 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 147 msiqid_t *msiq_id); 148 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 149 msiqid_t msiq_id, msi_type_t msitype); 150 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 151 pci_msi_valid_state_t *msi_valid_state); 152 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 153 pci_msi_valid_state_t msi_valid_state); 154 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 155 pci_msi_state_t *msi_state); 156 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 157 pci_msi_state_t msi_state); 158 159 /* 160 * MSG Functions: 161 */ 162 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 163 msiqid_t *msiq_id); 164 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 165 msiqid_t msiq_id); 166 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 167 pcie_msg_valid_state_t *msg_valid_state); 168 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 169 pcie_msg_valid_state_t msg_valid_state); 170 171 typedef struct px_config_acc_pvt { 172 dev_info_t *dip; 173 uint32_t raddr; 174 uint32_t vaddr; 175 } px_config_acc_pvt_t; 176 177 /* 178 * Peek/poke functionality: 179 */ 180 181 extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 182 uint32_t *status, uint64_t *data_p); 183 extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 184 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 185 186 /* 187 * Priviledged physical access: 188 */ 189 extern uint64_t hv_ra2pa(uint64_t ra); 190 extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 191 uint64_t arg3); 192 extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); 193 194 #endif /* _ASM */ 195 196 #ifdef __cplusplus 197 } 198 #endif 199 200 #endif /* _SYS_PX_LIB4V_H */ 201