1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #include <sys/types.h> 26 #include <sys/sysmacros.h> 27 #include <sys/ddi.h> 28 #include <sys/async.h> 29 #include <sys/sunddi.h> 30 #include <sys/ddifm.h> 31 #include <sys/fm/protocol.h> 32 #include <sys/vmem.h> 33 #include <sys/intr.h> 34 #include <sys/ivintr.h> 35 #include <sys/errno.h> 36 #include <sys/hypervisor_api.h> 37 #include <sys/hsvc.h> 38 #include <px_obj.h> 39 #include <sys/machsystm.h> 40 #include <sys/sunndi.h> 41 #include <sys/pcie_impl.h> 42 #include "px_lib4v.h" 43 #include "px_err.h" 44 #include <sys/pci_cfgacc.h> 45 #include <sys/pci_cfgacc_4v.h> 46 47 48 /* mask for the ranges property in calculating the real PFN range */ 49 uint_t px_ranges_phi_mask = ((1 << 28) -1); 50 51 /* 52 * Hypervisor VPCI services information for the px nexus driver. 53 */ 54 static uint64_t px_vpci_maj_ver; /* Negotiated VPCI API major version */ 55 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 56 static uint_t px_vpci_users = 0; /* VPCI API users */ 57 static hsvc_info_t px_hsvc_vpci = { 58 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 59 PX_VPCI_MINOR_VER, "PX" 60 }; 61 62 /* 63 * Hypervisor SDIO services information for the px nexus driver. 64 */ 65 static uint64_t px_sdio_min_ver; /* Negotiated SDIO API minor version */ 66 static uint_t px_sdio_users = 0; /* SDIO API users */ 67 static hsvc_info_t px_hsvc_sdio = { 68 HSVC_REV_1, NULL, HSVC_GROUP_SDIO, PX_SDIO_MAJOR_VER, 69 PX_SDIO_MINOR_VER, "PX" 70 }; 71 72 /* 73 * Hypervisor SDIO ERR services information for the px nexus driver. 74 */ 75 static uint64_t px_sdio_err_min_ver; /* Negotiated SDIO ERR API */ 76 /* minor version */ 77 static uint_t px_sdio_err_users = 0; /* SDIO ERR API users */ 78 static hsvc_info_t px_hsvc_sdio_err = { 79 HSVC_REV_1, NULL, HSVC_GROUP_SDIO_ERR, PX_SDIO_ERR_MAJOR_VER, 80 PX_SDIO_ERR_MINOR_VER, "PX" 81 }; 82 83 #define CHILD_LOANED "child_loaned" 84 static int px_lib_count_waiting_dev(dev_info_t *); 85 86 int 87 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 88 { 89 px_nexus_regspec_t *rp; 90 uint_t reglen; 91 int ret; 92 px_t *px_p = DIP_TO_STATE(dip); 93 uint64_t mjrnum; 94 uint64_t mnrnum; 95 96 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 97 98 /* 99 * Check HV intr group api versioning. 100 * This driver uses the old interrupt routines which are supported 101 * in old firmware in the CORE API group and in newer firmware in 102 * the INTR API group. Support for these calls will be dropped 103 * once the INTR API group major goes to 2. 104 */ 105 if ((hsvc_version(HSVC_GROUP_INTR, &mjrnum, &mnrnum) == 0) && 106 (mjrnum > 1)) { 107 cmn_err(CE_WARN, "px: unsupported intr api group: " 108 "maj:0x%lx, min:0x%lx", mjrnum, mnrnum); 109 return (ENOTSUP); 110 } 111 112 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 113 "reg", (uchar_t **)&rp, ®len); 114 if (ret != DDI_PROP_SUCCESS) { 115 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 116 return (DDI_FAILURE); 117 } 118 119 /* 120 * Initilize device handle. The device handle uniquely identifies 121 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 122 * of the first entry of the SUN4V device's "reg" property as 123 * defined by the SUN4V Bus Binding to Open Firmware. 124 */ 125 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 126 ddi_prop_free(rp); 127 128 /* 129 * hotplug implementation requires this property to be associated with 130 * any indirect PCI config access services 131 */ 132 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 133 PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR)), dip, 134 PCI_BUS_CONF_MAP_PROP, 1); 135 136 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 137 138 /* 139 * If a /pci node has a pci-intx-not-supported property, this property 140 * represents that the fabric doesn't support fixed interrupt. 141 */ 142 if (!ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 143 "pci-intx-not-supported")) { 144 DBG(DBG_ATTACH, dip, "px_lib_dev_init: " 145 "pci-intx-not-supported is not found, dip=0x%p\n", dip); 146 px_p->px_supp_intr_types |= DDI_INTR_TYPE_FIXED; 147 } 148 149 /* 150 * Negotiate the API version for VPCI hypervisor services. 151 */ 152 if (px_vpci_users == 0) { 153 if ((ret = hsvc_register(&px_hsvc_vpci, &px_vpci_min_ver)) 154 == 0) { 155 px_vpci_maj_ver = px_hsvc_vpci.hsvc_major; 156 goto hv_negotiation_complete; 157 } 158 /* 159 * Negotiation with the latest known VPCI hypervisor services 160 * failed. Fallback to version 1.0. 161 */ 162 px_hsvc_vpci.hsvc_major = PX_HSVC_MAJOR_VER_1; 163 px_hsvc_vpci.hsvc_minor = PX_HSVC_MINOR_VER_0; 164 165 if ((ret = hsvc_register(&px_hsvc_vpci, &px_vpci_min_ver)) 166 == 0) { 167 px_vpci_maj_ver = px_hsvc_vpci.hsvc_major; 168 goto hv_negotiation_complete; 169 } 170 171 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 172 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 173 px_hsvc_vpci.hsvc_modname, px_hsvc_vpci.hsvc_group, 174 px_hsvc_vpci.hsvc_major, px_hsvc_vpci.hsvc_minor, ret); 175 176 return (DDI_FAILURE); 177 } 178 hv_negotiation_complete: 179 180 px_vpci_users++; 181 182 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 183 "major 0x%lx minor 0x%lx\n", px_vpci_maj_ver, 184 px_vpci_min_ver); 185 186 /* 187 * Negotiate the API version for SDIO hypervisor services. 188 */ 189 if ((px_sdio_users == 0) && 190 ((ret = hsvc_register(&px_hsvc_sdio, &px_sdio_min_ver)) != 0)) { 191 DBG(DBG_ATTACH, dip, "%s: cannot negotiate hypervisor " 192 "services group: 0x%lx major: 0x%lx minor: 0x%lx " 193 "errno: %d\n", px_hsvc_sdio.hsvc_modname, 194 px_hsvc_sdio.hsvc_group, px_hsvc_sdio.hsvc_major, 195 px_hsvc_sdio.hsvc_minor, ret); 196 } else { 197 px_sdio_users++; 198 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO API" 199 "version, major 0x%lx minor 0x%lx\n", 200 px_hsvc_sdio.hsvc_major, px_sdio_min_ver); 201 } 202 203 /* 204 * Negotiate the API version for SDIO ERR hypervisor services. 205 */ 206 if ((px_sdio_err_users == 0) && 207 ((ret = hsvc_register(&px_hsvc_sdio_err, 208 &px_sdio_err_min_ver)) != 0)) { 209 DBG(DBG_ATTACH, dip, "%s: cannot negotiate SDIO ERR hypervisor " 210 "services group: 0x%lx major: 0x%lx minor: 0x%lx " 211 "errno: %d\n", px_hsvc_sdio_err.hsvc_modname, 212 px_hsvc_sdio_err.hsvc_group, px_hsvc_sdio_err.hsvc_major, 213 px_hsvc_sdio_err.hsvc_minor, ret); 214 } else { 215 px_sdio_err_users++; 216 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO ERR API " 217 "version, major 0x%lx minor 0x%lx\n", 218 px_hsvc_sdio_err.hsvc_major, px_sdio_err_min_ver); 219 } 220 221 /* 222 * Find out the number of dev we need to wait under this RC 223 * before we issue fabric sync hypercall 224 */ 225 px_p->px_plat_p = (void *)(uintptr_t)px_lib_count_waiting_dev(dip); 226 DBG(DBG_ATTACH, dip, "Found %d bridges need waiting under RC %p", 227 (int)(uintptr_t)px_p->px_plat_p, dip); 228 return (DDI_SUCCESS); 229 } 230 231 /*ARGSUSED*/ 232 int 233 px_lib_dev_fini(dev_info_t *dip) 234 { 235 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 236 237 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 238 PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR)), dip, 239 PCI_BUS_CONF_MAP_PROP); 240 241 if (--px_vpci_users == 0) 242 (void) hsvc_unregister(&px_hsvc_vpci); 243 244 if (--px_sdio_users == 0) 245 (void) hsvc_unregister(&px_hsvc_sdio); 246 247 if (--px_sdio_err_users == 0) 248 (void) hsvc_unregister(&px_hsvc_sdio_err); 249 250 return (DDI_SUCCESS); 251 } 252 253 /*ARGSUSED*/ 254 int 255 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 256 sysino_t *sysino) 257 { 258 uint64_t ret; 259 260 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 261 "devino 0x%x\n", dip, devino); 262 263 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 264 devino, sysino)) != H_EOK) { 265 DBG(DBG_LIB_INT, dip, 266 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 267 return (DDI_FAILURE); 268 } 269 270 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 271 *sysino); 272 273 return (DDI_SUCCESS); 274 } 275 276 /*ARGSUSED*/ 277 int 278 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 279 intr_valid_state_t *intr_valid_state) 280 { 281 uint64_t ret; 282 283 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 284 dip, sysino); 285 286 if ((ret = hvio_intr_getvalid(sysino, 287 (int *)intr_valid_state)) != H_EOK) { 288 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 289 ret); 290 return (DDI_FAILURE); 291 } 292 293 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 294 *intr_valid_state); 295 296 return (DDI_SUCCESS); 297 } 298 299 /*ARGSUSED*/ 300 int 301 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 302 intr_valid_state_t intr_valid_state) 303 { 304 uint64_t ret; 305 306 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 307 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 308 309 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 310 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 311 ret); 312 return (DDI_FAILURE); 313 } 314 315 return (DDI_SUCCESS); 316 } 317 318 /*ARGSUSED*/ 319 int 320 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 321 intr_state_t *intr_state) 322 { 323 uint64_t ret; 324 325 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 326 dip, sysino); 327 328 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 329 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 330 ret); 331 return (DDI_FAILURE); 332 } 333 334 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 335 *intr_state); 336 337 return (DDI_SUCCESS); 338 } 339 340 /*ARGSUSED*/ 341 int 342 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 343 intr_state_t intr_state) 344 { 345 uint64_t ret; 346 347 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 348 "intr_state 0x%x\n", dip, sysino, intr_state); 349 350 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 351 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 352 ret); 353 return (DDI_FAILURE); 354 } 355 356 return (DDI_SUCCESS); 357 } 358 359 /*ARGSUSED*/ 360 int 361 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 362 { 363 uint64_t ret; 364 365 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 366 dip, sysino); 367 368 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 369 DBG(DBG_LIB_INT, dip, 370 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 371 return (DDI_FAILURE); 372 } 373 374 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", *cpuid); 375 376 return (DDI_SUCCESS); 377 } 378 379 /*ARGSUSED*/ 380 int 381 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 382 { 383 uint64_t ret; 384 385 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 386 "cpuid 0x%x\n", dip, sysino, cpuid); 387 388 ret = hvio_intr_settarget(sysino, cpuid); 389 if (ret == H_ECPUERROR) { 390 cmn_err(CE_PANIC, 391 "px_lib_intr_settarget: hvio_intr_settarget failed, " 392 "ret = 0x%lx, cpuid = 0x%x, sysino = 0x%lx\n", ret, 393 cpuid, sysino); 394 } else if (ret != H_EOK) { 395 DBG(DBG_LIB_INT, dip, 396 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 397 return (DDI_FAILURE); 398 } 399 400 return (DDI_SUCCESS); 401 } 402 403 /*ARGSUSED*/ 404 int 405 px_lib_intr_reset(dev_info_t *dip) 406 { 407 px_t *px_p = DIP_TO_STATE(dip); 408 px_ib_t *ib_p = px_p->px_ib_p; 409 px_ino_t *ino_p; 410 411 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 412 413 mutex_enter(&ib_p->ib_ino_lst_mutex); 414 415 /* Reset all Interrupts */ 416 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 417 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 418 INTR_IDLE_STATE) != DDI_SUCCESS) 419 return (BF_FATAL); 420 } 421 422 mutex_exit(&ib_p->ib_ino_lst_mutex); 423 424 return (BF_NONE); 425 } 426 427 /*ARGSUSED*/ 428 int 429 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 430 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 431 { 432 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 433 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 434 io_page_list_t *pfns, *pfn_p; 435 pages_t ttes_mapped = 0; 436 int i, err = DDI_SUCCESS; 437 438 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 439 "pages 0x%x attr 0x%llx addr 0x%p pfn_index 0x%llx flags 0x%x\n", 440 dip, tsbid, pages, attr, addr, pfn_index, flags); 441 442 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 443 KM_NOSLEEP)) == NULL) { 444 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 445 return (DDI_FAILURE); 446 } 447 448 for (i = 0; i < pages; i++) 449 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 450 451 /* 452 * If HV VPCI version is 2.0 and higher, pass BDF, phantom function, 453 * and relaxed ordering attributes. Otherwise, pass only read or write 454 * attribute. 455 */ 456 if ((px_vpci_maj_ver == PX_HSVC_MAJOR_VER_1) && 457 (px_vpci_min_ver == PX_HSVC_MINOR_VER_0)) 458 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 459 460 while ((ttes_mapped = pfn_p - pfns) < pages) { 461 uintptr_t ra = va_to_pa(pfn_p); 462 pages_t ttes2map; 463 uint64_t ret; 464 465 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 466 ra = MMU_PTOB(MMU_BTOP(ra)); 467 468 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 469 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 470 471 ttes_mapped = 0; 472 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 473 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 474 ttes2map, attr, (io_page_list_t *)(ra | 475 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 476 &ttes_mapped)) != H_EOK) { 477 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 478 "ret 0x%lx\n", ret); 479 480 ttes_mapped = pfn_p - pfns; 481 err = DDI_FAILURE; 482 goto cleanup; 483 } 484 485 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 486 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%llx " 487 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 488 tsb_index + (pfn_p - pfns), ttes2map, attr, 489 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 490 ttes_mapped); 491 } 492 } 493 494 cleanup: 495 if ((err == DDI_FAILURE) && ttes_mapped) 496 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 497 498 kmem_free(pfns, pages * sizeof (io_page_list_t)); 499 return (err); 500 } 501 502 /*ARGSUSED*/ 503 int 504 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 505 { 506 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 507 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 508 pages_t ttes2demap, ttes_demapped = 0; 509 uint64_t ret; 510 511 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 512 "pages 0x%x\n", dip, tsbid, pages); 513 514 for (ttes2demap = pages; ttes2demap; 515 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 516 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 517 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 518 &ttes_demapped)) != H_EOK) { 519 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 520 "ret 0x%lx\n", ret); 521 522 return (DDI_FAILURE); 523 } 524 525 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 526 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 527 tsb_num, tsb_index, ttes2demap, ttes_demapped); 528 } 529 530 return (DDI_SUCCESS); 531 } 532 533 /*ARGSUSED*/ 534 int 535 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 536 r_addr_t *r_addr_p) 537 { 538 uint64_t ret; 539 540 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 541 dip, tsbid); 542 543 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 544 attr_p, r_addr_p)) != H_EOK) { 545 DBG(DBG_LIB_DMA, dip, 546 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 547 548 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 549 } 550 551 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%llx " 552 "r_addr 0x%llx\n", *attr_p, *r_addr_p); 553 554 return (DDI_SUCCESS); 555 } 556 557 /*ARGSUSED*/ 558 uint64_t 559 px_get_rng_parent_hi_mask(px_t *px_p) 560 { 561 return (PX_RANGE_PROP_MASK); 562 } 563 564 /* 565 * Checks dma attributes against system bypass ranges 566 * A sun4v device must be capable of generating the entire 64-bit 567 * address in order to perform bypass DMA. 568 */ 569 /*ARGSUSED*/ 570 int 571 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 572 uint64_t *lo_p, uint64_t *hi_p) 573 { 574 if ((attr_p->dma_attr_addr_lo != 0ull) || 575 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 576 577 return (DDI_DMA_BADATTR); 578 } 579 580 *lo_p = 0ull; 581 *hi_p = UINT64_MAX; 582 583 return (DDI_SUCCESS); 584 } 585 586 587 /*ARGSUSED*/ 588 int 589 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 590 io_addr_t *io_addr_p) 591 { 592 uint64_t ret; 593 594 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 595 "attr 0x%llx\n", dip, ra, attr); 596 /* 597 * If HV VPCI version is 2.0 and higher, pass BDF, phantom function, 598 * and relaxed ordering attributes. Otherwise, pass only read or write 599 * attribute. 600 */ 601 if ((px_vpci_maj_ver == PX_HSVC_MAJOR_VER_1) && 602 (px_vpci_min_ver == PX_HSVC_MINOR_VER_0)) 603 attr &= PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE; 604 605 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 606 attr, io_addr_p)) != H_EOK) { 607 DBG(DBG_LIB_DMA, dip, 608 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 609 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 610 } 611 612 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 613 *io_addr_p); 614 615 return (DDI_SUCCESS); 616 } 617 618 /* 619 * Returns any needed IO address bit(s) for relaxed ordering in IOMMU 620 * bypass mode. 621 */ 622 /* ARGSUSED */ 623 uint64_t 624 px_lib_ro_bypass(dev_info_t *dip, io_attributes_t attr, uint64_t ioaddr) 625 { 626 return (ioaddr); 627 } 628 629 /*ARGSUSED*/ 630 int 631 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 632 off_t off, size_t len, uint_t cache_flags) 633 { 634 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 635 uint64_t sync_dir; 636 size_t bytes_synced; 637 int end, idx; 638 off_t pg_off; 639 devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */ 640 641 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 642 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 643 dip, rdip, handle, off, len, cache_flags); 644 645 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 646 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 647 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 648 return (DDI_FAILURE); 649 } 650 651 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 652 return (DDI_SUCCESS); 653 654 if (!len) 655 len = mp->dmai_size; 656 657 if (mp->dmai_rflags & DDI_DMA_READ) 658 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 659 else 660 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 661 662 off += mp->dmai_offset; 663 pg_off = off & MMU_PAGEOFFSET; 664 665 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: page offset %x size %x\n", 666 pg_off, len); 667 668 /* sync on page basis */ 669 end = MMU_BTOPR(off + len - 1); 670 for (idx = MMU_BTOP(off); idx < end; idx++, 671 len -= bytes_synced, pg_off = 0) { 672 size_t bytes_to_sync = bytes_to_sync = 673 MIN(len, MMU_PAGESIZE - pg_off); 674 675 if (hvio_dma_sync(hdl, MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + 676 pg_off, bytes_to_sync, sync_dir, &bytes_synced) != H_EOK) 677 break; 678 679 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: Called hvio_dma_sync " 680 "ra = %p bytes to sync = %x bytes synced %x\n", 681 MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, bytes_to_sync, 682 bytes_synced); 683 684 if (bytes_to_sync != bytes_synced) 685 break; 686 } 687 688 return (len ? DDI_FAILURE : DDI_SUCCESS); 689 } 690 691 692 /* 693 * MSIQ Functions: 694 */ 695 696 /*ARGSUSED*/ 697 int 698 px_lib_msiq_init(dev_info_t *dip) 699 { 700 px_t *px_p = DIP_TO_STATE(dip); 701 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 702 r_addr_t ra; 703 size_t msiq_size; 704 uint_t rec_cnt; 705 int i, err = DDI_SUCCESS; 706 uint64_t ret; 707 708 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 709 710 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 711 712 /* sun4v requires all EQ allocation to be on q size boundary */ 713 if ((msiq_state_p->msiq_buf_p = contig_mem_alloc_align( 714 msiq_state_p->msiq_cnt * msiq_size, msiq_size)) == NULL) { 715 DBG(DBG_LIB_MSIQ, dip, 716 "px_lib_msiq_init: Contig alloc failed\n"); 717 718 return (DDI_FAILURE); 719 } 720 721 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 722 msiq_state_p->msiq_p[i].msiq_base_p = (msiqhead_t *) 723 ((caddr_t)msiq_state_p->msiq_buf_p + (i * msiq_size)); 724 725 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 726 (i * msiq_size)); 727 728 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 729 (i + msiq_state_p->msiq_1st_msiq_id), 730 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 731 DBG(DBG_LIB_MSIQ, dip, 732 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 733 err = DDI_FAILURE; 734 break; 735 } 736 737 if ((err = px_lib_msiq_info(dip, 738 (i + msiq_state_p->msiq_1st_msiq_id), 739 &ra, &rec_cnt)) != DDI_SUCCESS) { 740 DBG(DBG_LIB_MSIQ, dip, 741 "px_lib_msiq_info failed, ret 0x%x\n", err); 742 err = DDI_FAILURE; 743 break; 744 } 745 746 DBG(DBG_LIB_MSIQ, dip, 747 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 748 } 749 750 return (err); 751 } 752 753 /*ARGSUSED*/ 754 int 755 px_lib_msiq_fini(dev_info_t *dip) 756 { 757 px_t *px_p = DIP_TO_STATE(dip); 758 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 759 size_t msiq_size; 760 761 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 762 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 763 764 if (msiq_state_p->msiq_buf_p != NULL) 765 contig_mem_free(msiq_state_p->msiq_buf_p, 766 msiq_state_p->msiq_cnt * msiq_size); 767 768 return (DDI_SUCCESS); 769 } 770 771 /*ARGSUSED*/ 772 int 773 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 774 uint_t *msiq_rec_cnt_p) 775 { 776 uint64_t ret; 777 778 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 779 dip, msiq_id); 780 781 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 782 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 783 DBG(DBG_LIB_MSIQ, dip, 784 "hvio_msiq_info failed, ret 0x%lx\n", ret); 785 return (DDI_FAILURE); 786 } 787 788 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 789 ra_p, *msiq_rec_cnt_p); 790 791 return (DDI_SUCCESS); 792 } 793 794 /*ARGSUSED*/ 795 int 796 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 797 pci_msiq_valid_state_t *msiq_valid_state) 798 { 799 uint64_t ret; 800 801 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 802 dip, msiq_id); 803 804 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 805 msiq_id, msiq_valid_state)) != H_EOK) { 806 DBG(DBG_LIB_MSIQ, dip, 807 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 808 return (DDI_FAILURE); 809 } 810 811 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 812 *msiq_valid_state); 813 814 return (DDI_SUCCESS); 815 } 816 817 /*ARGSUSED*/ 818 int 819 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 820 pci_msiq_valid_state_t msiq_valid_state) 821 { 822 uint64_t ret; 823 824 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 825 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 826 827 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 828 msiq_id, msiq_valid_state)) != H_EOK) { 829 DBG(DBG_LIB_MSIQ, dip, 830 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 831 return (DDI_FAILURE); 832 } 833 834 return (DDI_SUCCESS); 835 } 836 837 /*ARGSUSED*/ 838 int 839 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 840 pci_msiq_state_t *msiq_state) 841 { 842 uint64_t ret; 843 844 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 845 dip, msiq_id); 846 847 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 848 msiq_id, msiq_state)) != H_EOK) { 849 DBG(DBG_LIB_MSIQ, dip, 850 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 851 return (DDI_FAILURE); 852 } 853 854 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 855 *msiq_state); 856 857 return (DDI_SUCCESS); 858 } 859 860 /*ARGSUSED*/ 861 int 862 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 863 pci_msiq_state_t msiq_state) 864 { 865 uint64_t ret; 866 867 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 868 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 869 870 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 871 msiq_id, msiq_state)) != H_EOK) { 872 DBG(DBG_LIB_MSIQ, dip, 873 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 874 return (DDI_FAILURE); 875 } 876 877 return (DDI_SUCCESS); 878 } 879 880 /*ARGSUSED*/ 881 int 882 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 883 msiqhead_t *msiq_head_p) 884 { 885 uint64_t ret; 886 887 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 888 dip, msiq_id); 889 890 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 891 msiq_id, msiq_head_p)) != H_EOK) { 892 DBG(DBG_LIB_MSIQ, dip, 893 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 894 return (DDI_FAILURE); 895 } 896 897 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 898 899 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 900 *msiq_head_p); 901 902 return (DDI_SUCCESS); 903 } 904 905 /*ARGSUSED*/ 906 int 907 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 908 msiqhead_t msiq_head) 909 { 910 uint64_t ret; 911 912 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 913 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 914 915 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 916 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 917 DBG(DBG_LIB_MSIQ, dip, 918 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 919 return (DDI_FAILURE); 920 } 921 922 return (DDI_SUCCESS); 923 } 924 925 /*ARGSUSED*/ 926 int 927 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 928 msiqtail_t *msiq_tail_p) 929 { 930 uint64_t ret; 931 932 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 933 dip, msiq_id); 934 935 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 936 msiq_id, msiq_tail_p)) != H_EOK) { 937 DBG(DBG_LIB_MSIQ, dip, 938 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 939 return (DDI_FAILURE); 940 } 941 942 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 943 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 944 *msiq_tail_p); 945 946 return (DDI_SUCCESS); 947 } 948 949 /*ARGSUSED*/ 950 void 951 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 952 msiq_rec_t *msiq_rec_p) 953 { 954 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 955 956 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 957 958 if (!curr_msiq_rec_p->msiq_rec_type) { 959 /* Set msiq_rec_type to zero */ 960 msiq_rec_p->msiq_rec_type = 0; 961 962 return; 963 } 964 965 *msiq_rec_p = *curr_msiq_rec_p; 966 } 967 968 /*ARGSUSED*/ 969 void 970 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 971 { 972 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 973 974 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip); 975 976 /* Zero out msiq_rec_type field */ 977 curr_msiq_rec_p->msiq_rec_type = 0; 978 } 979 980 /* 981 * MSI Functions: 982 */ 983 984 /*ARGSUSED*/ 985 int 986 px_lib_msi_init(dev_info_t *dip) 987 { 988 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 989 990 /* Noop */ 991 return (DDI_SUCCESS); 992 } 993 994 /*ARGSUSED*/ 995 int 996 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 997 msiqid_t *msiq_id) 998 { 999 uint64_t ret; 1000 1001 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 1002 dip, msi_num); 1003 1004 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 1005 msi_num, msiq_id)) != H_EOK) { 1006 DBG(DBG_LIB_MSI, dip, 1007 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 1008 return (DDI_FAILURE); 1009 } 1010 1011 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 1012 *msiq_id); 1013 1014 return (DDI_SUCCESS); 1015 } 1016 1017 /*ARGSUSED*/ 1018 int 1019 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 1020 msiqid_t msiq_id, msi_type_t msitype) 1021 { 1022 uint64_t ret; 1023 1024 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 1025 "msq_id 0x%x\n", dip, msi_num, msiq_id); 1026 1027 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 1028 msi_num, msiq_id, msitype)) != H_EOK) { 1029 DBG(DBG_LIB_MSI, dip, 1030 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 1031 return (DDI_FAILURE); 1032 } 1033 1034 return (DDI_SUCCESS); 1035 } 1036 1037 /*ARGSUSED*/ 1038 int 1039 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 1040 pci_msi_valid_state_t *msi_valid_state) 1041 { 1042 uint64_t ret; 1043 1044 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 1045 dip, msi_num); 1046 1047 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 1048 msi_num, msi_valid_state)) != H_EOK) { 1049 DBG(DBG_LIB_MSI, dip, 1050 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 1051 return (DDI_FAILURE); 1052 } 1053 1054 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 1055 *msi_valid_state); 1056 1057 return (DDI_SUCCESS); 1058 } 1059 1060 /*ARGSUSED*/ 1061 int 1062 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 1063 pci_msi_valid_state_t msi_valid_state) 1064 { 1065 uint64_t ret; 1066 1067 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 1068 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 1069 1070 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 1071 msi_num, msi_valid_state)) != H_EOK) { 1072 DBG(DBG_LIB_MSI, dip, 1073 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 1074 return (DDI_FAILURE); 1075 } 1076 1077 return (DDI_SUCCESS); 1078 } 1079 1080 /*ARGSUSED*/ 1081 int 1082 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 1083 pci_msi_state_t *msi_state) 1084 { 1085 uint64_t ret; 1086 1087 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 1088 dip, msi_num); 1089 1090 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 1091 msi_num, msi_state)) != H_EOK) { 1092 DBG(DBG_LIB_MSI, dip, 1093 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 1094 return (DDI_FAILURE); 1095 } 1096 1097 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 1098 *msi_state); 1099 1100 return (DDI_SUCCESS); 1101 } 1102 1103 /*ARGSUSED*/ 1104 int 1105 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 1106 pci_msi_state_t msi_state) 1107 { 1108 uint64_t ret; 1109 1110 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 1111 "msi_state 0x%x\n", dip, msi_num, msi_state); 1112 1113 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 1114 msi_num, msi_state)) != H_EOK) { 1115 DBG(DBG_LIB_MSI, dip, 1116 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 1117 return (DDI_FAILURE); 1118 } 1119 1120 return (DDI_SUCCESS); 1121 } 1122 1123 /* 1124 * MSG Functions: 1125 */ 1126 1127 /*ARGSUSED*/ 1128 int 1129 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1130 msiqid_t *msiq_id) 1131 { 1132 uint64_t ret; 1133 1134 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1135 dip, msg_type); 1136 1137 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1138 msg_type, msiq_id)) != H_EOK) { 1139 DBG(DBG_LIB_MSG, dip, 1140 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1141 return (DDI_FAILURE); 1142 } 1143 1144 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1145 *msiq_id); 1146 1147 return (DDI_SUCCESS); 1148 } 1149 1150 /*ARGSUSED*/ 1151 int 1152 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1153 msiqid_t msiq_id) 1154 { 1155 uint64_t ret; 1156 1157 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 1158 "msq_id 0x%x\n", dip, msg_type, msiq_id); 1159 1160 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1161 msg_type, msiq_id)) != H_EOK) { 1162 DBG(DBG_LIB_MSG, dip, 1163 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1164 return (DDI_FAILURE); 1165 } 1166 1167 return (DDI_SUCCESS); 1168 } 1169 1170 /*ARGSUSED*/ 1171 int 1172 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1173 pcie_msg_valid_state_t *msg_valid_state) 1174 { 1175 uint64_t ret; 1176 1177 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1178 dip, msg_type); 1179 1180 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1181 msg_valid_state)) != H_EOK) { 1182 DBG(DBG_LIB_MSG, dip, 1183 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1184 return (DDI_FAILURE); 1185 } 1186 1187 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1188 *msg_valid_state); 1189 1190 return (DDI_SUCCESS); 1191 } 1192 1193 /*ARGSUSED*/ 1194 int 1195 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1196 pcie_msg_valid_state_t msg_valid_state) 1197 { 1198 uint64_t ret; 1199 1200 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1201 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1202 1203 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1204 msg_valid_state)) != H_EOK) { 1205 DBG(DBG_LIB_MSG, dip, 1206 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1207 return (DDI_FAILURE); 1208 } 1209 1210 return (DDI_SUCCESS); 1211 } 1212 1213 /* 1214 * Suspend/Resume Functions: 1215 * Currently unsupported by hypervisor and all functions are noops. 1216 */ 1217 /*ARGSUSED*/ 1218 int 1219 px_lib_suspend(dev_info_t *dip) 1220 { 1221 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1222 1223 /* Not supported */ 1224 return (DDI_FAILURE); 1225 } 1226 1227 /*ARGSUSED*/ 1228 void 1229 px_lib_resume(dev_info_t *dip) 1230 { 1231 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1232 1233 /* Noop */ 1234 } 1235 1236 /* 1237 * Misc Functions: 1238 * Currently unsupported by hypervisor and all functions are noops. 1239 */ 1240 /*ARGSUSED*/ 1241 static int 1242 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1243 uint8_t size, pci_cfg_data_t *data_p) 1244 { 1245 uint64_t ret; 1246 1247 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1248 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1249 1250 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1251 size, data_p)) != H_EOK) { 1252 DBG(DBG_LIB_CFG, dip, 1253 "hvio_config_get failed, ret 0x%lx\n", ret); 1254 return (DDI_FAILURE); 1255 } 1256 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1257 1258 return (DDI_SUCCESS); 1259 } 1260 1261 /*ARGSUSED*/ 1262 static int 1263 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1264 uint8_t size, pci_cfg_data_t data) 1265 { 1266 uint64_t ret; 1267 1268 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1269 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1270 1271 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1272 size, data)) != H_EOK) { 1273 DBG(DBG_LIB_CFG, dip, 1274 "hvio_config_put failed, ret 0x%lx\n", ret); 1275 return (DDI_FAILURE); 1276 } 1277 1278 return (DDI_SUCCESS); 1279 } 1280 1281 static uint32_t 1282 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1283 { 1284 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1285 handle->ahi_common.ah_bus_private; 1286 pcie_bus_t *busp = NULL; 1287 dev_info_t *cdip = NULL; 1288 uint32_t pci_dev_addr = px_pvt->raddr; 1289 uint32_t vaddr = px_pvt->vaddr; 1290 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1291 uint64_t rdata = 0; 1292 1293 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1294 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1295 /* XXX update error kstats */ 1296 return (0xffffffff); 1297 1298 if (cdip = pcie_find_dip_by_bdf(px_pvt->dip, pci_dev_addr >> 8)) 1299 busp = PCIE_DIP2BUS(cdip); 1300 /* 1301 * This can be called early, before busp or busp->bus_dom has 1302 * been initialized, so check both before invoking 1303 * PCIE_IS_ASSIGNED. 1304 */ 1305 if (busp && PCIE_BUS2DOM(busp) && PCIE_IS_ASSIGNED(busp)) { 1306 if (off == PCI_CONF_VENID && size == 2) 1307 rdata = busp->bus_dev_ven_id & 0xffff; 1308 else if (off == PCI_CONF_DEVID && size == 2) 1309 rdata = busp->bus_dev_ven_id >> 16; 1310 else if (off == PCI_CONF_VENID && size == 4) 1311 rdata = busp->bus_dev_ven_id; 1312 } 1313 return ((uint32_t)rdata); 1314 } 1315 1316 static void 1317 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1318 int size, pci_cfg_data_t wdata) 1319 { 1320 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1321 handle->ahi_common.ah_bus_private; 1322 uint32_t pci_dev_addr = px_pvt->raddr; 1323 uint32_t vaddr = px_pvt->vaddr; 1324 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1325 1326 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1327 size, wdata) != DDI_SUCCESS) { 1328 /*EMPTY*/ 1329 /* XXX update error kstats */ 1330 } 1331 } 1332 1333 static uint8_t 1334 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1335 { 1336 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1337 } 1338 1339 static uint16_t 1340 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1341 { 1342 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1343 } 1344 1345 static uint32_t 1346 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1347 { 1348 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1349 } 1350 1351 static uint64_t 1352 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1353 { 1354 uint32_t rdatah, rdatal; 1355 1356 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1357 rdatah = (uint32_t)px_pci_config_get(handle, 1358 (uint32_t *)((char *)addr+4), 4); 1359 return (((uint64_t)rdatah << 32) | rdatal); 1360 } 1361 1362 static void 1363 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1364 { 1365 pci_cfg_data_t wdata = { 0 }; 1366 1367 wdata.qw = (uint8_t)data; 1368 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1369 } 1370 1371 static void 1372 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1373 { 1374 pci_cfg_data_t wdata = { 0 }; 1375 1376 wdata.qw = (uint16_t)data; 1377 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1378 } 1379 1380 static void 1381 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1382 { 1383 pci_cfg_data_t wdata = { 0 }; 1384 1385 wdata.qw = (uint32_t)data; 1386 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1387 } 1388 1389 static void 1390 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1391 { 1392 pci_cfg_data_t wdata = { 0 }; 1393 1394 wdata.qw = (uint32_t)(data & 0xffffffff); 1395 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1396 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1397 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1398 } 1399 1400 static void 1401 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1402 uint8_t *dev_addr, size_t repcount, uint_t flags) 1403 { 1404 if (flags == DDI_DEV_AUTOINCR) 1405 for (; repcount; repcount--) 1406 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1407 else 1408 for (; repcount; repcount--) 1409 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1410 } 1411 1412 /* 1413 * Function to rep read 16 bit data off the PCI configuration space behind 1414 * the 21554's host interface. 1415 */ 1416 static void 1417 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1418 uint16_t *dev_addr, size_t repcount, uint_t flags) 1419 { 1420 if (flags == DDI_DEV_AUTOINCR) 1421 for (; repcount; repcount--) 1422 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1423 else 1424 for (; repcount; repcount--) 1425 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1426 } 1427 1428 /* 1429 * Function to rep read 32 bit data off the PCI configuration space behind 1430 * the 21554's host interface. 1431 */ 1432 static void 1433 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1434 uint32_t *dev_addr, size_t repcount, uint_t flags) 1435 { 1436 if (flags == DDI_DEV_AUTOINCR) 1437 for (; repcount; repcount--) 1438 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1439 else 1440 for (; repcount; repcount--) 1441 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1442 } 1443 1444 /* 1445 * Function to rep read 64 bit data off the PCI configuration space behind 1446 * the 21554's host interface. 1447 */ 1448 static void 1449 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1450 uint64_t *dev_addr, size_t repcount, uint_t flags) 1451 { 1452 if (flags == DDI_DEV_AUTOINCR) 1453 for (; repcount; repcount--) 1454 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1455 else 1456 for (; repcount; repcount--) 1457 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1458 } 1459 1460 /* 1461 * Function to rep write 8 bit data into the PCI configuration space behind 1462 * the 21554's host interface. 1463 */ 1464 static void 1465 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1466 uint8_t *dev_addr, size_t repcount, uint_t flags) 1467 { 1468 if (flags == DDI_DEV_AUTOINCR) 1469 for (; repcount; repcount--) 1470 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1471 else 1472 for (; repcount; repcount--) 1473 px_pci_config_put8(handle, dev_addr, *host_addr++); 1474 } 1475 1476 /* 1477 * Function to rep write 16 bit data into the PCI configuration space behind 1478 * the 21554's host interface. 1479 */ 1480 static void 1481 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1482 uint16_t *dev_addr, size_t repcount, uint_t flags) 1483 { 1484 if (flags == DDI_DEV_AUTOINCR) 1485 for (; repcount; repcount--) 1486 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1487 else 1488 for (; repcount; repcount--) 1489 px_pci_config_put16(handle, dev_addr, *host_addr++); 1490 } 1491 1492 /* 1493 * Function to rep write 32 bit data into the PCI configuration space behind 1494 * the 21554's host interface. 1495 */ 1496 static void 1497 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1498 uint32_t *dev_addr, size_t repcount, uint_t flags) 1499 { 1500 if (flags == DDI_DEV_AUTOINCR) 1501 for (; repcount; repcount--) 1502 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1503 else 1504 for (; repcount; repcount--) 1505 px_pci_config_put32(handle, dev_addr, *host_addr++); 1506 } 1507 1508 /* 1509 * Function to rep write 64 bit data into the PCI configuration space behind 1510 * the 21554's host interface. 1511 */ 1512 static void 1513 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1514 uint64_t *dev_addr, size_t repcount, uint_t flags) 1515 { 1516 if (flags == DDI_DEV_AUTOINCR) 1517 for (; repcount; repcount--) 1518 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1519 else 1520 for (; repcount; repcount--) 1521 px_pci_config_put64(handle, dev_addr, *host_addr++); 1522 } 1523 1524 /* 1525 * Provide a private access handle to route config access calls to Hypervisor. 1526 * Beware: Do all error checking for config space accesses before calling 1527 * this function. ie. do error checking from the calling function. 1528 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1529 * DDI_SUCCESS from here makes the code organization readable/easier from 1530 * the generic code. 1531 */ 1532 /*ARGSUSED*/ 1533 int 1534 px_lib_map_vconfig(dev_info_t *dip, 1535 ddi_map_req_t *mp, pci_config_offset_t off, 1536 pci_regspec_t *rp, caddr_t *addrp) 1537 { 1538 int fmcap; 1539 ndi_err_t *errp; 1540 on_trap_data_t *otp; 1541 ddi_acc_hdl_t *hp; 1542 ddi_acc_impl_t *ap; 1543 uchar_t busnum; /* bus number */ 1544 uchar_t devnum; /* device number */ 1545 uchar_t funcnum; /* function number */ 1546 px_config_acc_pvt_t *px_pvt; 1547 1548 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1549 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1550 1551 /* Check for mapping teardown operation */ 1552 if ((mp->map_op == DDI_MO_UNMAP) || 1553 (mp->map_op == DDI_MO_UNLOCK)) { 1554 /* free up memory allocated for the private access handle. */ 1555 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1556 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1557 1558 /* unmap operation of PCI IO/config space. */ 1559 return (DDI_SUCCESS); 1560 } 1561 1562 fmcap = ddi_fm_capable(dip); 1563 if (DDI_FM_ACC_ERR_CAP(fmcap)) { 1564 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 1565 otp = (on_trap_data_t *)errp->err_ontrap; 1566 otp->ot_handle = (void *)(hp); 1567 otp->ot_prot = OT_DATA_ACCESS; 1568 errp->err_status = DDI_FM_OK; 1569 errp->err_expected = DDI_FM_ERR_UNEXPECTED; 1570 errp->err_cf = px_err_cfg_hdl_check; 1571 } 1572 1573 ap->ahi_get8 = px_pci_config_get8; 1574 ap->ahi_get16 = px_pci_config_get16; 1575 ap->ahi_get32 = px_pci_config_get32; 1576 ap->ahi_get64 = px_pci_config_get64; 1577 ap->ahi_put8 = px_pci_config_put8; 1578 ap->ahi_put16 = px_pci_config_put16; 1579 ap->ahi_put32 = px_pci_config_put32; 1580 ap->ahi_put64 = px_pci_config_put64; 1581 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1582 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1583 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1584 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1585 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1586 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1587 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1588 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1589 1590 /* Initialize to default check/notify functions */ 1591 ap->ahi_fault = 0; 1592 ap->ahi_fault_check = i_ddi_acc_fault_check; 1593 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1594 1595 /* allocate memory for our private handle */ 1596 px_pvt = (px_config_acc_pvt_t *) 1597 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1598 hp->ah_bus_private = (void *)px_pvt; 1599 1600 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1601 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1602 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1603 1604 /* set up private data for use during IO routines */ 1605 1606 /* addr needed by the HV APIs */ 1607 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1608 /* 1609 * Address that specifies the actual offset into the 256MB 1610 * memory mapped configuration space, 4K per device. 1611 * First 12bits form the offset into 4K config space. 1612 * This address is only used during the IO routines to calculate 1613 * the offset at which the transaction must be performed. 1614 * Drivers bypassing DDI functions to access PCI config space will 1615 * panic the system since the following is a bogus virtual address. 1616 */ 1617 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1618 px_pvt->dip = dip; 1619 1620 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1621 px_pvt->raddr, px_pvt->vaddr); 1622 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1623 return (DDI_SUCCESS); 1624 } 1625 1626 /*ARGSUSED*/ 1627 void 1628 px_lib_map_attr_check(ddi_map_req_t *mp) 1629 { 1630 } 1631 1632 /* 1633 * px_lib_log_safeacc_err: 1634 * Imitate a cpu/mem trap call when a peek/poke fails. 1635 * This will initiate something similar to px_fm_callback. 1636 */ 1637 static void 1638 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag, 1639 r_addr_t addr) 1640 { 1641 uint32_t addr_high, addr_low; 1642 pcie_req_id_t bdf = PCIE_INVALID_BDF; 1643 pci_ranges_t *ranges_p; 1644 int range_len, i; 1645 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1646 ddi_fm_error_t derr; 1647 1648 if (px_fm_enter(px_p) != DDI_SUCCESS) 1649 return; 1650 1651 derr.fme_status = DDI_FM_NONFATAL; 1652 derr.fme_version = DDI_FME_VERSION; 1653 derr.fme_flag = fme_flag; 1654 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1655 derr.fme_acc_handle = handle; 1656 if (hp) 1657 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1658 1659 addr_high = (uint32_t)(addr >> 32); 1660 addr_low = (uint32_t)addr; 1661 1662 /* 1663 * Make sure this failed load came from this PCIe port. Check by 1664 * matching the upper 32 bits of the address with the ranges property. 1665 */ 1666 range_len = px_p->px_ranges_length / sizeof (pci_ranges_t); 1667 i = 0; 1668 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1669 if (ranges_p->parent_high == addr_high) { 1670 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1671 case PCI_ADDR_CONFIG: 1672 bdf = (pcie_req_id_t)(addr_low >> 12); 1673 break; 1674 default: 1675 bdf = PCIE_INVALID_BDF; 1676 break; 1677 } 1678 break; 1679 } 1680 } 1681 1682 (void) px_rp_en_q(px_p, bdf, addr, NULL); 1683 (void) px_scan_fabric(px_p, px_p->px_dip, &derr); 1684 px_fm_exit(px_p); 1685 } 1686 1687 1688 #ifdef DEBUG 1689 int px_peekfault_cnt = 0; 1690 int px_pokefault_cnt = 0; 1691 #endif /* DEBUG */ 1692 1693 /* 1694 * Do a safe write to a device. 1695 * 1696 * When this function is given a handle (cautious access), all errors are 1697 * suppressed. 1698 * 1699 * When this function is not given a handle (poke), only Unsupported Request 1700 * and Completer Abort errors are suppressed. 1701 * 1702 * In all cases, all errors are returned in the function return status. 1703 */ 1704 1705 int 1706 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1707 peekpoke_ctlops_t *in_args) 1708 { 1709 px_t *px_p = DIP_TO_STATE(dip); 1710 px_pec_t *pec_p = px_p->px_pec_p; 1711 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1712 1713 size_t repcount = in_args->repcount; 1714 size_t size = in_args->size; 1715 uintptr_t dev_addr = in_args->dev_addr; 1716 uintptr_t host_addr = in_args->host_addr; 1717 1718 int err = DDI_SUCCESS; 1719 uint64_t hvio_poke_status; 1720 uint32_t wrt_stat; 1721 1722 r_addr_t ra; 1723 uint64_t pokeval; 1724 pcie_req_id_t bdf; 1725 1726 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1727 for (; repcount; repcount--) { 1728 1729 switch (size) { 1730 case sizeof (uint8_t): 1731 pokeval = *(uint8_t *)host_addr; 1732 break; 1733 case sizeof (uint16_t): 1734 pokeval = *(uint16_t *)host_addr; 1735 break; 1736 case sizeof (uint32_t): 1737 pokeval = *(uint32_t *)host_addr; 1738 break; 1739 case sizeof (uint64_t): 1740 pokeval = *(uint64_t *)host_addr; 1741 break; 1742 default: 1743 DBG(DBG_MAP, px_p->px_dip, 1744 "poke: invalid size %d passed\n", size); 1745 err = DDI_FAILURE; 1746 goto done; 1747 } 1748 1749 /* 1750 * Grab pokefault mutex since hypervisor does not guarantee 1751 * poke serialization. 1752 */ 1753 if (hp) { 1754 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1755 (ddi_acc_handle_t)hp); 1756 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1757 } else { 1758 mutex_enter(&pec_p->pec_pokefault_mutex); 1759 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1760 } 1761 1762 if (pcie_get_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1763 err = DDI_FAILURE; 1764 goto done; 1765 } 1766 1767 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1768 pokeval, bdf << 8, &wrt_stat); 1769 1770 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1771 err = DDI_FAILURE; 1772 #ifdef DEBUG 1773 px_pokefault_cnt++; 1774 #endif 1775 /* 1776 * For CAUTIOUS and POKE access, notify FMA to 1777 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1778 */ 1779 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1780 (hp ? DDI_FM_ERR_EXPECTED : 1781 DDI_FM_ERR_POKE), ra); 1782 1783 pec_p->pec_ontrap_data = NULL; 1784 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1785 if (hp) { 1786 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1787 (ddi_acc_handle_t)hp); 1788 } else { 1789 mutex_exit(&pec_p->pec_pokefault_mutex); 1790 } 1791 goto done; 1792 } 1793 1794 pec_p->pec_ontrap_data = NULL; 1795 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1796 if (hp) { 1797 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1798 (ddi_acc_handle_t)hp); 1799 } else { 1800 mutex_exit(&pec_p->pec_pokefault_mutex); 1801 } 1802 1803 host_addr += size; 1804 1805 if (in_args->flags == DDI_DEV_AUTOINCR) { 1806 dev_addr += size; 1807 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1808 } 1809 } 1810 1811 done: 1812 return (err); 1813 } 1814 1815 1816 /*ARGSUSED*/ 1817 int 1818 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1819 peekpoke_ctlops_t *in_args, void *result) 1820 { 1821 px_t *px_p = DIP_TO_STATE(dip); 1822 px_pec_t *pec_p = px_p->px_pec_p; 1823 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1824 1825 size_t repcount = in_args->repcount; 1826 uintptr_t dev_addr = in_args->dev_addr; 1827 uintptr_t host_addr = in_args->host_addr; 1828 1829 r_addr_t ra; 1830 uint32_t read_status; 1831 uint64_t hvio_peek_status; 1832 uint64_t peekval; 1833 int err = DDI_SUCCESS; 1834 1835 result = (void *)in_args->host_addr; 1836 1837 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1838 for (; repcount; repcount--) { 1839 1840 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1841 if (hp) { 1842 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1843 (ddi_acc_handle_t)hp); 1844 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1845 } else { 1846 mutex_enter(&pec_p->pec_pokefault_mutex); 1847 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1848 } 1849 1850 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1851 in_args->size, &read_status, &peekval); 1852 1853 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1854 err = DDI_FAILURE; 1855 1856 /* 1857 * For CAUTIOUS and PEEK access, notify FMA to 1858 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1859 */ 1860 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1861 (hp ? DDI_FM_ERR_EXPECTED : 1862 DDI_FM_ERR_PEEK), ra); 1863 1864 /* Stuff FFs in host addr if peek. */ 1865 if (hp == NULL) { 1866 int i; 1867 uint8_t *ff_addr = (uint8_t *)host_addr; 1868 for (i = 0; i < in_args->size; i++) 1869 *ff_addr++ = 0xff; 1870 } 1871 #ifdef DEBUG 1872 px_peekfault_cnt++; 1873 #endif 1874 pec_p->pec_ontrap_data = NULL; 1875 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1876 if (hp) { 1877 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1878 (ddi_acc_handle_t)hp); 1879 } else { 1880 mutex_exit(&pec_p->pec_pokefault_mutex); 1881 } 1882 goto done; 1883 1884 } 1885 pec_p->pec_ontrap_data = NULL; 1886 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1887 if (hp) { 1888 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1889 (ddi_acc_handle_t)hp); 1890 } else { 1891 mutex_exit(&pec_p->pec_pokefault_mutex); 1892 } 1893 1894 switch (in_args->size) { 1895 case sizeof (uint8_t): 1896 *(uint8_t *)host_addr = (uint8_t)peekval; 1897 break; 1898 case sizeof (uint16_t): 1899 *(uint16_t *)host_addr = (uint16_t)peekval; 1900 break; 1901 case sizeof (uint32_t): 1902 *(uint32_t *)host_addr = (uint32_t)peekval; 1903 break; 1904 case sizeof (uint64_t): 1905 *(uint64_t *)host_addr = (uint64_t)peekval; 1906 break; 1907 default: 1908 DBG(DBG_MAP, px_p->px_dip, 1909 "peek: invalid size %d passed\n", 1910 in_args->size); 1911 err = DDI_FAILURE; 1912 goto done; 1913 } 1914 1915 host_addr += in_args->size; 1916 1917 if (in_args->flags == DDI_DEV_AUTOINCR) { 1918 dev_addr += in_args->size; 1919 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1920 } 1921 } 1922 done: 1923 return (err); 1924 } 1925 1926 1927 /* add interrupt vector */ 1928 int 1929 px_err_add_intr(px_fault_t *px_fault_p) 1930 { 1931 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1932 1933 DBG(DBG_LIB_INT, px_p->px_dip, 1934 "px_err_add_intr: calling add_ivintr"); 1935 1936 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1937 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL, 1938 (caddr_t)&px_fault_p->px_intr_payload[0]) == 0); 1939 1940 DBG(DBG_LIB_INT, px_p->px_dip, 1941 "px_err_add_intr: ib_intr_enable "); 1942 1943 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1944 1945 return (DDI_SUCCESS); 1946 } 1947 1948 /* remove interrupt vector */ 1949 void 1950 px_err_rem_intr(px_fault_t *px_fault_p) 1951 { 1952 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1953 1954 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1955 IB_INTR_WAIT); 1956 1957 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 1958 } 1959 1960 void 1961 px_cb_intr_redist(void *arg) 1962 { 1963 px_t *px_p = (px_t *)arg; 1964 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1965 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1966 } 1967 1968 int 1969 px_cb_add_intr(px_fault_t *f_p) 1970 { 1971 px_t *px_p = DIP_TO_STATE(f_p->px_fh_dip); 1972 1973 DBG(DBG_LIB_INT, px_p->px_dip, 1974 "px_err_add_intr: calling add_ivintr"); 1975 1976 VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL, 1977 (intrfunc)f_p->px_err_func, (caddr_t)f_p, NULL, 1978 (caddr_t)&f_p->px_intr_payload[0]) == 0); 1979 1980 intr_dist_add(px_cb_intr_redist, px_p); 1981 1982 DBG(DBG_LIB_INT, px_p->px_dip, 1983 "px_err_add_intr: ib_intr_enable "); 1984 1985 px_ib_intr_enable(px_p, intr_dist_cpuid(), f_p->px_intr_ino); 1986 1987 return (DDI_SUCCESS); 1988 } 1989 1990 void 1991 px_cb_rem_intr(px_fault_t *f_p) 1992 { 1993 intr_dist_rem(px_cb_intr_redist, DIP_TO_STATE(f_p->px_fh_dip)); 1994 px_err_rem_intr(f_p); 1995 } 1996 1997 #ifdef FMA 1998 void 1999 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 2000 { 2001 px_pec_err_t *err_pkt; 2002 2003 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 2004 2005 /* initialise all the structure members */ 2006 rc_status->status_valid = 0; 2007 2008 if (err_pkt->pec_descr.P) { 2009 /* PCI Status Register */ 2010 rc_status->pci_err_status = err_pkt->pci_err_status; 2011 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 2012 } 2013 2014 if (err_pkt->pec_descr.E) { 2015 /* PCIe Status Register */ 2016 rc_status->pcie_err_status = err_pkt->pcie_err_status; 2017 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 2018 } 2019 2020 if (err_pkt->pec_descr.U) { 2021 rc_status->ue_status = err_pkt->ue_reg_status; 2022 rc_status->status_valid |= UE_STATUS_VALID; 2023 } 2024 2025 if (err_pkt->pec_descr.H) { 2026 rc_status->ue_hdr1 = err_pkt->hdr[0]; 2027 rc_status->status_valid |= UE_HDR1_VALID; 2028 } 2029 2030 if (err_pkt->pec_descr.I) { 2031 rc_status->ue_hdr2 = err_pkt->hdr[1]; 2032 rc_status->status_valid |= UE_HDR2_VALID; 2033 } 2034 2035 /* ue_fst_err_ptr - not available for sun4v?? */ 2036 2037 2038 if (err_pkt->pec_descr.S) { 2039 rc_status->source_id = err_pkt->err_src_reg; 2040 rc_status->status_valid |= SOURCE_ID_VALID; 2041 } 2042 2043 if (err_pkt->pec_descr.R) { 2044 rc_status->root_err_status = err_pkt->root_err_status; 2045 rc_status->status_valid |= CE_STATUS_VALID; 2046 } 2047 } 2048 #endif 2049 2050 /*ARGSUSED*/ 2051 int 2052 px_lib_pmctl(int cmd, px_t *px_p) 2053 { 2054 return (DDI_FAILURE); 2055 } 2056 2057 /*ARGSUSED*/ 2058 uint_t 2059 px_pmeq_intr(caddr_t arg) 2060 { 2061 return (DDI_INTR_CLAIMED); 2062 } 2063 2064 /* 2065 * fetch the config space base addr of the root complex 2066 * note this depends on px structure being initialized 2067 */ 2068 uint64_t 2069 px_lib_get_cfgacc_base(dev_info_t *dip) 2070 { 2071 int instance = DIP_TO_INST(dip); 2072 px_t *px_p = INST_TO_STATE(instance); 2073 2074 return (px_p->px_dev_hdl); 2075 } 2076 2077 void 2078 px_panic_domain(px_t *px_p, pcie_req_id_t bdf) 2079 { 2080 uint64_t ret; 2081 dev_info_t *dip = px_p->px_dip; 2082 2083 DBG(DBG_ERR_INTR, dip, "px_panic_domain: handle 0x%lx, ino %d, " 2084 "bdf<<8 0x%lx\n", 2085 (uint64_t)DIP_TO_HANDLE(dip), px_p->px_cb_fault.px_intr_ino, 2086 (pci_device_t)bdf << 8); 2087 if ((ret = pci_error_send(DIP_TO_HANDLE(dip), 2088 px_p->px_cb_fault.px_intr_ino, (pci_device_t)bdf << 8)) != H_EOK) { 2089 DBG(DBG_ERR_INTR, dip, "pci_error_send failed, ret 0x%lx\n", 2090 ret); 2091 } else 2092 DBG(DBG_ERR_INTR, dip, "pci_error_send worked\n"); 2093 } 2094 2095 /*ARGSUSED*/ 2096 int 2097 px_lib_hotplug_init(dev_info_t *dip, void *arg) 2098 { 2099 return (DDI_ENOTSUP); 2100 } 2101 2102 /*ARGSUSED*/ 2103 void 2104 px_lib_hotplug_uninit(dev_info_t *dip) 2105 { 2106 } 2107 2108 /*ARGSUSED*/ 2109 void 2110 px_hp_intr_redist(px_t *px_p) 2111 { 2112 } 2113 2114 /* Dummy cpr add callback */ 2115 /*ARGSUSED*/ 2116 void 2117 px_cpr_add_callb(px_t *px_p) 2118 { 2119 } 2120 2121 /* Dummy cpr rem callback */ 2122 /*ARGSUSED*/ 2123 void 2124 px_cpr_rem_callb(px_t *px_p) 2125 { 2126 } 2127 2128 /*ARGSUSED*/ 2129 boolean_t 2130 px_lib_is_in_drain_state(px_t *px_p) 2131 { 2132 return (B_FALSE); 2133 } 2134 2135 /* 2136 * There is no IOAPI to get the BDF of the pcie root port nexus at this moment. 2137 * Assume it is 0x0000, until otherwise noted. For now, all sun4v platforms 2138 * have programmed the BDF to be 0x0000. 2139 */ 2140 /*ARGSUSED*/ 2141 pcie_req_id_t 2142 px_lib_get_bdf(px_t *px_p) 2143 { 2144 return (0x0000); 2145 } 2146 2147 int 2148 px_lib_get_root_complex_mps(px_t *px_p, dev_info_t *dip, int *mps) 2149 { 2150 pci_device_t bdf = px_lib_get_bdf(px_p); 2151 2152 if (hvio_get_rp_mps_cap(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK) 2153 return (DDI_SUCCESS); 2154 else 2155 return (DDI_FAILURE); 2156 } 2157 2158 int 2159 px_lib_set_root_complex_mps(px_t *px_p, dev_info_t *dip, int mps) 2160 { 2161 pci_device_t bdf = px_lib_get_bdf(px_p); 2162 2163 if (hvio_set_rp_mps(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK) 2164 return (DDI_SUCCESS); 2165 else 2166 return (DDI_FAILURE); 2167 } 2168 2169 static int 2170 px_lib_do_count_waiting_dev(dev_info_t *dip, void *arg) 2171 { 2172 int *count = (int *)arg; 2173 dev_info_t *cdip = ddi_get_child(dip); 2174 2175 while (cdip != NULL) { 2176 /* check if this is an assigned device */ 2177 if (ddi_prop_exists(DDI_DEV_T_NONE, cdip, DDI_PROP_DONTPASS, 2178 "ddi-assigned")) { 2179 DBG(DBG_ATTACH, dip, "px_lib_do_count_waiting_dev: " 2180 "Found an assigned dev %p, under bridge %p", 2181 cdip, dip); 2182 2183 /* 2184 * Mark this bridge as needing waiting for 2185 * CHILD_LOANED will be removed after bridge reports 2186 * its readyness back to px driver 2187 */ 2188 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 2189 CHILD_LOANED, 1) == DDI_PROP_SUCCESS) 2190 (*count)++; 2191 break; 2192 } 2193 cdip = ddi_get_next_sibling(cdip); 2194 } 2195 2196 return (DDI_WALK_CONTINUE); 2197 } 2198 2199 static int 2200 px_lib_count_waiting_dev(dev_info_t *dip) 2201 { 2202 int circular_count; 2203 int count = 0; 2204 2205 /* No need to continue if this system is not SDIO capable */ 2206 if (px_sdio_users == 0) 2207 return (0); 2208 2209 /* see if px iteslf has assigned children */ 2210 (void) px_lib_do_count_waiting_dev(dip, &count); 2211 2212 /* scan dev under this px */ 2213 ndi_devi_enter(dip, &circular_count); 2214 ddi_walk_devs(ddi_get_child(dip), px_lib_do_count_waiting_dev, &count); 2215 ndi_devi_exit(dip, circular_count); 2216 return (count); 2217 } 2218 2219 /* Called from px/bridge driver directly to report its readyness */ 2220 int 2221 px_lib_fabric_sync(dev_info_t *dip) 2222 { 2223 px_t *px; 2224 dev_info_t *rcdip; 2225 int waitdev; 2226 2227 /* No need to continue if this system is not SDIO capable */ 2228 if (px_sdio_users == 0) 2229 return (DDI_SUCCESS); 2230 2231 /* a valid bridge w/ assigned dev under it? */ 2232 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, CHILD_LOANED) != 2233 DDI_PROP_SUCCESS) 2234 return (DDI_FAILURE); 2235 2236 /* find out RC dip */ 2237 for (rcdip = dip; rcdip != NULL; rcdip = ddi_get_parent(rcdip)) { 2238 if (PCIE_DIP2BUS(rcdip) && PCIE_IS_RC(PCIE_DIP2BUS(rcdip))) 2239 break; 2240 } 2241 if ((rcdip == NULL) || ((px = (px_t *)DIP_TO_STATE(rcdip)) == NULL)) 2242 return (DDI_FAILURE); 2243 2244 /* are we ready? */ 2245 waitdev = (int)(uintptr_t)px->px_plat_p; 2246 ASSERT(waitdev); 2247 DBG(DBG_CTLOPS, rcdip, "px_lib_fabric_sync: " 2248 "Px/bridge %p is ready, %d left", rcdip, waitdev - 1); 2249 --waitdev; 2250 px->px_plat_p = (void *)(uintptr_t)waitdev; 2251 if (waitdev != 0) 2252 return (DDI_SUCCESS); 2253 2254 /* notify hpyervisor */ 2255 DBG(DBG_CTLOPS, rcdip, "px_lib_fabric_sync: " 2256 "Notifying HV that RC %p is ready users=%d", rcdip, px_sdio_users); 2257 2258 if (pci_iov_root_configured(px->px_dev_hdl) != H_EOK) 2259 return (DDI_FAILURE); 2260 2261 return (DDI_SUCCESS); 2262 } 2263