1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ib_ino_info_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 /* 326 * If HV VPCI version is 1.1 and higher, pass the BDF, phantom 327 * function, and relax ordering information. Otherwise, justp pass 328 * read or write attribute information. 329 */ 330 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 331 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 332 333 while ((ttes_mapped = pfn_p - pfns) < pages) { 334 uintptr_t ra = va_to_pa(pfn_p); 335 pages_t ttes2map; 336 uint64_t ret; 337 338 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 339 ra = MMU_PTOB(MMU_BTOP(ra)); 340 341 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 342 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 343 344 ttes_mapped = 0; 345 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 346 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 347 ttes2map, attr, (io_page_list_t *)(ra | 348 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 349 &ttes_mapped)) != H_EOK) { 350 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 351 "ret 0x%lx\n", ret); 352 353 ttes_mapped = pfn_p - pfns; 354 err = DDI_FAILURE; 355 goto cleanup; 356 } 357 358 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 359 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 360 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 361 tsb_index + (pfn_p - pfns), ttes2map, attr, 362 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 363 ttes_mapped); 364 } 365 } 366 367 cleanup: 368 if ((err == DDI_FAILURE) && ttes_mapped) 369 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 370 371 kmem_free(pfns, pages * sizeof (io_page_list_t)); 372 return (err); 373 } 374 375 /*ARGSUSED*/ 376 int 377 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 378 { 379 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 380 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 381 pages_t ttes2demap, ttes_demapped = 0; 382 uint64_t ret; 383 384 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 385 "pages 0x%x\n", dip, tsbid, pages); 386 387 for (ttes2demap = pages; ttes2demap; 388 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 389 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 390 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 391 &ttes_demapped)) != H_EOK) { 392 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 393 "ret 0x%lx\n", ret); 394 395 return (DDI_FAILURE); 396 } 397 398 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 399 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 400 tsb_num, tsb_index, ttes2demap, ttes_demapped); 401 } 402 403 return (DDI_SUCCESS); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 409 r_addr_t *r_addr_p) 410 { 411 uint64_t ret; 412 413 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 414 dip, tsbid); 415 416 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 417 attr_p, r_addr_p)) != H_EOK) { 418 DBG(DBG_LIB_DMA, dip, 419 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 420 421 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 422 } 423 424 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 425 *attr_p, *r_addr_p); 426 427 return (DDI_SUCCESS); 428 } 429 430 /* 431 * fetch chip's range propery's value. For sun4v, config space base 432 * is not used (pxtool_get_phys_addr) will return zero, so just return 433 * zero for px_get_range_prop(). 434 */ 435 /*ARGSUSED*/ 436 uint64_t 437 px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank) 438 { 439 return (0); 440 } 441 442 /* 443 * Checks dma attributes against system bypass ranges 444 * A sun4v device must be capable of generating the entire 64-bit 445 * address in order to perform bypass DMA. 446 */ 447 /*ARGSUSED*/ 448 int 449 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 450 uint64_t *lo_p, uint64_t *hi_p) 451 { 452 if ((attr_p->dma_attr_addr_lo != 0ull) || 453 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 454 455 return (DDI_DMA_BADATTR); 456 } 457 458 *lo_p = 0ull; 459 *hi_p = UINT64_MAX; 460 461 return (DDI_SUCCESS); 462 } 463 464 465 /*ARGSUSED*/ 466 int 467 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 468 io_addr_t *io_addr_p) 469 { 470 uint64_t ret; 471 472 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 473 "attr 0x%x\n", dip, ra, attr); 474 475 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 476 attr, io_addr_p)) != H_EOK) { 477 DBG(DBG_LIB_DMA, dip, 478 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 479 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 480 } 481 482 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 483 *io_addr_p); 484 485 return (DDI_SUCCESS); 486 } 487 488 /*ARGSUSED*/ 489 int 490 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 491 off_t off, size_t len, uint_t cache_flags) 492 { 493 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 494 uint64_t sync_dir; 495 px_dvma_addr_t dvma_addr, pg_off; 496 size_t num_sync; 497 uint64_t status = H_EOK; 498 499 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 500 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 501 dip, rdip, handle, off, len, cache_flags); 502 503 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 504 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 505 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 506 return (DDI_FAILURE); 507 } 508 509 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 510 return (DDI_SUCCESS); 511 512 if (!len) 513 len = mp->dmai_size; 514 515 pg_off = mp->dmai_offset; /* start min */ 516 dvma_addr = MAX(off, pg_off); /* lo */ 517 pg_off += mp->dmai_size; /* end max */ 518 pg_off = MIN(off + len, pg_off); /* hi */ 519 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 520 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 521 ddi_driver_name(rdip), ddi_get_instance(rdip), 522 off, len, mp->dmai_offset, 523 mp->dmai_offset + mp->dmai_size); 524 return (DDI_FAILURE); 525 } 526 527 len = pg_off - dvma_addr; /* sz = hi - lo */ 528 dvma_addr += mp->dmai_mapping; /* start addr */ 529 530 if (mp->dmai_rflags & DDI_DMA_READ) 531 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 532 else 533 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 534 535 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 536 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 537 sync_dir, &num_sync); 538 dvma_addr += num_sync; 539 } 540 541 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 542 } 543 544 545 /* 546 * MSIQ Functions: 547 */ 548 549 /*ARGSUSED*/ 550 int 551 px_lib_msiq_init(dev_info_t *dip) 552 { 553 px_t *px_p = DIP_TO_STATE(dip); 554 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 555 uint64_t *msiq_addr, ra; 556 size_t msiq_size; 557 uint_t rec_cnt; 558 int i, err = DDI_SUCCESS; 559 uint64_t ret; 560 561 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 562 563 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 564 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 565 566 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 567 568 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 569 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 570 571 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 572 (i + msiq_state_p->msiq_1st_msiq_id), 573 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 574 DBG(DBG_LIB_MSIQ, dip, 575 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 576 err = DDI_FAILURE; 577 break; 578 } 579 580 if ((err = px_lib_msiq_info(dip, 581 (i + msiq_state_p->msiq_1st_msiq_id), 582 &ra, &rec_cnt)) != DDI_SUCCESS) { 583 DBG(DBG_LIB_MSIQ, dip, 584 "px_lib_msiq_info failed, ret 0x%x\n", err); 585 err = DDI_FAILURE; 586 break; 587 } 588 589 DBG(DBG_LIB_MSIQ, dip, 590 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 591 } 592 593 return (err); 594 } 595 596 /*ARGSUSED*/ 597 int 598 px_lib_msiq_fini(dev_info_t *dip) 599 { 600 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 601 602 return (DDI_SUCCESS); 603 } 604 605 /*ARGSUSED*/ 606 int 607 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 608 uint_t *msiq_rec_cnt_p) 609 { 610 uint64_t ret; 611 612 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 613 dip, msiq_id); 614 615 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 616 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 617 DBG(DBG_LIB_MSIQ, dip, 618 "hvio_msiq_info failed, ret 0x%lx\n", ret); 619 return (DDI_FAILURE); 620 } 621 622 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 623 ra_p, *msiq_rec_cnt_p); 624 625 return (DDI_SUCCESS); 626 } 627 628 /*ARGSUSED*/ 629 int 630 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 631 pci_msiq_valid_state_t *msiq_valid_state) 632 { 633 uint64_t ret; 634 635 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 636 dip, msiq_id); 637 638 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 639 msiq_id, msiq_valid_state)) != H_EOK) { 640 DBG(DBG_LIB_MSIQ, dip, 641 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 642 return (DDI_FAILURE); 643 } 644 645 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 646 *msiq_valid_state); 647 648 return (DDI_SUCCESS); 649 } 650 651 /*ARGSUSED*/ 652 int 653 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 654 pci_msiq_valid_state_t msiq_valid_state) 655 { 656 uint64_t ret; 657 658 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 659 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 660 661 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 662 msiq_id, msiq_valid_state)) != H_EOK) { 663 DBG(DBG_LIB_MSIQ, dip, 664 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 665 return (DDI_FAILURE); 666 } 667 668 return (DDI_SUCCESS); 669 } 670 671 /*ARGSUSED*/ 672 int 673 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 674 pci_msiq_state_t *msiq_state) 675 { 676 uint64_t ret; 677 678 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 679 dip, msiq_id); 680 681 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 682 msiq_id, msiq_state)) != H_EOK) { 683 DBG(DBG_LIB_MSIQ, dip, 684 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 685 return (DDI_FAILURE); 686 } 687 688 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 689 *msiq_state); 690 691 return (DDI_SUCCESS); 692 } 693 694 /*ARGSUSED*/ 695 int 696 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 697 pci_msiq_state_t msiq_state) 698 { 699 uint64_t ret; 700 701 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 702 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 703 704 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 705 msiq_id, msiq_state)) != H_EOK) { 706 DBG(DBG_LIB_MSIQ, dip, 707 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 708 return (DDI_FAILURE); 709 } 710 711 return (DDI_SUCCESS); 712 } 713 714 /*ARGSUSED*/ 715 int 716 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 717 msiqhead_t *msiq_head_p) 718 { 719 uint64_t ret; 720 721 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 722 dip, msiq_id); 723 724 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 725 msiq_id, msiq_head_p)) != H_EOK) { 726 DBG(DBG_LIB_MSIQ, dip, 727 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 728 return (DDI_FAILURE); 729 } 730 731 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 732 733 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 734 *msiq_head_p); 735 736 return (DDI_SUCCESS); 737 } 738 739 /*ARGSUSED*/ 740 int 741 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 742 msiqhead_t msiq_head) 743 { 744 uint64_t ret; 745 746 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 747 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 748 749 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 750 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 751 DBG(DBG_LIB_MSIQ, dip, 752 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 753 return (DDI_FAILURE); 754 } 755 756 return (DDI_SUCCESS); 757 } 758 759 /*ARGSUSED*/ 760 int 761 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 762 msiqtail_t *msiq_tail_p) 763 { 764 uint64_t ret; 765 766 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 767 dip, msiq_id); 768 769 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 770 msiq_id, msiq_tail_p)) != H_EOK) { 771 DBG(DBG_LIB_MSIQ, dip, 772 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 773 return (DDI_FAILURE); 774 } 775 776 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 777 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 778 *msiq_tail_p); 779 780 return (DDI_SUCCESS); 781 } 782 783 /*ARGSUSED*/ 784 void 785 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 786 { 787 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 788 789 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 790 791 if (!curr_msiq_rec_p->msiq_rec_type) 792 return; 793 794 *msiq_rec_p = *curr_msiq_rec_p; 795 796 /* Zero out msiq_rec_type field */ 797 curr_msiq_rec_p->msiq_rec_type = 0; 798 } 799 800 /* 801 * MSI Functions: 802 */ 803 804 /*ARGSUSED*/ 805 int 806 px_lib_msi_init(dev_info_t *dip) 807 { 808 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 809 810 /* Noop */ 811 return (DDI_SUCCESS); 812 } 813 814 /*ARGSUSED*/ 815 int 816 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 817 msiqid_t *msiq_id) 818 { 819 uint64_t ret; 820 821 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 822 dip, msi_num); 823 824 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 825 msi_num, msiq_id)) != H_EOK) { 826 DBG(DBG_LIB_MSI, dip, 827 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 828 return (DDI_FAILURE); 829 } 830 831 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 832 *msiq_id); 833 834 return (DDI_SUCCESS); 835 } 836 837 /*ARGSUSED*/ 838 int 839 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 840 msiqid_t msiq_id, msi_type_t msitype) 841 { 842 uint64_t ret; 843 844 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 845 "msq_id 0x%x\n", dip, msi_num, msiq_id); 846 847 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 848 msi_num, msiq_id, msitype)) != H_EOK) { 849 DBG(DBG_LIB_MSI, dip, 850 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 851 return (DDI_FAILURE); 852 } 853 854 return (DDI_SUCCESS); 855 } 856 857 /*ARGSUSED*/ 858 int 859 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 860 pci_msi_valid_state_t *msi_valid_state) 861 { 862 uint64_t ret; 863 864 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 865 dip, msi_num); 866 867 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 868 msi_num, msi_valid_state)) != H_EOK) { 869 DBG(DBG_LIB_MSI, dip, 870 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 871 return (DDI_FAILURE); 872 } 873 874 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 875 *msi_valid_state); 876 877 return (DDI_SUCCESS); 878 } 879 880 /*ARGSUSED*/ 881 int 882 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 883 pci_msi_valid_state_t msi_valid_state) 884 { 885 uint64_t ret; 886 887 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 888 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 889 890 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 891 msi_num, msi_valid_state)) != H_EOK) { 892 DBG(DBG_LIB_MSI, dip, 893 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 894 return (DDI_FAILURE); 895 } 896 897 return (DDI_SUCCESS); 898 } 899 900 /*ARGSUSED*/ 901 int 902 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 903 pci_msi_state_t *msi_state) 904 { 905 uint64_t ret; 906 907 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 908 dip, msi_num); 909 910 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 911 msi_num, msi_state)) != H_EOK) { 912 DBG(DBG_LIB_MSI, dip, 913 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 914 return (DDI_FAILURE); 915 } 916 917 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 918 *msi_state); 919 920 return (DDI_SUCCESS); 921 } 922 923 /*ARGSUSED*/ 924 int 925 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 926 pci_msi_state_t msi_state) 927 { 928 uint64_t ret; 929 930 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 931 "msi_state 0x%x\n", dip, msi_num, msi_state); 932 933 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 934 msi_num, msi_state)) != H_EOK) { 935 DBG(DBG_LIB_MSI, dip, 936 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 937 return (DDI_FAILURE); 938 } 939 940 return (DDI_SUCCESS); 941 } 942 943 /* 944 * MSG Functions: 945 */ 946 947 /*ARGSUSED*/ 948 int 949 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 950 msiqid_t *msiq_id) 951 { 952 uint64_t ret; 953 954 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 955 dip, msg_type); 956 957 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 958 msg_type, msiq_id)) != H_EOK) { 959 DBG(DBG_LIB_MSG, dip, 960 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 961 return (DDI_FAILURE); 962 } 963 964 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 965 *msiq_id); 966 967 return (DDI_SUCCESS); 968 } 969 970 /*ARGSUSED*/ 971 int 972 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 973 msiqid_t msiq_id) 974 { 975 uint64_t ret; 976 977 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 978 "msq_id 0x%x\n", dip, msg_type, msiq_id); 979 980 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 981 msg_type, msiq_id)) != H_EOK) { 982 DBG(DBG_LIB_MSG, dip, 983 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 984 return (DDI_FAILURE); 985 } 986 987 return (DDI_SUCCESS); 988 } 989 990 /*ARGSUSED*/ 991 int 992 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 993 pcie_msg_valid_state_t *msg_valid_state) 994 { 995 uint64_t ret; 996 997 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 998 dip, msg_type); 999 1000 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1001 msg_valid_state)) != H_EOK) { 1002 DBG(DBG_LIB_MSG, dip, 1003 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1004 return (DDI_FAILURE); 1005 } 1006 1007 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1008 *msg_valid_state); 1009 1010 return (DDI_SUCCESS); 1011 } 1012 1013 /*ARGSUSED*/ 1014 int 1015 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1016 pcie_msg_valid_state_t msg_valid_state) 1017 { 1018 uint64_t ret; 1019 1020 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1021 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1022 1023 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1024 msg_valid_state)) != H_EOK) { 1025 DBG(DBG_LIB_MSG, dip, 1026 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1027 return (DDI_FAILURE); 1028 } 1029 1030 return (DDI_SUCCESS); 1031 } 1032 1033 /* 1034 * Suspend/Resume Functions: 1035 * Currently unsupported by hypervisor and all functions are noops. 1036 */ 1037 /*ARGSUSED*/ 1038 int 1039 px_lib_suspend(dev_info_t *dip) 1040 { 1041 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1042 1043 /* Not supported */ 1044 return (DDI_FAILURE); 1045 } 1046 1047 /*ARGSUSED*/ 1048 void 1049 px_lib_resume(dev_info_t *dip) 1050 { 1051 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1052 1053 /* Noop */ 1054 } 1055 1056 /* 1057 * Misc Functions: 1058 * Currently unsupported by hypervisor and all functions are noops. 1059 */ 1060 /*ARGSUSED*/ 1061 static int 1062 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1063 uint8_t size, pci_cfg_data_t *data_p) 1064 { 1065 uint64_t ret; 1066 1067 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1068 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1069 1070 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1071 size, data_p)) != H_EOK) { 1072 DBG(DBG_LIB_CFG, dip, 1073 "hvio_config_get failed, ret 0x%lx\n", ret); 1074 return (DDI_FAILURE); 1075 } 1076 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1077 1078 return (DDI_SUCCESS); 1079 } 1080 1081 /*ARGSUSED*/ 1082 static int 1083 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1084 uint8_t size, pci_cfg_data_t data) 1085 { 1086 uint64_t ret; 1087 1088 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1089 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1090 1091 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1092 size, data)) != H_EOK) { 1093 DBG(DBG_LIB_CFG, dip, 1094 "hvio_config_put failed, ret 0x%lx\n", ret); 1095 return (DDI_FAILURE); 1096 } 1097 1098 return (DDI_SUCCESS); 1099 } 1100 1101 static uint32_t 1102 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1103 { 1104 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1105 handle->ahi_common.ah_bus_private; 1106 uint32_t pci_dev_addr = px_pvt->raddr; 1107 uint32_t vaddr = px_pvt->vaddr; 1108 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1109 uint32_t rdata = 0; 1110 1111 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1112 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1113 /* XXX update error kstats */ 1114 return (0xffffffff); 1115 return (rdata); 1116 } 1117 1118 static void 1119 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1120 int size, pci_cfg_data_t wdata) 1121 { 1122 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1123 handle->ahi_common.ah_bus_private; 1124 uint32_t pci_dev_addr = px_pvt->raddr; 1125 uint32_t vaddr = px_pvt->vaddr; 1126 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1127 1128 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1129 size, wdata) != DDI_SUCCESS) { 1130 /*EMPTY*/ 1131 /* XXX update error kstats */ 1132 } 1133 } 1134 1135 static uint8_t 1136 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1137 { 1138 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1139 } 1140 1141 static uint16_t 1142 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1143 { 1144 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1145 } 1146 1147 static uint32_t 1148 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1149 { 1150 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1151 } 1152 1153 static uint64_t 1154 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1155 { 1156 uint32_t rdatah, rdatal; 1157 1158 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1159 rdatah = (uint32_t)px_pci_config_get(handle, 1160 (uint32_t *)((char *)addr+4), 4); 1161 return (((uint64_t)rdatah << 32) | rdatal); 1162 } 1163 1164 static void 1165 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1166 { 1167 pci_cfg_data_t wdata = { 0 }; 1168 1169 wdata.qw = (uint8_t)data; 1170 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1171 } 1172 1173 static void 1174 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1175 { 1176 pci_cfg_data_t wdata = { 0 }; 1177 1178 wdata.qw = (uint16_t)data; 1179 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1180 } 1181 1182 static void 1183 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1184 { 1185 pci_cfg_data_t wdata = { 0 }; 1186 1187 wdata.qw = (uint32_t)data; 1188 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1189 } 1190 1191 static void 1192 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1193 { 1194 pci_cfg_data_t wdata = { 0 }; 1195 1196 wdata.qw = (uint32_t)(data & 0xffffffff); 1197 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1198 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1199 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1200 } 1201 1202 static void 1203 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1204 uint8_t *dev_addr, size_t repcount, uint_t flags) 1205 { 1206 if (flags == DDI_DEV_AUTOINCR) 1207 for (; repcount; repcount--) 1208 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1209 else 1210 for (; repcount; repcount--) 1211 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1212 } 1213 1214 /* 1215 * Function to rep read 16 bit data off the PCI configuration space behind 1216 * the 21554's host interface. 1217 */ 1218 static void 1219 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1220 uint16_t *dev_addr, size_t repcount, uint_t flags) 1221 { 1222 if (flags == DDI_DEV_AUTOINCR) 1223 for (; repcount; repcount--) 1224 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1225 else 1226 for (; repcount; repcount--) 1227 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1228 } 1229 1230 /* 1231 * Function to rep read 32 bit data off the PCI configuration space behind 1232 * the 21554's host interface. 1233 */ 1234 static void 1235 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1236 uint32_t *dev_addr, size_t repcount, uint_t flags) 1237 { 1238 if (flags == DDI_DEV_AUTOINCR) 1239 for (; repcount; repcount--) 1240 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1241 else 1242 for (; repcount; repcount--) 1243 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1244 } 1245 1246 /* 1247 * Function to rep read 64 bit data off the PCI configuration space behind 1248 * the 21554's host interface. 1249 */ 1250 static void 1251 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1252 uint64_t *dev_addr, size_t repcount, uint_t flags) 1253 { 1254 if (flags == DDI_DEV_AUTOINCR) 1255 for (; repcount; repcount--) 1256 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1257 else 1258 for (; repcount; repcount--) 1259 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1260 } 1261 1262 /* 1263 * Function to rep write 8 bit data into the PCI configuration space behind 1264 * the 21554's host interface. 1265 */ 1266 static void 1267 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1268 uint8_t *dev_addr, size_t repcount, uint_t flags) 1269 { 1270 if (flags == DDI_DEV_AUTOINCR) 1271 for (; repcount; repcount--) 1272 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1273 else 1274 for (; repcount; repcount--) 1275 px_pci_config_put8(handle, dev_addr, *host_addr++); 1276 } 1277 1278 /* 1279 * Function to rep write 16 bit data into the PCI configuration space behind 1280 * the 21554's host interface. 1281 */ 1282 static void 1283 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1284 uint16_t *dev_addr, size_t repcount, uint_t flags) 1285 { 1286 if (flags == DDI_DEV_AUTOINCR) 1287 for (; repcount; repcount--) 1288 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1289 else 1290 for (; repcount; repcount--) 1291 px_pci_config_put16(handle, dev_addr, *host_addr++); 1292 } 1293 1294 /* 1295 * Function to rep write 32 bit data into the PCI configuration space behind 1296 * the 21554's host interface. 1297 */ 1298 static void 1299 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1300 uint32_t *dev_addr, size_t repcount, uint_t flags) 1301 { 1302 if (flags == DDI_DEV_AUTOINCR) 1303 for (; repcount; repcount--) 1304 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1305 else 1306 for (; repcount; repcount--) 1307 px_pci_config_put32(handle, dev_addr, *host_addr++); 1308 } 1309 1310 /* 1311 * Function to rep write 64 bit data into the PCI configuration space behind 1312 * the 21554's host interface. 1313 */ 1314 static void 1315 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1316 uint64_t *dev_addr, size_t repcount, uint_t flags) 1317 { 1318 if (flags == DDI_DEV_AUTOINCR) 1319 for (; repcount; repcount--) 1320 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1321 else 1322 for (; repcount; repcount--) 1323 px_pci_config_put64(handle, dev_addr, *host_addr++); 1324 } 1325 1326 /* 1327 * Provide a private access handle to route config access calls to Hypervisor. 1328 * Beware: Do all error checking for config space accesses before calling 1329 * this function. ie. do error checking from the calling function. 1330 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1331 * DDI_SUCCESS from here makes the code organization readable/easier from 1332 * the generic code. 1333 */ 1334 /*ARGSUSED*/ 1335 int 1336 px_lib_map_vconfig(dev_info_t *dip, 1337 ddi_map_req_t *mp, pci_config_offset_t off, 1338 pci_regspec_t *rp, caddr_t *addrp) 1339 { 1340 ddi_acc_hdl_t *hp; 1341 ddi_acc_impl_t *ap; 1342 uchar_t busnum; /* bus number */ 1343 uchar_t devnum; /* device number */ 1344 uchar_t funcnum; /* function number */ 1345 px_config_acc_pvt_t *px_pvt; 1346 1347 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1348 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1349 1350 /* Check for mapping teardown operation */ 1351 if ((mp->map_op == DDI_MO_UNMAP) || 1352 (mp->map_op == DDI_MO_UNLOCK)) { 1353 /* free up memory allocated for the private access handle. */ 1354 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1355 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1356 1357 /* unmap operation of PCI IO/config space. */ 1358 return (DDI_SUCCESS); 1359 } 1360 1361 ap->ahi_get8 = px_pci_config_get8; 1362 ap->ahi_get16 = px_pci_config_get16; 1363 ap->ahi_get32 = px_pci_config_get32; 1364 ap->ahi_get64 = px_pci_config_get64; 1365 ap->ahi_put8 = px_pci_config_put8; 1366 ap->ahi_put16 = px_pci_config_put16; 1367 ap->ahi_put32 = px_pci_config_put32; 1368 ap->ahi_put64 = px_pci_config_put64; 1369 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1370 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1371 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1372 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1373 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1374 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1375 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1376 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1377 1378 /* Initialize to default check/notify functions */ 1379 ap->ahi_fault = 0; 1380 ap->ahi_fault_check = i_ddi_acc_fault_check; 1381 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1382 1383 /* allocate memory for our private handle */ 1384 px_pvt = (px_config_acc_pvt_t *) 1385 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1386 hp->ah_bus_private = (void *)px_pvt; 1387 1388 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1389 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1390 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1391 1392 /* set up private data for use during IO routines */ 1393 1394 /* addr needed by the HV APIs */ 1395 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1396 /* 1397 * Address that specifies the actual offset into the 256MB 1398 * memory mapped configuration space, 4K per device. 1399 * First 12bits form the offset into 4K config space. 1400 * This address is only used during the IO routines to calculate 1401 * the offset at which the transaction must be performed. 1402 * Drivers bypassing DDI functions to access PCI config space will 1403 * panic the system since the following is a bogus virtual address. 1404 */ 1405 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1406 px_pvt->dip = dip; 1407 1408 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1409 px_pvt->raddr, px_pvt->vaddr); 1410 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1411 return (DDI_SUCCESS); 1412 } 1413 1414 /*ARGSUSED*/ 1415 void 1416 px_lib_map_attr_check(ddi_map_req_t *mp) 1417 { 1418 } 1419 1420 /* 1421 * px_lib_log_safeacc_err: 1422 * Imitate a cpu/mem trap call when a peek/poke fails. 1423 * This will initiate something similar to px_fm_callback. 1424 */ 1425 static void 1426 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1427 { 1428 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1429 ddi_fm_error_t derr; 1430 1431 derr.fme_status = DDI_FM_NONFATAL; 1432 derr.fme_version = DDI_FME_VERSION; 1433 derr.fme_flag = fme_flag; 1434 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1435 derr.fme_acc_handle = handle; 1436 if (hp) 1437 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1438 1439 mutex_enter(&px_p->px_fm_mutex); 1440 1441 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1442 1443 mutex_exit(&px_p->px_fm_mutex); 1444 } 1445 1446 1447 #ifdef DEBUG 1448 int px_peekfault_cnt = 0; 1449 int px_pokefault_cnt = 0; 1450 #endif /* DEBUG */ 1451 1452 static int 1453 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1454 { 1455 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1456 pci_regspec_t regspec_array[8]; 1457 pci_regspec_t *regspec = regspec_array; 1458 int buflen = sizeof (regspec_array); 1459 boolean_t kmalloced = B_FALSE; 1460 int status; 1461 1462 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1463 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1464 1465 /* If need more space, fallback to kmem_alloc. */ 1466 if (status == DDI_PROP_BUF_TOO_SMALL) { 1467 regspec = kmem_alloc(buflen, KM_SLEEP); 1468 1469 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1470 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1471 1472 kmalloced = B_TRUE; 1473 } 1474 1475 /* Get phys_hi from first element. All have same bdf. */ 1476 if (status == DDI_PROP_SUCCESS) 1477 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1478 1479 if (kmalloced) 1480 kmem_free(regspec, buflen); 1481 1482 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1483 } 1484 1485 /* 1486 * Do a safe write to a device. 1487 * 1488 * When this function is given a handle (cautious access), all errors are 1489 * suppressed. 1490 * 1491 * When this function is not given a handle (poke), only Unsupported Request 1492 * and Completer Abort errors are suppressed. 1493 * 1494 * In all cases, all errors are returned in the function return status. 1495 */ 1496 1497 int 1498 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1499 peekpoke_ctlops_t *in_args) 1500 { 1501 px_t *px_p = DIP_TO_STATE(dip); 1502 px_pec_t *pec_p = px_p->px_pec_p; 1503 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1504 1505 size_t repcount = in_args->repcount; 1506 size_t size = in_args->size; 1507 uintptr_t dev_addr = in_args->dev_addr; 1508 uintptr_t host_addr = in_args->host_addr; 1509 1510 int err = DDI_SUCCESS; 1511 uint64_t hvio_poke_status; 1512 uint32_t bdf; 1513 uint32_t wrt_stat; 1514 1515 r_addr_t ra; 1516 uint64_t pokeval; 1517 1518 /* 1519 * Used only to notify error handling peek/poke is occuring 1520 * One scenario is when a fabric err as a result of peek/poke. 1521 * However there is no way to guarantee that the fabric error 1522 * handler will occur in the window where otd is set. 1523 */ 1524 on_trap_data_t otd; 1525 1526 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1527 DBG(DBG_LIB_DMA, px_p->px_dip, 1528 "poke: px_lib_bdf_from_dip failed\n"); 1529 err = DDI_FAILURE; 1530 goto done; 1531 } 1532 1533 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1534 for (; repcount; repcount--) { 1535 1536 switch (size) { 1537 case sizeof (uint8_t): 1538 pokeval = *(uint8_t *)host_addr; 1539 break; 1540 case sizeof (uint16_t): 1541 pokeval = *(uint16_t *)host_addr; 1542 break; 1543 case sizeof (uint32_t): 1544 pokeval = *(uint32_t *)host_addr; 1545 break; 1546 case sizeof (uint64_t): 1547 pokeval = *(uint64_t *)host_addr; 1548 break; 1549 default: 1550 DBG(DBG_MAP, px_p->px_dip, 1551 "poke: invalid size %d passed\n", size); 1552 err = DDI_FAILURE; 1553 goto done; 1554 } 1555 1556 /* 1557 * Grab pokefault mutex since hypervisor does not guarantee 1558 * poke serialization. 1559 */ 1560 if (hp) { 1561 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1562 (ddi_acc_handle_t)hp); 1563 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1564 } else { 1565 mutex_enter(&pec_p->pec_pokefault_mutex); 1566 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1567 } 1568 pec_p->pec_ontrap_data = &otd; 1569 1570 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1571 pokeval, bdf, &wrt_stat); 1572 1573 if (otd.ot_trap & OT_DATA_ACCESS) 1574 err = DDI_FAILURE; 1575 1576 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1577 err = DDI_FAILURE; 1578 #ifdef DEBUG 1579 px_pokefault_cnt++; 1580 #endif 1581 /* 1582 * For CAUTIOUS and POKE access, notify FMA to 1583 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1584 */ 1585 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1586 (hp ? DDI_FM_ERR_EXPECTED : 1587 DDI_FM_ERR_POKE)); 1588 1589 pec_p->pec_ontrap_data = NULL; 1590 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1591 if (hp) { 1592 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1593 (ddi_acc_handle_t)hp); 1594 } else { 1595 mutex_exit(&pec_p->pec_pokefault_mutex); 1596 } 1597 goto done; 1598 } 1599 1600 pec_p->pec_ontrap_data = NULL; 1601 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1602 if (hp) { 1603 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1604 (ddi_acc_handle_t)hp); 1605 } else { 1606 mutex_exit(&pec_p->pec_pokefault_mutex); 1607 } 1608 1609 host_addr += size; 1610 1611 if (in_args->flags == DDI_DEV_AUTOINCR) { 1612 dev_addr += size; 1613 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1614 } 1615 } 1616 1617 done: 1618 return (err); 1619 } 1620 1621 1622 /*ARGSUSED*/ 1623 int 1624 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1625 peekpoke_ctlops_t *in_args, void *result) 1626 { 1627 px_t *px_p = DIP_TO_STATE(dip); 1628 px_pec_t *pec_p = px_p->px_pec_p; 1629 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1630 1631 size_t repcount = in_args->repcount; 1632 uintptr_t dev_addr = in_args->dev_addr; 1633 uintptr_t host_addr = in_args->host_addr; 1634 1635 r_addr_t ra; 1636 uint32_t read_status; 1637 uint64_t hvio_peek_status; 1638 uint64_t peekval; 1639 int err = DDI_SUCCESS; 1640 1641 /* 1642 * Used only to notify error handling peek/poke is occuring 1643 * One scenario is when a fabric err as a result of peek/poke. 1644 * However there is no way to guarantee that the fabric error 1645 * handler will occur in the window where otd is set. 1646 */ 1647 on_trap_data_t otd; 1648 1649 result = (void *)in_args->host_addr; 1650 1651 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1652 for (; repcount; repcount--) { 1653 1654 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1655 if (hp) { 1656 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1657 (ddi_acc_handle_t)hp); 1658 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1659 } else { 1660 mutex_enter(&pec_p->pec_pokefault_mutex); 1661 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1662 } 1663 pec_p->pec_ontrap_data = &otd; 1664 1665 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1666 in_args->size, &read_status, &peekval); 1667 1668 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1669 err = DDI_FAILURE; 1670 1671 /* 1672 * For CAUTIOUS and PEEK access, notify FMA to 1673 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1674 */ 1675 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1676 (hp ? DDI_FM_ERR_EXPECTED : 1677 DDI_FM_ERR_PEEK)); 1678 1679 /* Stuff FFs in host addr if peek. */ 1680 if (hp == NULL) { 1681 int i; 1682 uint8_t *ff_addr = (uint8_t *)host_addr; 1683 for (i = 0; i < in_args->size; i++) 1684 *ff_addr++ = 0xff; 1685 } 1686 #ifdef DEBUG 1687 px_peekfault_cnt++; 1688 #endif 1689 pec_p->pec_ontrap_data = NULL; 1690 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1691 if (hp) { 1692 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1693 (ddi_acc_handle_t)hp); 1694 } else { 1695 mutex_exit(&pec_p->pec_pokefault_mutex); 1696 } 1697 goto done; 1698 1699 } 1700 pec_p->pec_ontrap_data = NULL; 1701 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1702 if (hp) { 1703 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1704 (ddi_acc_handle_t)hp); 1705 } else { 1706 mutex_exit(&pec_p->pec_pokefault_mutex); 1707 } 1708 1709 switch (in_args->size) { 1710 case sizeof (uint8_t): 1711 *(uint8_t *)host_addr = (uint8_t)peekval; 1712 break; 1713 case sizeof (uint16_t): 1714 *(uint16_t *)host_addr = (uint16_t)peekval; 1715 break; 1716 case sizeof (uint32_t): 1717 *(uint32_t *)host_addr = (uint32_t)peekval; 1718 break; 1719 case sizeof (uint64_t): 1720 *(uint64_t *)host_addr = (uint64_t)peekval; 1721 break; 1722 default: 1723 DBG(DBG_MAP, px_p->px_dip, 1724 "peek: invalid size %d passed\n", 1725 in_args->size); 1726 err = DDI_FAILURE; 1727 goto done; 1728 } 1729 1730 host_addr += in_args->size; 1731 1732 if (in_args->flags == DDI_DEV_AUTOINCR) { 1733 dev_addr += in_args->size; 1734 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1735 } 1736 } 1737 done: 1738 return (err); 1739 } 1740 1741 1742 /* add interrupt vector */ 1743 int 1744 px_err_add_intr(px_fault_t *px_fault_p) 1745 { 1746 int ret; 1747 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1748 1749 DBG(DBG_LIB_INT, px_p->px_dip, 1750 "px_err_add_intr: calling add_ivintr"); 1751 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1752 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1753 (caddr_t)&px_fault_p->px_intr_payload[0]); 1754 1755 if (ret != DDI_SUCCESS) { 1756 DBG(DBG_LIB_INT, px_p->px_dip, 1757 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1758 1759 return (ret); 1760 } 1761 DBG(DBG_LIB_INT, px_p->px_dip, 1762 "px_err_add_intr: ib_intr_enable "); 1763 1764 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1765 1766 return (ret); 1767 } 1768 1769 /* remove interrupt vector */ 1770 void 1771 px_err_rem_intr(px_fault_t *px_fault_p) 1772 { 1773 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1774 1775 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1776 IB_INTR_WAIT); 1777 1778 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1779 } 1780 1781 int 1782 px_cb_add_intr(px_fault_t *f_p) 1783 { 1784 return (px_err_add_intr(f_p)); 1785 } 1786 1787 void 1788 px_cb_rem_intr(px_fault_t *f_p) 1789 { 1790 px_err_rem_intr(f_p); 1791 } 1792 1793 void 1794 px_cb_intr_redist(px_t *px_p) 1795 { 1796 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1797 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1798 } 1799 1800 #ifdef FMA 1801 void 1802 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1803 { 1804 px_pec_err_t *err_pkt; 1805 1806 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1807 1808 /* initialise all the structure members */ 1809 rc_status->status_valid = 0; 1810 1811 if (err_pkt->pec_descr.P) { 1812 /* PCI Status Register */ 1813 rc_status->pci_err_status = err_pkt->pci_err_status; 1814 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1815 } 1816 1817 if (err_pkt->pec_descr.E) { 1818 /* PCIe Status Register */ 1819 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1820 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1821 } 1822 1823 if (err_pkt->pec_descr.U) { 1824 rc_status->ue_status = err_pkt->ue_reg_status; 1825 rc_status->status_valid |= UE_STATUS_VALID; 1826 } 1827 1828 if (err_pkt->pec_descr.H) { 1829 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1830 rc_status->status_valid |= UE_HDR1_VALID; 1831 } 1832 1833 if (err_pkt->pec_descr.I) { 1834 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1835 rc_status->status_valid |= UE_HDR2_VALID; 1836 } 1837 1838 /* ue_fst_err_ptr - not available for sun4v?? */ 1839 1840 1841 if (err_pkt->pec_descr.S) { 1842 rc_status->source_id = err_pkt->err_src_reg; 1843 rc_status->status_valid |= SOURCE_ID_VALID; 1844 } 1845 1846 if (err_pkt->pec_descr.R) { 1847 rc_status->root_err_status = err_pkt->root_err_status; 1848 rc_status->status_valid |= CE_STATUS_VALID; 1849 } 1850 } 1851 #endif 1852 1853 /*ARGSUSED*/ 1854 int 1855 px_lib_pmctl(int cmd, px_t *px_p) 1856 { 1857 return (DDI_FAILURE); 1858 } 1859 1860 /*ARGSUSED*/ 1861 uint_t 1862 px_pmeq_intr(caddr_t arg) 1863 { 1864 return (DDI_INTR_CLAIMED); 1865 } 1866 1867 /* 1868 * Unprotected raw reads/writes of fabric device's config space. 1869 * Only used for temporary PCI-E Fabric Error Handling. 1870 */ 1871 uint32_t 1872 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1873 uint32_t data = 0; 1874 1875 (void) hvio_config_get(px_p->px_dev_hdl, 1876 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1877 (pci_cfg_data_t *)&data); 1878 1879 return (data); 1880 } 1881 1882 void 1883 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1884 uint32_t val) { 1885 pci_cfg_data_t wdata = { 0 }; 1886 1887 wdata.qw = (uint32_t)val; 1888 (void) hvio_config_put(px_p->px_dev_hdl, 1889 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1890 } 1891 1892 /*ARGSUSED*/ 1893 int 1894 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1895 { 1896 return (DDI_ENOTSUP); 1897 } 1898 1899 /*ARGSUSED*/ 1900 void 1901 px_lib_hotplug_uninit(dev_info_t *dip) 1902 { 1903 } 1904 1905 /* Dummy cpr add callback */ 1906 /*ARGSUSED*/ 1907 void 1908 px_cpr_add_callb(px_t *px_p) 1909 { 1910 } 1911 1912 /* Dummy cpr rem callback */ 1913 /*ARGSUSED*/ 1914 void 1915 px_cpr_rem_callb(px_t *px_p) 1916 { 1917 } 1918