1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ib_ino_info_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 /* 326 * If HV VPCI version is 1.1 and higher, pass the BDF, phantom 327 * function, and relax ordering information. Otherwise, justp pass 328 * read or write attribute information. 329 */ 330 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 331 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 332 333 while ((ttes_mapped = pfn_p - pfns) < pages) { 334 uintptr_t ra = va_to_pa(pfn_p); 335 pages_t ttes2map; 336 uint64_t ret; 337 338 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 339 ra = MMU_PTOB(MMU_BTOP(ra)); 340 341 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 342 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 343 344 ttes_mapped = 0; 345 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 346 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 347 ttes2map, attr, (io_page_list_t *)(ra | 348 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 349 &ttes_mapped)) != H_EOK) { 350 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 351 "ret 0x%lx\n", ret); 352 353 ttes_mapped = pfn_p - pfns; 354 err = DDI_FAILURE; 355 goto cleanup; 356 } 357 358 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 359 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 360 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 361 tsb_index + (pfn_p - pfns), ttes2map, attr, 362 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 363 ttes_mapped); 364 } 365 } 366 367 cleanup: 368 if ((err == DDI_FAILURE) && ttes_mapped) 369 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 370 371 kmem_free(pfns, pages * sizeof (io_page_list_t)); 372 return (err); 373 } 374 375 /*ARGSUSED*/ 376 int 377 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 378 { 379 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 380 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 381 pages_t ttes2demap, ttes_demapped = 0; 382 uint64_t ret; 383 384 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 385 "pages 0x%x\n", dip, tsbid, pages); 386 387 for (ttes2demap = pages; ttes2demap; 388 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 389 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 390 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 391 &ttes_demapped)) != H_EOK) { 392 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 393 "ret 0x%lx\n", ret); 394 395 return (DDI_FAILURE); 396 } 397 398 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 399 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 400 tsb_num, tsb_index, ttes2demap, ttes_demapped); 401 } 402 403 return (DDI_SUCCESS); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 409 r_addr_t *r_addr_p) 410 { 411 uint64_t ret; 412 413 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 414 dip, tsbid); 415 416 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 417 attr_p, r_addr_p)) != H_EOK) { 418 DBG(DBG_LIB_DMA, dip, 419 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 420 421 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 422 } 423 424 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 425 *attr_p, *r_addr_p); 426 427 return (DDI_SUCCESS); 428 } 429 430 /*ARGSUSED*/ 431 uint64_t 432 px_get_rng_parent_hi_mask(px_t *px_p) 433 { 434 return (PX_RANGE_PROP_MASK); 435 } 436 437 /* 438 * Checks dma attributes against system bypass ranges 439 * A sun4v device must be capable of generating the entire 64-bit 440 * address in order to perform bypass DMA. 441 */ 442 /*ARGSUSED*/ 443 int 444 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 445 uint64_t *lo_p, uint64_t *hi_p) 446 { 447 if ((attr_p->dma_attr_addr_lo != 0ull) || 448 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 449 450 return (DDI_DMA_BADATTR); 451 } 452 453 *lo_p = 0ull; 454 *hi_p = UINT64_MAX; 455 456 return (DDI_SUCCESS); 457 } 458 459 460 /*ARGSUSED*/ 461 int 462 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 463 io_addr_t *io_addr_p) 464 { 465 uint64_t ret; 466 467 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 468 "attr 0x%x\n", dip, ra, attr); 469 470 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 471 attr, io_addr_p)) != H_EOK) { 472 DBG(DBG_LIB_DMA, dip, 473 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 474 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 475 } 476 477 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 478 *io_addr_p); 479 480 return (DDI_SUCCESS); 481 } 482 483 /*ARGSUSED*/ 484 int 485 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 486 off_t off, size_t len, uint_t cache_flags) 487 { 488 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 489 uint64_t sync_dir; 490 px_dvma_addr_t dvma_addr, pg_off; 491 size_t num_sync; 492 uint64_t status = H_EOK; 493 494 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 495 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 496 dip, rdip, handle, off, len, cache_flags); 497 498 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 499 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 500 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 501 return (DDI_FAILURE); 502 } 503 504 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 505 return (DDI_SUCCESS); 506 507 if (!len) 508 len = mp->dmai_size; 509 510 pg_off = mp->dmai_offset; /* start min */ 511 dvma_addr = MAX(off, pg_off); /* lo */ 512 pg_off += mp->dmai_size; /* end max */ 513 pg_off = MIN(off + len, pg_off); /* hi */ 514 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 515 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 516 ddi_driver_name(rdip), ddi_get_instance(rdip), 517 off, len, mp->dmai_offset, 518 mp->dmai_offset + mp->dmai_size); 519 return (DDI_FAILURE); 520 } 521 522 len = pg_off - dvma_addr; /* sz = hi - lo */ 523 dvma_addr += mp->dmai_mapping; /* start addr */ 524 525 if (mp->dmai_rflags & DDI_DMA_READ) 526 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 527 else 528 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 529 530 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 531 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 532 sync_dir, &num_sync); 533 dvma_addr += num_sync; 534 } 535 536 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 537 } 538 539 540 /* 541 * MSIQ Functions: 542 */ 543 544 /*ARGSUSED*/ 545 int 546 px_lib_msiq_init(dev_info_t *dip) 547 { 548 px_t *px_p = DIP_TO_STATE(dip); 549 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 550 r_addr_t ra; 551 size_t msiq_size; 552 uint_t rec_cnt; 553 int i, err = DDI_SUCCESS; 554 uint64_t ret; 555 556 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 557 558 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 559 560 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 561 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 562 (i * msiq_size)); 563 564 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 565 (i + msiq_state_p->msiq_1st_msiq_id), 566 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 567 DBG(DBG_LIB_MSIQ, dip, 568 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 569 err = DDI_FAILURE; 570 break; 571 } 572 573 if ((err = px_lib_msiq_info(dip, 574 (i + msiq_state_p->msiq_1st_msiq_id), 575 &ra, &rec_cnt)) != DDI_SUCCESS) { 576 DBG(DBG_LIB_MSIQ, dip, 577 "px_lib_msiq_info failed, ret 0x%x\n", err); 578 err = DDI_FAILURE; 579 break; 580 } 581 582 DBG(DBG_LIB_MSIQ, dip, 583 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 584 } 585 586 return (err); 587 } 588 589 /*ARGSUSED*/ 590 int 591 px_lib_msiq_fini(dev_info_t *dip) 592 { 593 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 594 595 return (DDI_SUCCESS); 596 } 597 598 /*ARGSUSED*/ 599 int 600 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 601 uint_t *msiq_rec_cnt_p) 602 { 603 uint64_t ret; 604 605 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 606 dip, msiq_id); 607 608 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 609 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 610 DBG(DBG_LIB_MSIQ, dip, 611 "hvio_msiq_info failed, ret 0x%lx\n", ret); 612 return (DDI_FAILURE); 613 } 614 615 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 616 ra_p, *msiq_rec_cnt_p); 617 618 return (DDI_SUCCESS); 619 } 620 621 /*ARGSUSED*/ 622 int 623 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 624 pci_msiq_valid_state_t *msiq_valid_state) 625 { 626 uint64_t ret; 627 628 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 629 dip, msiq_id); 630 631 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 632 msiq_id, msiq_valid_state)) != H_EOK) { 633 DBG(DBG_LIB_MSIQ, dip, 634 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 635 return (DDI_FAILURE); 636 } 637 638 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 639 *msiq_valid_state); 640 641 return (DDI_SUCCESS); 642 } 643 644 /*ARGSUSED*/ 645 int 646 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 647 pci_msiq_valid_state_t msiq_valid_state) 648 { 649 uint64_t ret; 650 651 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 652 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 653 654 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 655 msiq_id, msiq_valid_state)) != H_EOK) { 656 DBG(DBG_LIB_MSIQ, dip, 657 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 658 return (DDI_FAILURE); 659 } 660 661 return (DDI_SUCCESS); 662 } 663 664 /*ARGSUSED*/ 665 int 666 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 667 pci_msiq_state_t *msiq_state) 668 { 669 uint64_t ret; 670 671 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 672 dip, msiq_id); 673 674 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 675 msiq_id, msiq_state)) != H_EOK) { 676 DBG(DBG_LIB_MSIQ, dip, 677 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 678 return (DDI_FAILURE); 679 } 680 681 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 682 *msiq_state); 683 684 return (DDI_SUCCESS); 685 } 686 687 /*ARGSUSED*/ 688 int 689 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 690 pci_msiq_state_t msiq_state) 691 { 692 uint64_t ret; 693 694 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 695 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 696 697 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 698 msiq_id, msiq_state)) != H_EOK) { 699 DBG(DBG_LIB_MSIQ, dip, 700 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 701 return (DDI_FAILURE); 702 } 703 704 return (DDI_SUCCESS); 705 } 706 707 /*ARGSUSED*/ 708 int 709 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 710 msiqhead_t *msiq_head_p) 711 { 712 uint64_t ret; 713 714 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 715 dip, msiq_id); 716 717 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 718 msiq_id, msiq_head_p)) != H_EOK) { 719 DBG(DBG_LIB_MSIQ, dip, 720 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 721 return (DDI_FAILURE); 722 } 723 724 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 725 726 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 727 *msiq_head_p); 728 729 return (DDI_SUCCESS); 730 } 731 732 /*ARGSUSED*/ 733 int 734 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 735 msiqhead_t msiq_head) 736 { 737 uint64_t ret; 738 739 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 740 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 741 742 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 743 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 744 DBG(DBG_LIB_MSIQ, dip, 745 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 746 return (DDI_FAILURE); 747 } 748 749 return (DDI_SUCCESS); 750 } 751 752 /*ARGSUSED*/ 753 int 754 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 755 msiqtail_t *msiq_tail_p) 756 { 757 uint64_t ret; 758 759 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 760 dip, msiq_id); 761 762 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 763 msiq_id, msiq_tail_p)) != H_EOK) { 764 DBG(DBG_LIB_MSIQ, dip, 765 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 766 return (DDI_FAILURE); 767 } 768 769 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 770 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 771 *msiq_tail_p); 772 773 return (DDI_SUCCESS); 774 } 775 776 /*ARGSUSED*/ 777 void 778 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 779 msiq_rec_t *msiq_rec_p) 780 { 781 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 782 783 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 784 785 if (!curr_msiq_rec_p->msiq_rec_type) 786 return; 787 788 *msiq_rec_p = *curr_msiq_rec_p; 789 790 /* Zero out msiq_rec_type field */ 791 curr_msiq_rec_p->msiq_rec_type = 0; 792 } 793 794 /* 795 * MSI Functions: 796 */ 797 798 /*ARGSUSED*/ 799 int 800 px_lib_msi_init(dev_info_t *dip) 801 { 802 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 803 804 /* Noop */ 805 return (DDI_SUCCESS); 806 } 807 808 /*ARGSUSED*/ 809 int 810 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 811 msiqid_t *msiq_id) 812 { 813 uint64_t ret; 814 815 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 816 dip, msi_num); 817 818 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 819 msi_num, msiq_id)) != H_EOK) { 820 DBG(DBG_LIB_MSI, dip, 821 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 822 return (DDI_FAILURE); 823 } 824 825 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 826 *msiq_id); 827 828 return (DDI_SUCCESS); 829 } 830 831 /*ARGSUSED*/ 832 int 833 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 834 msiqid_t msiq_id, msi_type_t msitype) 835 { 836 uint64_t ret; 837 838 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 839 "msq_id 0x%x\n", dip, msi_num, msiq_id); 840 841 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 842 msi_num, msiq_id, msitype)) != H_EOK) { 843 DBG(DBG_LIB_MSI, dip, 844 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 845 return (DDI_FAILURE); 846 } 847 848 return (DDI_SUCCESS); 849 } 850 851 /*ARGSUSED*/ 852 int 853 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 854 pci_msi_valid_state_t *msi_valid_state) 855 { 856 uint64_t ret; 857 858 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 859 dip, msi_num); 860 861 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 862 msi_num, msi_valid_state)) != H_EOK) { 863 DBG(DBG_LIB_MSI, dip, 864 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 865 return (DDI_FAILURE); 866 } 867 868 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 869 *msi_valid_state); 870 871 return (DDI_SUCCESS); 872 } 873 874 /*ARGSUSED*/ 875 int 876 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 877 pci_msi_valid_state_t msi_valid_state) 878 { 879 uint64_t ret; 880 881 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 882 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 883 884 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 885 msi_num, msi_valid_state)) != H_EOK) { 886 DBG(DBG_LIB_MSI, dip, 887 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 888 return (DDI_FAILURE); 889 } 890 891 return (DDI_SUCCESS); 892 } 893 894 /*ARGSUSED*/ 895 int 896 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 897 pci_msi_state_t *msi_state) 898 { 899 uint64_t ret; 900 901 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 902 dip, msi_num); 903 904 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 905 msi_num, msi_state)) != H_EOK) { 906 DBG(DBG_LIB_MSI, dip, 907 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 908 return (DDI_FAILURE); 909 } 910 911 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 912 *msi_state); 913 914 return (DDI_SUCCESS); 915 } 916 917 /*ARGSUSED*/ 918 int 919 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 920 pci_msi_state_t msi_state) 921 { 922 uint64_t ret; 923 924 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 925 "msi_state 0x%x\n", dip, msi_num, msi_state); 926 927 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 928 msi_num, msi_state)) != H_EOK) { 929 DBG(DBG_LIB_MSI, dip, 930 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 931 return (DDI_FAILURE); 932 } 933 934 return (DDI_SUCCESS); 935 } 936 937 /* 938 * MSG Functions: 939 */ 940 941 /*ARGSUSED*/ 942 int 943 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 944 msiqid_t *msiq_id) 945 { 946 uint64_t ret; 947 948 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 949 dip, msg_type); 950 951 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 952 msg_type, msiq_id)) != H_EOK) { 953 DBG(DBG_LIB_MSG, dip, 954 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 955 return (DDI_FAILURE); 956 } 957 958 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 959 *msiq_id); 960 961 return (DDI_SUCCESS); 962 } 963 964 /*ARGSUSED*/ 965 int 966 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 967 msiqid_t msiq_id) 968 { 969 uint64_t ret; 970 971 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 972 "msq_id 0x%x\n", dip, msg_type, msiq_id); 973 974 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 975 msg_type, msiq_id)) != H_EOK) { 976 DBG(DBG_LIB_MSG, dip, 977 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 978 return (DDI_FAILURE); 979 } 980 981 return (DDI_SUCCESS); 982 } 983 984 /*ARGSUSED*/ 985 int 986 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 987 pcie_msg_valid_state_t *msg_valid_state) 988 { 989 uint64_t ret; 990 991 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 992 dip, msg_type); 993 994 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 995 msg_valid_state)) != H_EOK) { 996 DBG(DBG_LIB_MSG, dip, 997 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 998 return (DDI_FAILURE); 999 } 1000 1001 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1002 *msg_valid_state); 1003 1004 return (DDI_SUCCESS); 1005 } 1006 1007 /*ARGSUSED*/ 1008 int 1009 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1010 pcie_msg_valid_state_t msg_valid_state) 1011 { 1012 uint64_t ret; 1013 1014 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1015 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1016 1017 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1018 msg_valid_state)) != H_EOK) { 1019 DBG(DBG_LIB_MSG, dip, 1020 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1021 return (DDI_FAILURE); 1022 } 1023 1024 return (DDI_SUCCESS); 1025 } 1026 1027 /* 1028 * Suspend/Resume Functions: 1029 * Currently unsupported by hypervisor and all functions are noops. 1030 */ 1031 /*ARGSUSED*/ 1032 int 1033 px_lib_suspend(dev_info_t *dip) 1034 { 1035 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1036 1037 /* Not supported */ 1038 return (DDI_FAILURE); 1039 } 1040 1041 /*ARGSUSED*/ 1042 void 1043 px_lib_resume(dev_info_t *dip) 1044 { 1045 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1046 1047 /* Noop */ 1048 } 1049 1050 /* 1051 * Misc Functions: 1052 * Currently unsupported by hypervisor and all functions are noops. 1053 */ 1054 /*ARGSUSED*/ 1055 static int 1056 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1057 uint8_t size, pci_cfg_data_t *data_p) 1058 { 1059 uint64_t ret; 1060 1061 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1062 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1063 1064 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1065 size, data_p)) != H_EOK) { 1066 DBG(DBG_LIB_CFG, dip, 1067 "hvio_config_get failed, ret 0x%lx\n", ret); 1068 return (DDI_FAILURE); 1069 } 1070 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1071 1072 return (DDI_SUCCESS); 1073 } 1074 1075 /*ARGSUSED*/ 1076 static int 1077 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1078 uint8_t size, pci_cfg_data_t data) 1079 { 1080 uint64_t ret; 1081 1082 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1083 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1084 1085 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1086 size, data)) != H_EOK) { 1087 DBG(DBG_LIB_CFG, dip, 1088 "hvio_config_put failed, ret 0x%lx\n", ret); 1089 return (DDI_FAILURE); 1090 } 1091 1092 return (DDI_SUCCESS); 1093 } 1094 1095 static uint32_t 1096 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1097 { 1098 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1099 handle->ahi_common.ah_bus_private; 1100 uint32_t pci_dev_addr = px_pvt->raddr; 1101 uint32_t vaddr = px_pvt->vaddr; 1102 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1103 uint32_t rdata = 0; 1104 1105 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1106 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1107 /* XXX update error kstats */ 1108 return (0xffffffff); 1109 return (rdata); 1110 } 1111 1112 static void 1113 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1114 int size, pci_cfg_data_t wdata) 1115 { 1116 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1117 handle->ahi_common.ah_bus_private; 1118 uint32_t pci_dev_addr = px_pvt->raddr; 1119 uint32_t vaddr = px_pvt->vaddr; 1120 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1121 1122 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1123 size, wdata) != DDI_SUCCESS) { 1124 /*EMPTY*/ 1125 /* XXX update error kstats */ 1126 } 1127 } 1128 1129 static uint8_t 1130 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1131 { 1132 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1133 } 1134 1135 static uint16_t 1136 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1137 { 1138 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1139 } 1140 1141 static uint32_t 1142 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1143 { 1144 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1145 } 1146 1147 static uint64_t 1148 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1149 { 1150 uint32_t rdatah, rdatal; 1151 1152 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1153 rdatah = (uint32_t)px_pci_config_get(handle, 1154 (uint32_t *)((char *)addr+4), 4); 1155 return (((uint64_t)rdatah << 32) | rdatal); 1156 } 1157 1158 static void 1159 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1160 { 1161 pci_cfg_data_t wdata = { 0 }; 1162 1163 wdata.qw = (uint8_t)data; 1164 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1165 } 1166 1167 static void 1168 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1169 { 1170 pci_cfg_data_t wdata = { 0 }; 1171 1172 wdata.qw = (uint16_t)data; 1173 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1174 } 1175 1176 static void 1177 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1178 { 1179 pci_cfg_data_t wdata = { 0 }; 1180 1181 wdata.qw = (uint32_t)data; 1182 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1183 } 1184 1185 static void 1186 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1187 { 1188 pci_cfg_data_t wdata = { 0 }; 1189 1190 wdata.qw = (uint32_t)(data & 0xffffffff); 1191 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1192 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1193 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1194 } 1195 1196 static void 1197 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1198 uint8_t *dev_addr, size_t repcount, uint_t flags) 1199 { 1200 if (flags == DDI_DEV_AUTOINCR) 1201 for (; repcount; repcount--) 1202 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1203 else 1204 for (; repcount; repcount--) 1205 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1206 } 1207 1208 /* 1209 * Function to rep read 16 bit data off the PCI configuration space behind 1210 * the 21554's host interface. 1211 */ 1212 static void 1213 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1214 uint16_t *dev_addr, size_t repcount, uint_t flags) 1215 { 1216 if (flags == DDI_DEV_AUTOINCR) 1217 for (; repcount; repcount--) 1218 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1219 else 1220 for (; repcount; repcount--) 1221 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1222 } 1223 1224 /* 1225 * Function to rep read 32 bit data off the PCI configuration space behind 1226 * the 21554's host interface. 1227 */ 1228 static void 1229 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1230 uint32_t *dev_addr, size_t repcount, uint_t flags) 1231 { 1232 if (flags == DDI_DEV_AUTOINCR) 1233 for (; repcount; repcount--) 1234 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1235 else 1236 for (; repcount; repcount--) 1237 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1238 } 1239 1240 /* 1241 * Function to rep read 64 bit data off the PCI configuration space behind 1242 * the 21554's host interface. 1243 */ 1244 static void 1245 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1246 uint64_t *dev_addr, size_t repcount, uint_t flags) 1247 { 1248 if (flags == DDI_DEV_AUTOINCR) 1249 for (; repcount; repcount--) 1250 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1251 else 1252 for (; repcount; repcount--) 1253 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1254 } 1255 1256 /* 1257 * Function to rep write 8 bit data into the PCI configuration space behind 1258 * the 21554's host interface. 1259 */ 1260 static void 1261 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1262 uint8_t *dev_addr, size_t repcount, uint_t flags) 1263 { 1264 if (flags == DDI_DEV_AUTOINCR) 1265 for (; repcount; repcount--) 1266 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1267 else 1268 for (; repcount; repcount--) 1269 px_pci_config_put8(handle, dev_addr, *host_addr++); 1270 } 1271 1272 /* 1273 * Function to rep write 16 bit data into the PCI configuration space behind 1274 * the 21554's host interface. 1275 */ 1276 static void 1277 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1278 uint16_t *dev_addr, size_t repcount, uint_t flags) 1279 { 1280 if (flags == DDI_DEV_AUTOINCR) 1281 for (; repcount; repcount--) 1282 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1283 else 1284 for (; repcount; repcount--) 1285 px_pci_config_put16(handle, dev_addr, *host_addr++); 1286 } 1287 1288 /* 1289 * Function to rep write 32 bit data into the PCI configuration space behind 1290 * the 21554's host interface. 1291 */ 1292 static void 1293 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1294 uint32_t *dev_addr, size_t repcount, uint_t flags) 1295 { 1296 if (flags == DDI_DEV_AUTOINCR) 1297 for (; repcount; repcount--) 1298 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1299 else 1300 for (; repcount; repcount--) 1301 px_pci_config_put32(handle, dev_addr, *host_addr++); 1302 } 1303 1304 /* 1305 * Function to rep write 64 bit data into the PCI configuration space behind 1306 * the 21554's host interface. 1307 */ 1308 static void 1309 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1310 uint64_t *dev_addr, size_t repcount, uint_t flags) 1311 { 1312 if (flags == DDI_DEV_AUTOINCR) 1313 for (; repcount; repcount--) 1314 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1315 else 1316 for (; repcount; repcount--) 1317 px_pci_config_put64(handle, dev_addr, *host_addr++); 1318 } 1319 1320 /* 1321 * Provide a private access handle to route config access calls to Hypervisor. 1322 * Beware: Do all error checking for config space accesses before calling 1323 * this function. ie. do error checking from the calling function. 1324 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1325 * DDI_SUCCESS from here makes the code organization readable/easier from 1326 * the generic code. 1327 */ 1328 /*ARGSUSED*/ 1329 int 1330 px_lib_map_vconfig(dev_info_t *dip, 1331 ddi_map_req_t *mp, pci_config_offset_t off, 1332 pci_regspec_t *rp, caddr_t *addrp) 1333 { 1334 ddi_acc_hdl_t *hp; 1335 ddi_acc_impl_t *ap; 1336 uchar_t busnum; /* bus number */ 1337 uchar_t devnum; /* device number */ 1338 uchar_t funcnum; /* function number */ 1339 px_config_acc_pvt_t *px_pvt; 1340 1341 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1342 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1343 1344 /* Check for mapping teardown operation */ 1345 if ((mp->map_op == DDI_MO_UNMAP) || 1346 (mp->map_op == DDI_MO_UNLOCK)) { 1347 /* free up memory allocated for the private access handle. */ 1348 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1349 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1350 1351 /* unmap operation of PCI IO/config space. */ 1352 return (DDI_SUCCESS); 1353 } 1354 1355 ap->ahi_get8 = px_pci_config_get8; 1356 ap->ahi_get16 = px_pci_config_get16; 1357 ap->ahi_get32 = px_pci_config_get32; 1358 ap->ahi_get64 = px_pci_config_get64; 1359 ap->ahi_put8 = px_pci_config_put8; 1360 ap->ahi_put16 = px_pci_config_put16; 1361 ap->ahi_put32 = px_pci_config_put32; 1362 ap->ahi_put64 = px_pci_config_put64; 1363 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1364 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1365 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1366 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1367 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1368 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1369 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1370 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1371 1372 /* Initialize to default check/notify functions */ 1373 ap->ahi_fault = 0; 1374 ap->ahi_fault_check = i_ddi_acc_fault_check; 1375 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1376 1377 /* allocate memory for our private handle */ 1378 px_pvt = (px_config_acc_pvt_t *) 1379 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1380 hp->ah_bus_private = (void *)px_pvt; 1381 1382 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1383 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1384 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1385 1386 /* set up private data for use during IO routines */ 1387 1388 /* addr needed by the HV APIs */ 1389 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1390 /* 1391 * Address that specifies the actual offset into the 256MB 1392 * memory mapped configuration space, 4K per device. 1393 * First 12bits form the offset into 4K config space. 1394 * This address is only used during the IO routines to calculate 1395 * the offset at which the transaction must be performed. 1396 * Drivers bypassing DDI functions to access PCI config space will 1397 * panic the system since the following is a bogus virtual address. 1398 */ 1399 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1400 px_pvt->dip = dip; 1401 1402 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1403 px_pvt->raddr, px_pvt->vaddr); 1404 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1405 return (DDI_SUCCESS); 1406 } 1407 1408 /*ARGSUSED*/ 1409 void 1410 px_lib_map_attr_check(ddi_map_req_t *mp) 1411 { 1412 } 1413 1414 /* 1415 * px_lib_log_safeacc_err: 1416 * Imitate a cpu/mem trap call when a peek/poke fails. 1417 * This will initiate something similar to px_fm_callback. 1418 */ 1419 static void 1420 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1421 { 1422 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1423 ddi_fm_error_t derr; 1424 1425 derr.fme_status = DDI_FM_NONFATAL; 1426 derr.fme_version = DDI_FME_VERSION; 1427 derr.fme_flag = fme_flag; 1428 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1429 derr.fme_acc_handle = handle; 1430 if (hp) 1431 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1432 1433 mutex_enter(&px_p->px_fm_mutex); 1434 1435 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1436 1437 mutex_exit(&px_p->px_fm_mutex); 1438 } 1439 1440 1441 #ifdef DEBUG 1442 int px_peekfault_cnt = 0; 1443 int px_pokefault_cnt = 0; 1444 #endif /* DEBUG */ 1445 1446 static int 1447 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1448 { 1449 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1450 pci_regspec_t regspec_array[8]; 1451 pci_regspec_t *regspec = regspec_array; 1452 int buflen = sizeof (regspec_array); 1453 boolean_t kmalloced = B_FALSE; 1454 int status; 1455 1456 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1457 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1458 1459 /* If need more space, fallback to kmem_alloc. */ 1460 if (status == DDI_PROP_BUF_TOO_SMALL) { 1461 regspec = kmem_alloc(buflen, KM_SLEEP); 1462 1463 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1464 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1465 1466 kmalloced = B_TRUE; 1467 } 1468 1469 /* Get phys_hi from first element. All have same bdf. */ 1470 if (status == DDI_PROP_SUCCESS) 1471 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1472 1473 if (kmalloced) 1474 kmem_free(regspec, buflen); 1475 1476 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1477 } 1478 1479 /* 1480 * Do a safe write to a device. 1481 * 1482 * When this function is given a handle (cautious access), all errors are 1483 * suppressed. 1484 * 1485 * When this function is not given a handle (poke), only Unsupported Request 1486 * and Completer Abort errors are suppressed. 1487 * 1488 * In all cases, all errors are returned in the function return status. 1489 */ 1490 1491 int 1492 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1493 peekpoke_ctlops_t *in_args) 1494 { 1495 px_t *px_p = DIP_TO_STATE(dip); 1496 px_pec_t *pec_p = px_p->px_pec_p; 1497 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1498 1499 size_t repcount = in_args->repcount; 1500 size_t size = in_args->size; 1501 uintptr_t dev_addr = in_args->dev_addr; 1502 uintptr_t host_addr = in_args->host_addr; 1503 1504 int err = DDI_SUCCESS; 1505 uint64_t hvio_poke_status; 1506 uint32_t bdf; 1507 uint32_t wrt_stat; 1508 1509 r_addr_t ra; 1510 uint64_t pokeval; 1511 1512 /* 1513 * Used only to notify error handling peek/poke is occuring 1514 * One scenario is when a fabric err as a result of peek/poke. 1515 * However there is no way to guarantee that the fabric error 1516 * handler will occur in the window where otd is set. 1517 */ 1518 on_trap_data_t otd; 1519 1520 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1521 DBG(DBG_LIB_DMA, px_p->px_dip, 1522 "poke: px_lib_bdf_from_dip failed\n"); 1523 err = DDI_FAILURE; 1524 goto done; 1525 } 1526 1527 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1528 for (; repcount; repcount--) { 1529 1530 switch (size) { 1531 case sizeof (uint8_t): 1532 pokeval = *(uint8_t *)host_addr; 1533 break; 1534 case sizeof (uint16_t): 1535 pokeval = *(uint16_t *)host_addr; 1536 break; 1537 case sizeof (uint32_t): 1538 pokeval = *(uint32_t *)host_addr; 1539 break; 1540 case sizeof (uint64_t): 1541 pokeval = *(uint64_t *)host_addr; 1542 break; 1543 default: 1544 DBG(DBG_MAP, px_p->px_dip, 1545 "poke: invalid size %d passed\n", size); 1546 err = DDI_FAILURE; 1547 goto done; 1548 } 1549 1550 /* 1551 * Grab pokefault mutex since hypervisor does not guarantee 1552 * poke serialization. 1553 */ 1554 if (hp) { 1555 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1556 (ddi_acc_handle_t)hp); 1557 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1558 } else { 1559 mutex_enter(&pec_p->pec_pokefault_mutex); 1560 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1561 } 1562 pec_p->pec_ontrap_data = &otd; 1563 1564 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1565 pokeval, bdf, &wrt_stat); 1566 1567 if (otd.ot_trap & OT_DATA_ACCESS) 1568 err = DDI_FAILURE; 1569 1570 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1571 err = DDI_FAILURE; 1572 #ifdef DEBUG 1573 px_pokefault_cnt++; 1574 #endif 1575 /* 1576 * For CAUTIOUS and POKE access, notify FMA to 1577 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1578 */ 1579 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1580 (hp ? DDI_FM_ERR_EXPECTED : 1581 DDI_FM_ERR_POKE)); 1582 1583 pec_p->pec_ontrap_data = NULL; 1584 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1585 if (hp) { 1586 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1587 (ddi_acc_handle_t)hp); 1588 } else { 1589 mutex_exit(&pec_p->pec_pokefault_mutex); 1590 } 1591 goto done; 1592 } 1593 1594 pec_p->pec_ontrap_data = NULL; 1595 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1596 if (hp) { 1597 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1598 (ddi_acc_handle_t)hp); 1599 } else { 1600 mutex_exit(&pec_p->pec_pokefault_mutex); 1601 } 1602 1603 host_addr += size; 1604 1605 if (in_args->flags == DDI_DEV_AUTOINCR) { 1606 dev_addr += size; 1607 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1608 } 1609 } 1610 1611 done: 1612 return (err); 1613 } 1614 1615 1616 /*ARGSUSED*/ 1617 int 1618 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1619 peekpoke_ctlops_t *in_args, void *result) 1620 { 1621 px_t *px_p = DIP_TO_STATE(dip); 1622 px_pec_t *pec_p = px_p->px_pec_p; 1623 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1624 1625 size_t repcount = in_args->repcount; 1626 uintptr_t dev_addr = in_args->dev_addr; 1627 uintptr_t host_addr = in_args->host_addr; 1628 1629 r_addr_t ra; 1630 uint32_t read_status; 1631 uint64_t hvio_peek_status; 1632 uint64_t peekval; 1633 int err = DDI_SUCCESS; 1634 1635 /* 1636 * Used only to notify error handling peek/poke is occuring 1637 * One scenario is when a fabric err as a result of peek/poke. 1638 * However there is no way to guarantee that the fabric error 1639 * handler will occur in the window where otd is set. 1640 */ 1641 on_trap_data_t otd; 1642 1643 result = (void *)in_args->host_addr; 1644 1645 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1646 for (; repcount; repcount--) { 1647 1648 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1649 if (hp) { 1650 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1651 (ddi_acc_handle_t)hp); 1652 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1653 } else { 1654 mutex_enter(&pec_p->pec_pokefault_mutex); 1655 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1656 } 1657 pec_p->pec_ontrap_data = &otd; 1658 1659 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1660 in_args->size, &read_status, &peekval); 1661 1662 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1663 err = DDI_FAILURE; 1664 1665 /* 1666 * For CAUTIOUS and PEEK access, notify FMA to 1667 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1668 */ 1669 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1670 (hp ? DDI_FM_ERR_EXPECTED : 1671 DDI_FM_ERR_PEEK)); 1672 1673 /* Stuff FFs in host addr if peek. */ 1674 if (hp == NULL) { 1675 int i; 1676 uint8_t *ff_addr = (uint8_t *)host_addr; 1677 for (i = 0; i < in_args->size; i++) 1678 *ff_addr++ = 0xff; 1679 } 1680 #ifdef DEBUG 1681 px_peekfault_cnt++; 1682 #endif 1683 pec_p->pec_ontrap_data = NULL; 1684 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1685 if (hp) { 1686 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1687 (ddi_acc_handle_t)hp); 1688 } else { 1689 mutex_exit(&pec_p->pec_pokefault_mutex); 1690 } 1691 goto done; 1692 1693 } 1694 pec_p->pec_ontrap_data = NULL; 1695 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1696 if (hp) { 1697 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1698 (ddi_acc_handle_t)hp); 1699 } else { 1700 mutex_exit(&pec_p->pec_pokefault_mutex); 1701 } 1702 1703 switch (in_args->size) { 1704 case sizeof (uint8_t): 1705 *(uint8_t *)host_addr = (uint8_t)peekval; 1706 break; 1707 case sizeof (uint16_t): 1708 *(uint16_t *)host_addr = (uint16_t)peekval; 1709 break; 1710 case sizeof (uint32_t): 1711 *(uint32_t *)host_addr = (uint32_t)peekval; 1712 break; 1713 case sizeof (uint64_t): 1714 *(uint64_t *)host_addr = (uint64_t)peekval; 1715 break; 1716 default: 1717 DBG(DBG_MAP, px_p->px_dip, 1718 "peek: invalid size %d passed\n", 1719 in_args->size); 1720 err = DDI_FAILURE; 1721 goto done; 1722 } 1723 1724 host_addr += in_args->size; 1725 1726 if (in_args->flags == DDI_DEV_AUTOINCR) { 1727 dev_addr += in_args->size; 1728 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1729 } 1730 } 1731 done: 1732 return (err); 1733 } 1734 1735 1736 /* add interrupt vector */ 1737 int 1738 px_err_add_intr(px_fault_t *px_fault_p) 1739 { 1740 int ret; 1741 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1742 1743 DBG(DBG_LIB_INT, px_p->px_dip, 1744 "px_err_add_intr: calling add_ivintr"); 1745 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1746 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1747 (caddr_t)&px_fault_p->px_intr_payload[0]); 1748 1749 if (ret != DDI_SUCCESS) { 1750 DBG(DBG_LIB_INT, px_p->px_dip, 1751 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1752 1753 return (ret); 1754 } 1755 DBG(DBG_LIB_INT, px_p->px_dip, 1756 "px_err_add_intr: ib_intr_enable "); 1757 1758 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1759 1760 return (ret); 1761 } 1762 1763 /* remove interrupt vector */ 1764 void 1765 px_err_rem_intr(px_fault_t *px_fault_p) 1766 { 1767 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1768 1769 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1770 IB_INTR_WAIT); 1771 1772 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1773 } 1774 1775 int 1776 px_cb_add_intr(px_fault_t *f_p) 1777 { 1778 return (px_err_add_intr(f_p)); 1779 } 1780 1781 void 1782 px_cb_rem_intr(px_fault_t *f_p) 1783 { 1784 px_err_rem_intr(f_p); 1785 } 1786 1787 void 1788 px_cb_intr_redist(px_t *px_p) 1789 { 1790 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1791 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1792 } 1793 1794 #ifdef FMA 1795 void 1796 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1797 { 1798 px_pec_err_t *err_pkt; 1799 1800 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1801 1802 /* initialise all the structure members */ 1803 rc_status->status_valid = 0; 1804 1805 if (err_pkt->pec_descr.P) { 1806 /* PCI Status Register */ 1807 rc_status->pci_err_status = err_pkt->pci_err_status; 1808 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1809 } 1810 1811 if (err_pkt->pec_descr.E) { 1812 /* PCIe Status Register */ 1813 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1814 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1815 } 1816 1817 if (err_pkt->pec_descr.U) { 1818 rc_status->ue_status = err_pkt->ue_reg_status; 1819 rc_status->status_valid |= UE_STATUS_VALID; 1820 } 1821 1822 if (err_pkt->pec_descr.H) { 1823 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1824 rc_status->status_valid |= UE_HDR1_VALID; 1825 } 1826 1827 if (err_pkt->pec_descr.I) { 1828 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1829 rc_status->status_valid |= UE_HDR2_VALID; 1830 } 1831 1832 /* ue_fst_err_ptr - not available for sun4v?? */ 1833 1834 1835 if (err_pkt->pec_descr.S) { 1836 rc_status->source_id = err_pkt->err_src_reg; 1837 rc_status->status_valid |= SOURCE_ID_VALID; 1838 } 1839 1840 if (err_pkt->pec_descr.R) { 1841 rc_status->root_err_status = err_pkt->root_err_status; 1842 rc_status->status_valid |= CE_STATUS_VALID; 1843 } 1844 } 1845 #endif 1846 1847 /*ARGSUSED*/ 1848 int 1849 px_lib_pmctl(int cmd, px_t *px_p) 1850 { 1851 return (DDI_FAILURE); 1852 } 1853 1854 /*ARGSUSED*/ 1855 uint_t 1856 px_pmeq_intr(caddr_t arg) 1857 { 1858 return (DDI_INTR_CLAIMED); 1859 } 1860 1861 /* 1862 * Unprotected raw reads/writes of fabric device's config space. 1863 * Only used for temporary PCI-E Fabric Error Handling. 1864 */ 1865 uint32_t 1866 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1867 uint32_t data = 0; 1868 1869 (void) hvio_config_get(px_p->px_dev_hdl, 1870 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1871 (pci_cfg_data_t *)&data); 1872 1873 return (data); 1874 } 1875 1876 void 1877 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1878 uint32_t val) { 1879 pci_cfg_data_t wdata = { 0 }; 1880 1881 wdata.qw = (uint32_t)val; 1882 (void) hvio_config_put(px_p->px_dev_hdl, 1883 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1884 } 1885 1886 /*ARGSUSED*/ 1887 int 1888 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1889 { 1890 return (DDI_ENOTSUP); 1891 } 1892 1893 /*ARGSUSED*/ 1894 void 1895 px_lib_hotplug_uninit(dev_info_t *dip) 1896 { 1897 } 1898 1899 /* Dummy cpr add callback */ 1900 /*ARGSUSED*/ 1901 void 1902 px_cpr_add_callb(px_t *px_p) 1903 { 1904 } 1905 1906 /* Dummy cpr rem callback */ 1907 /*ARGSUSED*/ 1908 void 1909 px_cpr_rem_callb(px_t *px_p) 1910 { 1911 } 1912 1913 /*ARGSUSED*/ 1914 boolean_t 1915 px_lib_is_in_drain_state(px_t *px_p) 1916 { 1917 return (B_FALSE); 1918 } 1919