xref: /titanic_50/usr/src/uts/sun4v/io/px/px_lib4v.c (revision 00834081db3e33f52b17b23b6fdf351f1043e196)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 #include <sys/types.h>
30 #include <sys/sysmacros.h>
31 #include <sys/ddi.h>
32 #include <sys/async.h>
33 #include <sys/sunddi.h>
34 #include <sys/ddifm.h>
35 #include <sys/fm/protocol.h>
36 #include <sys/vmem.h>
37 #include <sys/intr.h>
38 #include <sys/ivintr.h>
39 #include <sys/errno.h>
40 #include <sys/hypervisor_api.h>
41 #include <px_obj.h>
42 #include <sys/machsystm.h>
43 #include <sys/hotplug/pci/pcihp.h>
44 #include "px_lib4v.h"
45 #include "px_err.h"
46 
47 /* mask for the ranges property in calculating the real PFN range */
48 uint_t px_ranges_phi_mask = ((1 << 28) -1);
49 
50 int
51 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl)
52 {
53 	px_nexus_regspec_t	*rp;
54 	uint_t			reglen;
55 	int			ret;
56 
57 	DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip);
58 
59 	ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
60 	    "reg", (uchar_t **)&rp, &reglen);
61 	if (ret != DDI_PROP_SUCCESS) {
62 		DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret);
63 		return (DDI_FAILURE);
64 	}
65 
66 	/*
67 	 * Initilize device handle. The device handle uniquely identifies
68 	 * a SUN4V device. It consists of the lower 28-bits of the hi-cell
69 	 * of the first entry of the SUN4V device's "reg" property as
70 	 * defined by the SUN4V Bus Binding to Open Firmware.
71 	 */
72 	*dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK);
73 
74 	ddi_prop_free(rp);
75 
76 	/*
77 	 * hotplug implementation requires this property to be associated with
78 	 * any indirect PCI config access services
79 	 */
80 	(void) ddi_prop_update_int(makedevice(ddi_driver_major(dip),
81 	    PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip,
82 	    PCI_BUS_CONF_MAP_PROP, 1);
83 
84 	DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl);
85 
86 	return (DDI_SUCCESS);
87 }
88 
89 /*ARGSUSED*/
90 int
91 px_lib_dev_fini(dev_info_t *dip)
92 {
93 	DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip);
94 
95 	(void) ddi_prop_remove(makedevice(ddi_driver_major(dip),
96 	    PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip,
97 	    PCI_BUS_CONF_MAP_PROP);
98 
99 	return (DDI_SUCCESS);
100 }
101 
102 /*ARGSUSED*/
103 int
104 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino,
105     sysino_t *sysino)
106 {
107 	uint64_t	ret;
108 
109 	DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p "
110 	    "devino 0x%x\n", dip, devino);
111 
112 	if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip),
113 	    devino, sysino)) != H_EOK) {
114 		DBG(DBG_LIB_INT, dip,
115 		    "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret);
116 		return (DDI_FAILURE);
117 	}
118 
119 	DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n",
120 	    *sysino);
121 
122 	return (DDI_SUCCESS);
123 }
124 
125 /*ARGSUSED*/
126 int
127 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino,
128     intr_valid_state_t *intr_valid_state)
129 {
130 	uint64_t	ret;
131 
132 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n",
133 	    dip, sysino);
134 
135 	if ((ret = hvio_intr_getvalid(sysino,
136 	    (int *)intr_valid_state)) != H_EOK) {
137 		DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n",
138 		    ret);
139 		return (DDI_FAILURE);
140 	}
141 
142 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n",
143 	    *intr_valid_state);
144 
145 	return (DDI_SUCCESS);
146 }
147 
148 /*ARGSUSED*/
149 int
150 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino,
151     intr_valid_state_t intr_valid_state)
152 {
153 	uint64_t	ret;
154 
155 	DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx "
156 	    "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state);
157 
158 	if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) {
159 		DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n",
160 		    ret);
161 		return (DDI_FAILURE);
162 	}
163 
164 	return (DDI_SUCCESS);
165 }
166 
167 /*ARGSUSED*/
168 int
169 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino,
170     intr_state_t *intr_state)
171 {
172 	uint64_t	ret;
173 
174 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n",
175 	    dip, sysino);
176 
177 	if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) {
178 		DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n",
179 		    ret);
180 		return (DDI_FAILURE);
181 	}
182 
183 	DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n",
184 	    *intr_state);
185 
186 	return (DDI_SUCCESS);
187 }
188 
189 /*ARGSUSED*/
190 int
191 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino,
192     intr_state_t intr_state)
193 {
194 	uint64_t	ret;
195 
196 	DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx "
197 	    "intr_state 0x%x\n", dip, sysino, intr_state);
198 
199 	if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) {
200 		DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n",
201 		    ret);
202 		return (DDI_FAILURE);
203 	}
204 
205 	return (DDI_SUCCESS);
206 }
207 
208 /*ARGSUSED*/
209 int
210 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid)
211 {
212 	uint64_t	ret;
213 
214 	DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n",
215 	    dip, sysino);
216 
217 	if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) {
218 		DBG(DBG_LIB_INT, dip,
219 		    "hvio_intr_gettarget failed, ret 0x%lx\n", ret);
220 		return (DDI_FAILURE);
221 	}
222 
223 	DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid);
224 
225 	return (DDI_SUCCESS);
226 }
227 
228 /*ARGSUSED*/
229 int
230 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid)
231 {
232 	uint64_t	ret;
233 
234 	DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx "
235 	    "cpuid 0x%x\n", dip, sysino, cpuid);
236 
237 	if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) {
238 		DBG(DBG_LIB_INT, dip,
239 		    "hvio_intr_settarget failed, ret 0x%lx\n", ret);
240 		return (DDI_FAILURE);
241 	}
242 
243 	return (DDI_SUCCESS);
244 }
245 
246 /*ARGSUSED*/
247 int
248 px_lib_intr_reset(dev_info_t *dip)
249 {
250 	px_t			*px_p = DIP_TO_STATE(dip);
251 	px_ib_t			*ib_p = px_p->px_ib_p;
252 	px_ib_ino_info_t	*ino_p;
253 
254 	DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip);
255 
256 	mutex_enter(&ib_p->ib_ino_lst_mutex);
257 
258 	/* Reset all Interrupts */
259 	for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) {
260 		if (px_lib_intr_setstate(dip, ino_p->ino_sysino,
261 		    INTR_IDLE_STATE) != DDI_SUCCESS)
262 			return (BF_FATAL);
263 	}
264 
265 	mutex_exit(&ib_p->ib_ino_lst_mutex);
266 
267 	return (BF_NONE);
268 }
269 
270 /*ARGSUSED*/
271 int
272 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages,
273     io_attributes_t io_attr, void *addr, size_t pfn_index,
274     int flag)
275 {
276 	tsbnum_t	tsb_num = PCI_TSBID_TO_TSBNUM(tsbid);
277 	tsbindex_t	tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid);
278 	io_page_list_t	*pfns, *pfn_p;
279 	pages_t		ttes_mapped = 0;
280 	int		i, err = DDI_SUCCESS;
281 
282 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx "
283 	    "pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n",
284 	    dip, tsbid, pages, io_attr, addr, pfn_index, flag);
285 
286 	if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)),
287 	    KM_NOSLEEP)) == NULL) {
288 		DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n");
289 		return (DDI_FAILURE);
290 	}
291 
292 	for (i = 0; i < pages; i++)
293 		pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flag, i));
294 
295 	while ((ttes_mapped = pfn_p - pfns) < pages) {
296 		uintptr_t	ra = va_to_pa(pfn_p);
297 		pages_t		ttes2map;
298 		uint64_t	ret;
299 
300 		ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3;
301 		ra = MMU_PTOB(MMU_BTOP(ra));
302 
303 		for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map;
304 		    ttes2map -= ttes_mapped, pfn_p += ttes_mapped) {
305 
306 			ttes_mapped = 0;
307 			if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip),
308 			    PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)),
309 			    ttes2map, io_attr, (io_page_list_t *)(ra |
310 			    ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)),
311 			    &ttes_mapped)) != H_EOK) {
312 				DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed "
313 				    "ret 0x%lx\n", ret);
314 
315 				ttes_mapped = pfn_p - pfns;
316 				err = DDI_FAILURE;
317 				goto cleanup;
318 			}
319 
320 			DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x "
321 			    "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x "
322 			    "ra 0x%p ttes_mapped 0x%x\n", tsb_num,
323 			    tsb_index + (pfn_p - pfns), ttes2map, io_attr,
324 			    ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET),
325 			    ttes_mapped);
326 		}
327 	}
328 
329 cleanup:
330 	if ((err == DDI_FAILURE) && ttes_mapped)
331 		(void) px_lib_iommu_demap(dip, tsbid, ttes_mapped);
332 
333 	kmem_free(pfns, pages * sizeof (io_page_list_t));
334 	return (err);
335 }
336 
337 /*ARGSUSED*/
338 int
339 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages)
340 {
341 	tsbnum_t	tsb_num = PCI_TSBID_TO_TSBNUM(tsbid);
342 	tsbindex_t	tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid);
343 	pages_t		ttes2demap, ttes_demapped = 0;
344 	uint64_t	ret;
345 
346 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx "
347 	    "pages 0x%x\n", dip, tsbid, pages);
348 
349 	for (ttes2demap = pages; ttes2demap;
350 	    ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) {
351 		if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip),
352 		    PCI_TSBID(tsb_num, tsb_index), ttes2demap,
353 		    &ttes_demapped)) != H_EOK) {
354 			DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, "
355 			    "ret 0x%lx\n", ret);
356 
357 			return (DDI_FAILURE);
358 		}
359 
360 		DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x "
361 		    "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n",
362 		    tsb_num, tsb_index, ttes2demap, ttes_demapped);
363 	}
364 
365 	return (DDI_SUCCESS);
366 }
367 
368 /*ARGSUSED*/
369 int
370 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid,
371     io_attributes_t *attributes_p, r_addr_t *r_addr_p)
372 {
373 	uint64_t	ret;
374 
375 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n",
376 	    dip, tsbid);
377 
378 	if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid,
379 	    attributes_p, r_addr_p)) != H_EOK) {
380 		DBG(DBG_LIB_DMA, dip,
381 		    "hvio_iommu_getmap failed, ret 0x%lx\n", ret);
382 
383 		return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE);
384 	}
385 
386 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n",
387 	    *attributes_p, *r_addr_p);
388 
389 	return (DDI_SUCCESS);
390 }
391 
392 
393 /*
394  * Checks dma attributes against system bypass ranges
395  * A sun4v device must be capable of generating the entire 64-bit
396  * address in order to perform bypass DMA.
397  */
398 /*ARGSUSED*/
399 int
400 px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p)
401 {
402 	if ((attrp->dma_attr_addr_lo != 0ull) ||
403 	    (attrp->dma_attr_addr_hi != UINT64_MAX)) {
404 
405 		return (DDI_DMA_BADATTR);
406 	}
407 
408 	*lo_p = 0ull;
409 	*hi_p = UINT64_MAX;
410 
411 	return (DDI_SUCCESS);
412 }
413 
414 
415 /*ARGSUSED*/
416 int
417 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra,
418     io_attributes_t io_attributes, io_addr_t *io_addr_p)
419 {
420 	uint64_t	ret;
421 
422 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx "
423 	    "attr 0x%x\n", dip, ra, io_attributes);
424 
425 	if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra,
426 	    io_attributes, io_addr_p)) != H_EOK) {
427 		DBG(DBG_LIB_DMA, dip,
428 		    "hvio_iommu_getbypass failed, ret 0x%lx\n", ret);
429 		return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE);
430 	}
431 
432 	DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n",
433 	    *io_addr_p);
434 
435 	return (DDI_SUCCESS);
436 }
437 
438 /*ARGSUSED*/
439 int
440 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
441 	off_t off, size_t len, uint_t cache_flags)
442 {
443 	ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
444 	uint64_t sync_dir;
445 	px_dvma_addr_t dvma_addr, pg_off;
446 	size_t num_sync;
447 	uint64_t status = H_EOK;
448 
449 	DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p "
450 	    "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n",
451 	    dip, rdip, handle, off, len, cache_flags);
452 
453 	if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) {
454 		cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.",
455 		    ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp);
456 		return (DDI_FAILURE);
457 	}
458 
459 	if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC)
460 		return (DDI_SUCCESS);
461 
462 	if (!len)
463 		len = mp->dmai_size;
464 
465 	pg_off = mp->dmai_offset;			/* start min */
466 	dvma_addr = MAX(off, pg_off);			/* lo */
467 	pg_off += mp->dmai_size;			/* end max */
468 	pg_off = MIN(off + len, pg_off);		/* hi */
469 	if (dvma_addr >= pg_off) {			/* lo >= hi ? */
470 		cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]",
471 		    ddi_driver_name(rdip), ddi_get_instance(rdip),
472 		    off, len, mp->dmai_offset,
473 		    mp->dmai_offset + mp->dmai_size);
474 		return (DDI_FAILURE);
475 	}
476 
477 	len = pg_off - dvma_addr;			/* sz = hi - lo */
478 	dvma_addr += mp->dmai_mapping;			/* start addr */
479 
480 	if (mp->dmai_rflags & DDI_DMA_READ)
481 		sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV;
482 	else
483 		sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV;
484 
485 	for (; ((len > 0) && (status == H_EOK)); len -= num_sync) {
486 		status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len,
487 		    sync_dir, &num_sync);
488 		dvma_addr += num_sync;
489 	}
490 
491 	return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE);
492 }
493 
494 
495 /*
496  * MSIQ Functions:
497  */
498 
499 /*ARGSUSED*/
500 int
501 px_lib_msiq_init(dev_info_t *dip)
502 {
503 	px_t		*px_p = DIP_TO_STATE(dip);
504 	px_msiq_state_t	*msiq_state_p = &px_p->px_ib_p->ib_msiq_state;
505 	uint64_t	*msiq_addr, ra;
506 	size_t		msiq_size;
507 	uint_t		rec_cnt;
508 	int		i, err = DDI_SUCCESS;
509 	uint64_t	ret;
510 
511 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip);
512 
513 	msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p +
514 	    (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT);
515 
516 	msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t);
517 
518 	for (i = 0; i < msiq_state_p->msiq_cnt; i++) {
519 		ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size));
520 
521 		if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip),
522 		    (i + msiq_state_p->msiq_1st_msiq_id),
523 		    ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) {
524 			DBG(DBG_LIB_MSIQ, dip,
525 			    "hvio_msiq_conf failed, ret 0x%lx\n", ret);
526 			err = DDI_FAILURE;
527 			break;
528 		}
529 
530 		if ((err = px_lib_msiq_info(dip,
531 		    (i + msiq_state_p->msiq_1st_msiq_id),
532 		    &ra, &rec_cnt)) != DDI_SUCCESS) {
533 			DBG(DBG_LIB_MSIQ, dip,
534 			    "px_lib_msiq_info failed, ret 0x%x\n", err);
535 			err = DDI_FAILURE;
536 			break;
537 		}
538 
539 		DBG(DBG_LIB_MSIQ, dip,
540 		    "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt);
541 	}
542 
543 	return (err);
544 }
545 
546 /*ARGSUSED*/
547 int
548 px_lib_msiq_fini(dev_info_t *dip)
549 {
550 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip);
551 
552 	return (DDI_SUCCESS);
553 }
554 
555 /*ARGSUSED*/
556 int
557 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p,
558     uint_t *msiq_rec_cnt_p)
559 {
560 	uint64_t	ret;
561 
562 	DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n",
563 	    dip, msiq_id);
564 
565 	if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip),
566 	    msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) {
567 		DBG(DBG_LIB_MSIQ, dip,
568 		    "hvio_msiq_info failed, ret 0x%lx\n", ret);
569 		return (DDI_FAILURE);
570 	}
571 
572 	DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n",
573 	    ra_p, *msiq_rec_cnt_p);
574 
575 	return (DDI_SUCCESS);
576 }
577 
578 /*ARGSUSED*/
579 int
580 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id,
581     pci_msiq_valid_state_t *msiq_valid_state)
582 {
583 	uint64_t	ret;
584 
585 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n",
586 	    dip, msiq_id);
587 
588 	if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip),
589 	    msiq_id, msiq_valid_state)) != H_EOK) {
590 		DBG(DBG_LIB_MSIQ, dip,
591 		    "hvio_msiq_getvalid failed, ret 0x%lx\n", ret);
592 		return (DDI_FAILURE);
593 	}
594 
595 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n",
596 	    *msiq_valid_state);
597 
598 	return (DDI_SUCCESS);
599 }
600 
601 /*ARGSUSED*/
602 int
603 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id,
604     pci_msiq_valid_state_t msiq_valid_state)
605 {
606 	uint64_t	ret;
607 
608 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x "
609 	    "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state);
610 
611 	if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip),
612 	    msiq_id, msiq_valid_state)) != H_EOK) {
613 		DBG(DBG_LIB_MSIQ, dip,
614 		    "hvio_msiq_setvalid failed, ret 0x%lx\n", ret);
615 		return (DDI_FAILURE);
616 	}
617 
618 	return (DDI_SUCCESS);
619 }
620 
621 /*ARGSUSED*/
622 int
623 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id,
624     pci_msiq_state_t *msiq_state)
625 {
626 	uint64_t	ret;
627 
628 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n",
629 	    dip, msiq_id);
630 
631 	if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip),
632 	    msiq_id, msiq_state)) != H_EOK) {
633 		DBG(DBG_LIB_MSIQ, dip,
634 		    "hvio_msiq_getstate failed, ret 0x%lx\n", ret);
635 		return (DDI_FAILURE);
636 	}
637 
638 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n",
639 	    *msiq_state);
640 
641 	return (DDI_SUCCESS);
642 }
643 
644 /*ARGSUSED*/
645 int
646 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id,
647     pci_msiq_state_t msiq_state)
648 {
649 	uint64_t	ret;
650 
651 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x "
652 	    "msiq_state 0x%x\n", dip, msiq_id, msiq_state);
653 
654 	if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip),
655 	    msiq_id, msiq_state)) != H_EOK) {
656 		DBG(DBG_LIB_MSIQ, dip,
657 		    "hvio_msiq_setstate failed, ret 0x%lx\n", ret);
658 		return (DDI_FAILURE);
659 	}
660 
661 	return (DDI_SUCCESS);
662 }
663 
664 /*ARGSUSED*/
665 int
666 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id,
667     msiqhead_t *msiq_head_p)
668 {
669 	uint64_t	ret;
670 
671 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n",
672 	    dip, msiq_id);
673 
674 	if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip),
675 	    msiq_id, msiq_head_p)) != H_EOK) {
676 		DBG(DBG_LIB_MSIQ, dip,
677 		    "hvio_msiq_gethead failed, ret 0x%lx\n", ret);
678 		return (DDI_FAILURE);
679 	}
680 
681 	*msiq_head_p =  (*msiq_head_p / sizeof (msiq_rec_t));
682 
683 	DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n",
684 	    *msiq_head_p);
685 
686 	return (DDI_SUCCESS);
687 }
688 
689 /*ARGSUSED*/
690 int
691 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id,
692     msiqhead_t msiq_head)
693 {
694 	uint64_t	ret;
695 
696 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x "
697 	    "msiq_head 0x%x\n", dip, msiq_id, msiq_head);
698 
699 	if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip),
700 	    msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) {
701 		DBG(DBG_LIB_MSIQ, dip,
702 		    "hvio_msiq_sethead failed, ret 0x%lx\n", ret);
703 		return (DDI_FAILURE);
704 	}
705 
706 	return (DDI_SUCCESS);
707 }
708 
709 /*ARGSUSED*/
710 int
711 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id,
712     msiqtail_t *msiq_tail_p)
713 {
714 	uint64_t	ret;
715 
716 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n",
717 	    dip, msiq_id);
718 
719 	if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip),
720 	    msiq_id, msiq_tail_p)) != H_EOK) {
721 		DBG(DBG_LIB_MSIQ, dip,
722 		    "hvio_msiq_gettail failed, ret 0x%lx\n", ret);
723 		return (DDI_FAILURE);
724 	}
725 
726 	*msiq_tail_p =  (*msiq_tail_p / sizeof (msiq_rec_t));
727 	DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n",
728 	    *msiq_tail_p);
729 
730 	return (DDI_SUCCESS);
731 }
732 
733 /*ARGSUSED*/
734 void
735 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p)
736 {
737 	msiq_rec_t	*curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr;
738 
739 	DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip);
740 
741 	if (!curr_msiq_rec_p->msiq_rec_type)
742 		return;
743 
744 	*msiq_rec_p = *curr_msiq_rec_p;
745 
746 	/* Zero out msiq_rec_type field */
747 	curr_msiq_rec_p->msiq_rec_type  = 0;
748 }
749 
750 /*
751  * MSI Functions:
752  */
753 
754 /*ARGSUSED*/
755 int
756 px_lib_msi_init(dev_info_t *dip)
757 {
758 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip);
759 
760 	/* Noop */
761 	return (DDI_SUCCESS);
762 }
763 
764 /*ARGSUSED*/
765 int
766 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num,
767     msiqid_t *msiq_id)
768 {
769 	uint64_t	ret;
770 
771 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n",
772 	    dip, msi_num);
773 
774 	if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip),
775 	    msi_num, msiq_id)) != H_EOK) {
776 		DBG(DBG_LIB_MSI, dip,
777 		    "hvio_msi_getmsiq failed, ret 0x%lx\n", ret);
778 		return (DDI_FAILURE);
779 	}
780 
781 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n",
782 	    *msiq_id);
783 
784 	return (DDI_SUCCESS);
785 }
786 
787 /*ARGSUSED*/
788 int
789 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num,
790     msiqid_t msiq_id, msi_type_t msitype)
791 {
792 	uint64_t	ret;
793 
794 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x "
795 	    "msq_id 0x%x\n", dip, msi_num, msiq_id);
796 
797 	if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip),
798 	    msi_num, msiq_id, msitype)) != H_EOK) {
799 		DBG(DBG_LIB_MSI, dip,
800 		    "hvio_msi_setmsiq failed, ret 0x%lx\n", ret);
801 		return (DDI_FAILURE);
802 	}
803 
804 	return (DDI_SUCCESS);
805 }
806 
807 /*ARGSUSED*/
808 int
809 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num,
810     pci_msi_valid_state_t *msi_valid_state)
811 {
812 	uint64_t	ret;
813 
814 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n",
815 	    dip, msi_num);
816 
817 	if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip),
818 	    msi_num, msi_valid_state)) != H_EOK) {
819 		DBG(DBG_LIB_MSI, dip,
820 		    "hvio_msi_getvalid failed, ret 0x%lx\n", ret);
821 		return (DDI_FAILURE);
822 	}
823 
824 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n",
825 	    *msi_valid_state);
826 
827 	return (DDI_SUCCESS);
828 }
829 
830 /*ARGSUSED*/
831 int
832 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num,
833     pci_msi_valid_state_t msi_valid_state)
834 {
835 	uint64_t	ret;
836 
837 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x "
838 	    "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state);
839 
840 	if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip),
841 	    msi_num, msi_valid_state)) != H_EOK) {
842 		DBG(DBG_LIB_MSI, dip,
843 		    "hvio_msi_setvalid failed, ret 0x%lx\n", ret);
844 		return (DDI_FAILURE);
845 	}
846 
847 	return (DDI_SUCCESS);
848 }
849 
850 /*ARGSUSED*/
851 int
852 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num,
853     pci_msi_state_t *msi_state)
854 {
855 	uint64_t	ret;
856 
857 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n",
858 	    dip, msi_num);
859 
860 	if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip),
861 	    msi_num, msi_state)) != H_EOK) {
862 		DBG(DBG_LIB_MSI, dip,
863 		    "hvio_msi_getstate failed, ret 0x%lx\n", ret);
864 		return (DDI_FAILURE);
865 	}
866 
867 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n",
868 	    *msi_state);
869 
870 	return (DDI_SUCCESS);
871 }
872 
873 /*ARGSUSED*/
874 int
875 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num,
876     pci_msi_state_t msi_state)
877 {
878 	uint64_t	ret;
879 
880 	DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x "
881 	    "msi_state 0x%x\n", dip, msi_num, msi_state);
882 
883 	if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip),
884 	    msi_num, msi_state)) != H_EOK) {
885 		DBG(DBG_LIB_MSI, dip,
886 		    "hvio_msi_setstate failed, ret 0x%lx\n", ret);
887 		return (DDI_FAILURE);
888 	}
889 
890 	return (DDI_SUCCESS);
891 }
892 
893 /*
894  * MSG Functions:
895  */
896 
897 /*ARGSUSED*/
898 int
899 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type,
900     msiqid_t *msiq_id)
901 {
902 	uint64_t	ret;
903 
904 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n",
905 	    dip, msg_type);
906 
907 	if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip),
908 	    msg_type, msiq_id)) != H_EOK) {
909 		DBG(DBG_LIB_MSG, dip,
910 		    "hvio_msg_getmsiq failed, ret 0x%lx\n", ret);
911 		return (DDI_FAILURE);
912 	}
913 
914 	DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n",
915 	    *msiq_id);
916 
917 	return (DDI_SUCCESS);
918 }
919 
920 /*ARGSUSED*/
921 int
922 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type,
923     msiqid_t msiq_id)
924 {
925 	uint64_t	ret;
926 
927 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x "
928 	    "msq_id 0x%x\n", dip, msg_type, msiq_id);
929 
930 	if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip),
931 	    msg_type, msiq_id)) != H_EOK) {
932 		DBG(DBG_LIB_MSG, dip,
933 		    "hvio_msg_setmsiq failed, ret 0x%lx\n", ret);
934 		return (DDI_FAILURE);
935 	}
936 
937 	return (DDI_SUCCESS);
938 }
939 
940 /*ARGSUSED*/
941 int
942 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type,
943     pcie_msg_valid_state_t *msg_valid_state)
944 {
945 	uint64_t	ret;
946 
947 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n",
948 	    dip, msg_type);
949 
950 	if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type,
951 	    msg_valid_state)) != H_EOK) {
952 		DBG(DBG_LIB_MSG, dip,
953 		    "hvio_msg_getvalid failed, ret 0x%lx\n", ret);
954 		return (DDI_FAILURE);
955 	}
956 
957 	DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n",
958 	    *msg_valid_state);
959 
960 	return (DDI_SUCCESS);
961 }
962 
963 /*ARGSUSED*/
964 int
965 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type,
966     pcie_msg_valid_state_t msg_valid_state)
967 {
968 	uint64_t	ret;
969 
970 	DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x "
971 	    "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state);
972 
973 	if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type,
974 	    msg_valid_state)) != H_EOK) {
975 		DBG(DBG_LIB_MSG, dip,
976 		    "hvio_msg_setvalid failed, ret 0x%lx\n", ret);
977 		return (DDI_FAILURE);
978 	}
979 
980 	return (DDI_SUCCESS);
981 }
982 
983 /*
984  * Suspend/Resume Functions:
985  * Currently unsupported by hypervisor and all functions are noops.
986  */
987 /*ARGSUSED*/
988 int
989 px_lib_suspend(dev_info_t *dip)
990 {
991 	DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n");
992 
993 	/* Not supported */
994 	return (DDI_FAILURE);
995 }
996 
997 /*ARGSUSED*/
998 void
999 px_lib_resume(dev_info_t *dip)
1000 {
1001 	DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n");
1002 
1003 	/* Noop */
1004 }
1005 
1006 /*
1007  * Misc Functions:
1008  * Currently unsupported by hypervisor and all functions are noops.
1009  */
1010 /*ARGSUSED*/
1011 uint64_t
1012 px_lib_get_cb(dev_info_t *dip)
1013 {
1014 	return (DDI_SUCCESS);
1015 }
1016 
1017 /*ARGSUSED*/
1018 void
1019 px_lib_set_cb(dev_info_t *dip, uint64_t val)
1020 {
1021 	/* Noop */
1022 }
1023 
1024 /*ARGSUSED*/
1025 static int
1026 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off,
1027     uint8_t size, pci_cfg_data_t *data_p)
1028 {
1029 	uint64_t	ret;
1030 
1031 	DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx "
1032 	    "off 0x%x size 0x%x\n", dip, bdf, off, size);
1033 
1034 	if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off,
1035 	    size, data_p)) != H_EOK) {
1036 		DBG(DBG_LIB_CFG, dip,
1037 		    "hvio_config_get failed, ret 0x%lx\n", ret);
1038 		return (DDI_FAILURE);
1039 	}
1040 	DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw);
1041 
1042 	return (DDI_SUCCESS);
1043 }
1044 
1045 /*ARGSUSED*/
1046 static int
1047 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off,
1048     uint8_t size, pci_cfg_data_t data)
1049 {
1050 	uint64_t	ret;
1051 
1052 	DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx "
1053 	    "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw);
1054 
1055 	if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off,
1056 	    size, data)) != H_EOK) {
1057 		DBG(DBG_LIB_CFG, dip,
1058 		    "hvio_config_put failed, ret 0x%lx\n", ret);
1059 		return (DDI_FAILURE);
1060 	}
1061 
1062 	return (DDI_SUCCESS);
1063 }
1064 
1065 static uint32_t
1066 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size)
1067 {
1068 	px_config_acc_pvt_t	*px_pvt = (px_config_acc_pvt_t *)
1069 					handle->ahi_common.ah_bus_private;
1070 	uint32_t pci_dev_addr = px_pvt->raddr;
1071 	uint32_t vaddr = px_pvt->vaddr;
1072 	uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff;
1073 	uint32_t rdata = 0;
1074 
1075 	if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off,
1076 				size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS)
1077 		/* XXX update error kstats */
1078 		return (0xffffffff);
1079 	return (rdata);
1080 }
1081 
1082 static void
1083 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr,
1084 		int size, pci_cfg_data_t wdata)
1085 {
1086 	px_config_acc_pvt_t	*px_pvt = (px_config_acc_pvt_t *)
1087 					handle->ahi_common.ah_bus_private;
1088 	uint32_t pci_dev_addr = px_pvt->raddr;
1089 	uint32_t vaddr = px_pvt->vaddr;
1090 	uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff;
1091 
1092 	if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off,
1093 				size, wdata) != DDI_SUCCESS) {
1094 		/*EMPTY*/
1095 		/* XXX update error kstats */
1096 	}
1097 }
1098 
1099 static uint8_t
1100 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr)
1101 {
1102 	return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1));
1103 }
1104 
1105 static uint16_t
1106 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr)
1107 {
1108 	return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2));
1109 }
1110 
1111 static uint32_t
1112 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr)
1113 {
1114 	return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4));
1115 }
1116 
1117 static uint64_t
1118 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr)
1119 {
1120 	uint32_t rdatah, rdatal;
1121 
1122 	rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4);
1123 	rdatah = (uint32_t)px_pci_config_get(handle,
1124 				(uint32_t *)((char *)addr+4), 4);
1125 	return (((uint64_t)rdatah << 32) | rdatal);
1126 }
1127 
1128 static void
1129 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data)
1130 {
1131 	pci_cfg_data_t wdata = { 0 };
1132 
1133 	wdata.qw = (uint8_t)data;
1134 	px_pci_config_put(handle, (uint32_t *)addr, 1, wdata);
1135 }
1136 
1137 static void
1138 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data)
1139 {
1140 	pci_cfg_data_t wdata = { 0 };
1141 
1142 	wdata.qw = (uint16_t)data;
1143 	px_pci_config_put(handle, (uint32_t *)addr, 2, wdata);
1144 }
1145 
1146 static void
1147 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data)
1148 {
1149 	pci_cfg_data_t wdata = { 0 };
1150 
1151 	wdata.qw = (uint32_t)data;
1152 	px_pci_config_put(handle, (uint32_t *)addr, 4, wdata);
1153 }
1154 
1155 static void
1156 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data)
1157 {
1158 	pci_cfg_data_t wdata = { 0 };
1159 
1160 	wdata.qw = (uint32_t)(data & 0xffffffff);
1161 	px_pci_config_put(handle, (uint32_t *)addr, 4, wdata);
1162 	wdata.qw = (uint32_t)((data >> 32) & 0xffffffff);
1163 	px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata);
1164 }
1165 
1166 static void
1167 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr,
1168 			uint8_t *dev_addr, size_t repcount, uint_t flags)
1169 {
1170 	if (flags == DDI_DEV_AUTOINCR)
1171 		for (; repcount; repcount--)
1172 			*host_addr++ = px_pci_config_get8(handle, dev_addr++);
1173 	else
1174 		for (; repcount; repcount--)
1175 			*host_addr++ = px_pci_config_get8(handle, dev_addr);
1176 }
1177 
1178 /*
1179  * Function to rep read 16 bit data off the PCI configuration space behind
1180  * the 21554's host interface.
1181  */
1182 static void
1183 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr,
1184 			uint16_t *dev_addr, size_t repcount, uint_t flags)
1185 {
1186 	if (flags == DDI_DEV_AUTOINCR)
1187 		for (; repcount; repcount--)
1188 			*host_addr++ = px_pci_config_get16(handle, dev_addr++);
1189 	else
1190 		for (; repcount; repcount--)
1191 			*host_addr++ = px_pci_config_get16(handle, dev_addr);
1192 }
1193 
1194 /*
1195  * Function to rep read 32 bit data off the PCI configuration space behind
1196  * the 21554's host interface.
1197  */
1198 static void
1199 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr,
1200 			uint32_t *dev_addr, size_t repcount, uint_t flags)
1201 {
1202 	if (flags == DDI_DEV_AUTOINCR)
1203 		for (; repcount; repcount--)
1204 			*host_addr++ = px_pci_config_get32(handle, dev_addr++);
1205 	else
1206 		for (; repcount; repcount--)
1207 			*host_addr++ = px_pci_config_get32(handle, dev_addr);
1208 }
1209 
1210 /*
1211  * Function to rep read 64 bit data off the PCI configuration space behind
1212  * the 21554's host interface.
1213  */
1214 static void
1215 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr,
1216 			uint64_t *dev_addr, size_t repcount, uint_t flags)
1217 {
1218 	if (flags == DDI_DEV_AUTOINCR)
1219 		for (; repcount; repcount--)
1220 			*host_addr++ = px_pci_config_get64(handle, dev_addr++);
1221 	else
1222 		for (; repcount; repcount--)
1223 			*host_addr++ = px_pci_config_get64(handle, dev_addr);
1224 }
1225 
1226 /*
1227  * Function to rep write 8 bit data into the PCI configuration space behind
1228  * the 21554's host interface.
1229  */
1230 static void
1231 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr,
1232 			uint8_t *dev_addr, size_t repcount, uint_t flags)
1233 {
1234 	if (flags == DDI_DEV_AUTOINCR)
1235 		for (; repcount; repcount--)
1236 			px_pci_config_put8(handle, dev_addr++, *host_addr++);
1237 	else
1238 		for (; repcount; repcount--)
1239 			px_pci_config_put8(handle, dev_addr, *host_addr++);
1240 }
1241 
1242 /*
1243  * Function to rep write 16 bit data into the PCI configuration space behind
1244  * the 21554's host interface.
1245  */
1246 static void
1247 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr,
1248 			uint16_t *dev_addr, size_t repcount, uint_t flags)
1249 {
1250 	if (flags == DDI_DEV_AUTOINCR)
1251 		for (; repcount; repcount--)
1252 			px_pci_config_put16(handle, dev_addr++, *host_addr++);
1253 	else
1254 		for (; repcount; repcount--)
1255 			px_pci_config_put16(handle, dev_addr, *host_addr++);
1256 }
1257 
1258 /*
1259  * Function to rep write 32 bit data into the PCI configuration space behind
1260  * the 21554's host interface.
1261  */
1262 static void
1263 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr,
1264 			uint32_t *dev_addr, size_t repcount, uint_t flags)
1265 {
1266 	if (flags == DDI_DEV_AUTOINCR)
1267 		for (; repcount; repcount--)
1268 			px_pci_config_put32(handle, dev_addr++, *host_addr++);
1269 	else
1270 		for (; repcount; repcount--)
1271 			px_pci_config_put32(handle, dev_addr, *host_addr++);
1272 }
1273 
1274 /*
1275  * Function to rep write 64 bit data into the PCI configuration space behind
1276  * the 21554's host interface.
1277  */
1278 static void
1279 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr,
1280 			uint64_t *dev_addr, size_t repcount, uint_t flags)
1281 {
1282 	if (flags == DDI_DEV_AUTOINCR)
1283 		for (; repcount; repcount--)
1284 			px_pci_config_put64(handle, dev_addr++, *host_addr++);
1285 	else
1286 		for (; repcount; repcount--)
1287 			px_pci_config_put64(handle, dev_addr, *host_addr++);
1288 }
1289 
1290 /*
1291  * Provide a private access handle to route config access calls to Hypervisor.
1292  * Beware: Do all error checking for config space accesses before calling
1293  * this function. ie. do error checking from the calling function.
1294  * Due to a lack of meaningful error code in DDI, the gauranteed return of
1295  * DDI_SUCCESS from here makes the code organization readable/easier from
1296  * the generic code.
1297  */
1298 /*ARGSUSED*/
1299 int
1300 px_lib_map_vconfig(dev_info_t *dip,
1301 	ddi_map_req_t *mp, pci_config_offset_t off,
1302 	pci_regspec_t *rp, caddr_t *addrp)
1303 {
1304 	ddi_acc_hdl_t *hp;
1305 	ddi_acc_impl_t *ap;
1306 	uchar_t busnum;	/* bus number */
1307 	uchar_t devnum;	/* device number */
1308 	uchar_t funcnum; /* function number */
1309 	px_config_acc_pvt_t *px_pvt;
1310 
1311 	hp = (ddi_acc_hdl_t *)mp->map_handlep;
1312 	ap = (ddi_acc_impl_t *)hp->ah_platform_private;
1313 
1314 	/* Check for mapping teardown operation */
1315 	if ((mp->map_op == DDI_MO_UNMAP) ||
1316 			(mp->map_op == DDI_MO_UNLOCK)) {
1317 		/* free up memory allocated for the private access handle. */
1318 		px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private;
1319 		kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t));
1320 
1321 		/* unmap operation of PCI IO/config space. */
1322 		return (DDI_SUCCESS);
1323 	}
1324 
1325 	ap->ahi_get8 = px_pci_config_get8;
1326 	ap->ahi_get16 = px_pci_config_get16;
1327 	ap->ahi_get32 = px_pci_config_get32;
1328 	ap->ahi_get64 = px_pci_config_get64;
1329 	ap->ahi_put8 = px_pci_config_put8;
1330 	ap->ahi_put16 = px_pci_config_put16;
1331 	ap->ahi_put32 = px_pci_config_put32;
1332 	ap->ahi_put64 = px_pci_config_put64;
1333 	ap->ahi_rep_get8 = px_pci_config_rep_get8;
1334 	ap->ahi_rep_get16 = px_pci_config_rep_get16;
1335 	ap->ahi_rep_get32 = px_pci_config_rep_get32;
1336 	ap->ahi_rep_get64 = px_pci_config_rep_get64;
1337 	ap->ahi_rep_put8 = px_pci_config_rep_put8;
1338 	ap->ahi_rep_put16 = px_pci_config_rep_put16;
1339 	ap->ahi_rep_put32 = px_pci_config_rep_put32;
1340 	ap->ahi_rep_put64 = px_pci_config_rep_put64;
1341 
1342 	/* Initialize to default check/notify functions */
1343 	ap->ahi_fault = 0;
1344 	ap->ahi_fault_check = i_ddi_acc_fault_check;
1345 	ap->ahi_fault_notify = i_ddi_acc_fault_notify;
1346 
1347 	/* allocate memory for our private handle */
1348 	px_pvt = (px_config_acc_pvt_t *)
1349 			kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP);
1350 	hp->ah_bus_private = (void *)px_pvt;
1351 
1352 	busnum = PCI_REG_BUS_G(rp->pci_phys_hi);
1353 	devnum = PCI_REG_DEV_G(rp->pci_phys_hi);
1354 	funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi);
1355 
1356 	/* set up private data for use during IO routines */
1357 
1358 	/* addr needed by the HV APIs */
1359 	px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8;
1360 	/*
1361 	 * Address that specifies the actual offset into the 256MB
1362 	 * memory mapped configuration space, 4K per device.
1363 	 * First 12bits form the offset into 4K config space.
1364 	 * This address is only used during the IO routines to calculate
1365 	 * the offset at which the transaction must be performed.
1366 	 * Drivers bypassing DDI functions to access PCI config space will
1367 	 * panic the system since the following is a bogus virtual address.
1368 	 */
1369 	px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off;
1370 	px_pvt->dip = dip;
1371 
1372 	DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n",
1373 				px_pvt->raddr, px_pvt->vaddr);
1374 	*addrp = (caddr_t)(uintptr_t)px_pvt->vaddr;
1375 	return (DDI_SUCCESS);
1376 }
1377 
1378 /*ARGSUSED*/
1379 void
1380 px_lib_map_attr_check(ddi_map_req_t *mp)
1381 {
1382 }
1383 
1384 /*
1385  * px_lib_log_safeacc_err:
1386  * Imitate a cpu/mem trap call when a peek/poke fails.
1387  * This will initiate something similar to px_fm_callback.
1388  */
1389 static void
1390 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag)
1391 {
1392 	ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle;
1393 	px_cb_t	*cb_p = px_p->px_cb_p;
1394 	ddi_fm_error_t derr;
1395 
1396 	derr.fme_status = DDI_FM_NONFATAL;
1397 	derr.fme_version = DDI_FME_VERSION;
1398 	derr.fme_flag = fme_flag;
1399 	derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1);
1400 	derr.fme_acc_handle = handle;
1401 	if (hp)
1402 		hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED;
1403 
1404 	mutex_enter(&cb_p->xbc_fm_mutex);
1405 
1406 	(void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr);
1407 
1408 	mutex_exit(&cb_p->xbc_fm_mutex);
1409 }
1410 
1411 
1412 #ifdef  DEBUG
1413 int	px_peekfault_cnt = 0;
1414 int	px_pokefault_cnt = 0;
1415 #endif  /* DEBUG */
1416 
1417 static int
1418 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf)
1419 {
1420 	/* Start with an array of 8 reg spaces for now to cover most devices. */
1421 	pci_regspec_t regspec_array[8];
1422 	pci_regspec_t *regspec = regspec_array;
1423 	int buflen = sizeof (regspec_array);
1424 	boolean_t kmalloced = B_FALSE;
1425 	int status;
1426 
1427 	status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip,
1428 	    DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen);
1429 
1430 	/* If need more space, fallback to kmem_alloc. */
1431 	if (status == DDI_PROP_BUF_TOO_SMALL) {
1432 		regspec = kmem_alloc(buflen, KM_SLEEP);
1433 
1434 		status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip,
1435 		    DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen);
1436 
1437 		kmalloced = B_TRUE;
1438 	}
1439 
1440 	/* Get phys_hi from first element.  All have same bdf. */
1441 	if (status == DDI_PROP_SUCCESS)
1442 		*bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M);
1443 
1444 	if (kmalloced)
1445 		kmem_free(regspec, buflen);
1446 
1447 	return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
1448 }
1449 
1450 /*
1451  * Do a safe write to a device.
1452  *
1453  * When this function is given a handle (cautious access), all errors are
1454  * suppressed.
1455  *
1456  * When this function is not given a handle (poke), only Unsupported Request
1457  * and Completer Abort errors are suppressed.
1458  *
1459  * In all cases, all errors are returned in the function return status.
1460  */
1461 
1462 int
1463 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip,
1464     peekpoke_ctlops_t *in_args)
1465 {
1466 	px_t *px_p = DIP_TO_STATE(dip);
1467 	px_pec_t *pec_p = px_p->px_pec_p;
1468 	ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle;
1469 
1470 	size_t repcount = in_args->repcount;
1471 	size_t size = in_args->size;
1472 	uintptr_t dev_addr = in_args->dev_addr;
1473 	uintptr_t host_addr = in_args->host_addr;
1474 
1475 	int err	= DDI_SUCCESS;
1476 	uint64_t hvio_poke_status;
1477 	uint32_t bdf;
1478 	uint32_t wrt_stat;
1479 
1480 	r_addr_t ra;
1481 	uint64_t pokeval;
1482 
1483 	/*
1484 	 * Used only to notify error handling peek/poke is occuring
1485 	 * One scenario is when a fabric err as a result of peek/poke.
1486 	 * However there is no way to guarantee that the fabric error
1487 	 * handler will occur in the window where otd is set.
1488 	 */
1489 	on_trap_data_t otd;
1490 
1491 	if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) {
1492 		DBG(DBG_LIB_DMA, px_p->px_dip,
1493 		    "poke: px_lib_bdf_from_dip failed\n");
1494 		err = DDI_FAILURE;
1495 		goto done;
1496 	}
1497 
1498 	ra = (r_addr_t)va_to_pa((void *)dev_addr);
1499 	for (; repcount; repcount--) {
1500 
1501 		switch (size) {
1502 		case sizeof (uint8_t):
1503 			pokeval = *(uint8_t *)host_addr;
1504 			break;
1505 		case sizeof (uint16_t):
1506 			pokeval = *(uint16_t *)host_addr;
1507 			break;
1508 		case sizeof (uint32_t):
1509 			pokeval = *(uint32_t *)host_addr;
1510 			break;
1511 		case sizeof (uint64_t):
1512 			pokeval = *(uint64_t *)host_addr;
1513 			break;
1514 		default:
1515 			DBG(DBG_MAP, px_p->px_dip,
1516 			    "poke: invalid size %d passed\n", size);
1517 			err = DDI_FAILURE;
1518 			goto done;
1519 		}
1520 
1521 		/*
1522 		 * Grab pokefault mutex since hypervisor does not guarantee
1523 		 * poke serialization.
1524 		 */
1525 		if (hp) {
1526 			i_ndi_busop_access_enter(hp->ahi_common.ah_dip,
1527 			    (ddi_acc_handle_t)hp);
1528 			pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED;
1529 		} else {
1530 			mutex_enter(&pec_p->pec_pokefault_mutex);
1531 			pec_p->pec_safeacc_type = DDI_FM_ERR_POKE;
1532 		}
1533 		pec_p->pec_ontrap_data = &otd;
1534 
1535 		hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size,
1536 			    pokeval, bdf, &wrt_stat);
1537 
1538 		if (otd.ot_trap & OT_DATA_ACCESS)
1539 			err = DDI_FAILURE;
1540 
1541 		if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) {
1542 			err = DDI_FAILURE;
1543 #ifdef  DEBUG
1544 			px_pokefault_cnt++;
1545 #endif
1546 			/*
1547 			 * For CAUTIOUS and POKE access, notify FMA to
1548 			 * cleanup.  Imitate a cpu/mem trap call like in sun4u.
1549 			 */
1550 			px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp,
1551 			    (hp ? DDI_FM_ERR_EXPECTED :
1552 			    DDI_FM_ERR_POKE));
1553 
1554 			pec_p->pec_ontrap_data = NULL;
1555 			pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1556 			if (hp) {
1557 				i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1558 				    (ddi_acc_handle_t)hp);
1559 			} else {
1560 				mutex_exit(&pec_p->pec_pokefault_mutex);
1561 			}
1562 			goto done;
1563 		}
1564 
1565 		pec_p->pec_ontrap_data = NULL;
1566 		pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1567 		if (hp) {
1568 			i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1569 			    (ddi_acc_handle_t)hp);
1570 		} else {
1571 			mutex_exit(&pec_p->pec_pokefault_mutex);
1572 		}
1573 
1574 		host_addr += size;
1575 
1576 		if (in_args->flags == DDI_DEV_AUTOINCR) {
1577 			dev_addr += size;
1578 			ra = (r_addr_t)va_to_pa((void *)dev_addr);
1579 		}
1580 	}
1581 
1582 done:
1583 	return (err);
1584 }
1585 
1586 
1587 /*ARGSUSED*/
1588 int
1589 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip,
1590     peekpoke_ctlops_t *in_args, void *result)
1591 {
1592 	px_t *px_p = DIP_TO_STATE(dip);
1593 	px_pec_t *pec_p = px_p->px_pec_p;
1594 	ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle;
1595 
1596 	size_t repcount = in_args->repcount;
1597 	uintptr_t dev_addr = in_args->dev_addr;
1598 	uintptr_t host_addr = in_args->host_addr;
1599 
1600 	r_addr_t ra;
1601 	uint32_t read_status;
1602 	uint64_t hvio_peek_status;
1603 	uint64_t peekval;
1604 	int err = DDI_SUCCESS;
1605 
1606 	/*
1607 	 * Used only to notify error handling peek/poke is occuring
1608 	 * One scenario is when a fabric err as a result of peek/poke.
1609 	 * However there is no way to guarantee that the fabric error
1610 	 * handler will occur in the window where otd is set.
1611 	 */
1612 	on_trap_data_t otd;
1613 
1614 	result = (void *)in_args->host_addr;
1615 
1616 	ra = (r_addr_t)va_to_pa((void *)dev_addr);
1617 	for (; repcount; repcount--) {
1618 
1619 		/* Lock pokefault mutex so read doesn't mask a poke fault. */
1620 		if (hp) {
1621 			i_ndi_busop_access_enter(hp->ahi_common.ah_dip,
1622 			    (ddi_acc_handle_t)hp);
1623 			pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED;
1624 		} else {
1625 			mutex_enter(&pec_p->pec_pokefault_mutex);
1626 			pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK;
1627 		}
1628 		pec_p->pec_ontrap_data = &otd;
1629 
1630 		hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra,
1631 		    in_args->size, &read_status, &peekval);
1632 
1633 		if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) {
1634 			err = DDI_FAILURE;
1635 
1636 			/*
1637 			 * For CAUTIOUS and PEEK access, notify FMA to
1638 			 * cleanup.  Imitate a cpu/mem trap call like in sun4u.
1639 			 */
1640 			px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp,
1641 			    (hp ? DDI_FM_ERR_EXPECTED :
1642 			    DDI_FM_ERR_PEEK));
1643 
1644 			/* Stuff FFs in host addr if peek. */
1645 			if (hp == NULL) {
1646 				int i;
1647 				uint8_t *ff_addr = (uint8_t *)host_addr;
1648 				for (i = 0; i < in_args->size; i++)
1649 					*ff_addr++ = 0xff;
1650 			}
1651 #ifdef  DEBUG
1652 			px_peekfault_cnt++;
1653 #endif
1654 			pec_p->pec_ontrap_data = NULL;
1655 			pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1656 			if (hp) {
1657 				i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1658 				    (ddi_acc_handle_t)hp);
1659 			} else {
1660 				mutex_exit(&pec_p->pec_pokefault_mutex);
1661 			}
1662 			goto done;
1663 
1664 		}
1665 		pec_p->pec_ontrap_data = NULL;
1666 		pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED;
1667 		if (hp) {
1668 			i_ndi_busop_access_exit(hp->ahi_common.ah_dip,
1669 			    (ddi_acc_handle_t)hp);
1670 		} else {
1671 			mutex_exit(&pec_p->pec_pokefault_mutex);
1672 		}
1673 
1674 		switch (in_args->size) {
1675 		case sizeof (uint8_t):
1676 			*(uint8_t *)host_addr = (uint8_t)peekval;
1677 			break;
1678 		case sizeof (uint16_t):
1679 			*(uint16_t *)host_addr = (uint16_t)peekval;
1680 			break;
1681 		case sizeof (uint32_t):
1682 			*(uint32_t *)host_addr = (uint32_t)peekval;
1683 			break;
1684 		case sizeof (uint64_t):
1685 			*(uint64_t *)host_addr = (uint64_t)peekval;
1686 			break;
1687 		default:
1688 			DBG(DBG_MAP, px_p->px_dip,
1689 			    "peek: invalid size %d passed\n",
1690 			    in_args->size);
1691 			err = DDI_FAILURE;
1692 			goto done;
1693 		}
1694 
1695 		host_addr += in_args->size;
1696 
1697 		if (in_args->flags == DDI_DEV_AUTOINCR) {
1698 			dev_addr += in_args->size;
1699 			ra = (r_addr_t)va_to_pa((void *)dev_addr);
1700 		}
1701 	}
1702 done:
1703 	return (err);
1704 }
1705 
1706 
1707 /* add interrupt vector */
1708 int
1709 px_err_add_intr(px_fault_t *px_fault_p)
1710 {
1711 	int	ret;
1712 	px_t	*px_p = DIP_TO_STATE(px_fault_p->px_fh_dip);
1713 
1714 	DBG(DBG_LIB_INT, px_p->px_dip,
1715 	    "px_err_add_intr: calling add_ivintr");
1716 	ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL,
1717 	    px_fault_p->px_err_func, (caddr_t)px_fault_p,
1718 	    (caddr_t)&px_fault_p->px_intr_payload[0]);
1719 
1720 	if (ret != DDI_SUCCESS) {
1721 		DBG(DBG_LIB_INT, px_p->px_dip,
1722 		"add_ivintr returns %d, faultp: %p", ret, px_fault_p);
1723 
1724 		return (ret);
1725 	}
1726 	DBG(DBG_LIB_INT, px_p->px_dip,
1727 	    "px_err_add_intr: ib_intr_enable ");
1728 
1729 	px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino);
1730 
1731 	return (ret);
1732 }
1733 
1734 
1735 /* remove interrupt vector */
1736 void
1737 px_err_rem_intr(px_fault_t *px_fault_p)
1738 {
1739 	px_t	*px_p = DIP_TO_STATE(px_fault_p->px_fh_dip);
1740 
1741 	px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino,
1742 	    IB_INTR_WAIT);
1743 
1744 	rem_ivintr(px_fault_p->px_fh_sysino, NULL);
1745 }
1746 
1747 
1748 #ifdef FMA
1749 void
1750 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status)
1751 {
1752 	px_pec_err_t	*err_pkt;
1753 
1754 	err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload;
1755 
1756 	/* initialise all the structure members */
1757 	rc_status->status_valid = 0;
1758 
1759 	if (err_pkt->pec_descr.P) {
1760 		/* PCI Status Register */
1761 		rc_status->pci_err_status = err_pkt->pci_err_status;
1762 		rc_status->status_valid |= PCI_ERR_STATUS_VALID;
1763 	}
1764 
1765 	if (err_pkt->pec_descr.E) {
1766 		/* PCIe Status Register */
1767 		rc_status->pcie_err_status = err_pkt->pcie_err_status;
1768 		rc_status->status_valid |= PCIE_ERR_STATUS_VALID;
1769 	}
1770 
1771 	if (err_pkt->pec_descr.U) {
1772 		rc_status->ue_status = err_pkt->ue_reg_status;
1773 		rc_status->status_valid |= UE_STATUS_VALID;
1774 	}
1775 
1776 	if (err_pkt->pec_descr.H) {
1777 		rc_status->ue_hdr1 = err_pkt->hdr[0];
1778 		rc_status->status_valid |= UE_HDR1_VALID;
1779 	}
1780 
1781 	if (err_pkt->pec_descr.I) {
1782 		rc_status->ue_hdr2 = err_pkt->hdr[1];
1783 		rc_status->status_valid |= UE_HDR2_VALID;
1784 	}
1785 
1786 	/* ue_fst_err_ptr - not available for sun4v?? */
1787 
1788 
1789 	if (err_pkt->pec_descr.S) {
1790 		rc_status->source_id = err_pkt->err_src_reg;
1791 		rc_status->status_valid |= SOURCE_ID_VALID;
1792 	}
1793 
1794 	if (err_pkt->pec_descr.R) {
1795 		rc_status->root_err_status = err_pkt->root_err_status;
1796 		rc_status->status_valid |= CE_STATUS_VALID;
1797 	}
1798 }
1799 #endif
1800 
1801 /*ARGSUSED*/
1802 int
1803 px_lib_pmctl(int cmd, px_t *px_p)
1804 {
1805 	return (DDI_FAILURE);
1806 }
1807 
1808 /*ARGSUSED*/
1809 uint_t
1810 px_pmeq_intr(caddr_t arg)
1811 {
1812 	return (DDI_INTR_CLAIMED);
1813 }
1814 
1815 /*
1816  * Unprotected raw reads/writes of fabric device's config space.
1817  * Only used for temporary PCI-E Fabric Error Handling.
1818  */
1819 uint32_t
1820 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) {
1821 	uint32_t 	data = 0;
1822 
1823 	(void) hvio_config_get(px_p->px_dev_hdl,
1824 	    (bdf << PX_RA_BDF_SHIFT), offset, 4,
1825 	    (pci_cfg_data_t *)&data);
1826 
1827 	return (data);
1828 }
1829 
1830 void
1831 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset,
1832     uint32_t val) {
1833 	pci_cfg_data_t	wdata = { 0 };
1834 
1835 	wdata.qw = (uint32_t)val;
1836 	(void) hvio_config_put(px_p->px_dev_hdl,
1837 	    (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata);
1838 }
1839 
1840 /*ARGSUSED*/
1841 int
1842 px_lib_hotplug_init(dev_info_t *dip, void *arg)
1843 {
1844 	return (DDI_ENOTSUP);
1845 }
1846 
1847 /*ARGSUSED*/
1848 void
1849 px_lib_hotplug_uninit(dev_info_t *dip)
1850 {
1851 }
1852 
1853 /* Dummy cpr add callback */
1854 /*ARGSUSED*/
1855 void
1856 px_cpr_add_callb(px_t *px_p)
1857 {
1858 }
1859 
1860 /* Dummy cpr rem callback */
1861 /*ARGSUSED*/
1862 void
1863 px_cpr_rem_callb(px_t *px_p)
1864 {
1865 }
1866