1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Niagara2 Network Interface Unit (NIU) Nexus Driver 30 */ 31 32 #include <sys/conf.h> 33 #include <sys/modctl.h> 34 #include <sys/ddi_impldefs.h> 35 #include <sys/ddi_subrdefs.h> 36 #include <sys/ddi.h> 37 #include <sys/sunndi.h> 38 #include <sys/sunddi.h> 39 #include <sys/open.h> 40 #include <sys/stat.h> 41 #include <sys/file.h> 42 #include <sys/machsystm.h> 43 #include <sys/hsvc.h> 44 #include <sys/sdt.h> 45 #include <sys/hypervisor_api.h> 46 #include "niumx_var.h" 47 48 49 static int niumx_intr_ops(dev_info_t *dip, dev_info_t *rdip, 50 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 51 static int niumx_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 52 static int niumx_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 53 static int niumx_set_intr(dev_info_t *dip, dev_info_t *rdip, 54 ddi_intr_handle_impl_t *hdlp, int valid); 55 static int niumx_add_intr(dev_info_t *dip, dev_info_t *rdip, 56 ddi_intr_handle_impl_t *hdlp); 57 static int niumx_rem_intr(dev_info_t *dip, dev_info_t *rdip, 58 ddi_intr_handle_impl_t *hdlp); 59 static uint_t niumx_intr_hdlr(void *arg); 60 static int niumx_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 61 off_t offset, off_t len, caddr_t *addrp); 62 static int niumx_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 63 ddi_dma_attr_t *attrp, 64 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 65 static int niumx_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, 66 ddi_dma_handle_t handlep); 67 static int niumx_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 68 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 69 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 70 static int niumx_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 71 ddi_dma_handle_t handle); 72 static int niumx_ctlops(dev_info_t *dip, dev_info_t *rdip, 73 ddi_ctl_enum_t op, void *arg, void *result); 74 75 static struct bus_ops niumx_bus_ops = { 76 BUSO_REV, 77 niumx_map, 78 0, 79 0, 80 0, 81 i_ddi_map_fault, 82 0, 83 niumx_dma_allochdl, 84 niumx_dma_freehdl, 85 niumx_dma_bindhdl, 86 niumx_dma_unbindhdl, 87 0, 88 0, 89 0, 90 niumx_ctlops, 91 ddi_bus_prop_op, 92 0, /* (*bus_get_eventcookie)(); */ 93 0, /* (*bus_add_eventcall)(); */ 94 0, /* (*bus_remove_eventcall)(); */ 95 0, /* (*bus_post_event)(); */ 96 0, /* (*bus_intr_ctl)(); */ 97 0, /* (*bus_config)(); */ 98 0, /* (*bus_unconfig)(); */ 99 0, /* (*bus_fm_init)(); */ 100 0, /* (*bus_fm_fini)(); */ 101 0, /* (*bus_enter)() */ 102 0, /* (*bus_exit)() */ 103 0, /* (*bus_power)() */ 104 niumx_intr_ops /* (*bus_intr_op)(); */ 105 }; 106 107 static struct dev_ops niumx_ops = { 108 DEVO_REV, /* devo_rev */ 109 0, /* refcnt */ 110 ddi_no_info, /* info */ 111 nulldev, /* identify */ 112 0, /* probe */ 113 niumx_attach, /* attach */ 114 niumx_detach, /* detach */ 115 nulldev, /* reset */ 116 (struct cb_ops *)0, /* driver operations */ 117 &niumx_bus_ops, /* bus operations */ 118 0 119 }; 120 121 /* Module linkage information for the kernel. */ 122 static struct modldrv modldrv = { 123 &mod_driverops, /* Type of module */ 124 "NIU Nexus Driver %I%", 125 &niumx_ops, /* driver ops */ 126 }; 127 128 static struct modlinkage modlinkage = { 129 MODREV_1, 130 (void *)&modldrv, 131 NULL 132 }; 133 134 static void *niumx_state; 135 static niumx_ih_t niumx_ihtable[NIUMX_MAX_INTRS]; 136 137 /* 138 * forward function declarations: 139 */ 140 static void niumx_removechild(dev_info_t *); 141 static int niumx_initchild(dev_info_t *child); 142 143 int 144 _init(void) 145 { 146 int e; 147 if ((e = ddi_soft_state_init(&niumx_state, sizeof (niumx_devstate_t), 148 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 149 ddi_soft_state_fini(&niumx_state); 150 return (e); 151 } 152 153 int 154 _fini(void) 155 { 156 int e; 157 if ((e = mod_remove(&modlinkage)) == 0) 158 ddi_soft_state_fini(&niumx_state); 159 return (e); 160 } 161 162 int 163 _info(struct modinfo *modinfop) 164 { 165 return (mod_info(&modlinkage, modinfop)); 166 } 167 168 void 169 niumx_intr_dist(void *arg) 170 { 171 kmutex_t *lock_p = (kmutex_t *)arg; 172 int i = NIUMX_RSVD_INTRS; 173 niumx_ih_t *ih_p = niumx_ihtable + i; 174 175 DBG(DBG_A_INTX, NULL, "niumx_intr_dist entered\n"); 176 mutex_enter(lock_p); 177 for (; i < NIUMX_MAX_INTRS; i++, ih_p++) { 178 sysino_t sysino = ih_p->ih_sysino; 179 cpuid_t cpuid; 180 int intr_state; 181 if (!sysino || /* sequence is significant */ 182 (hvio_intr_getvalid(sysino, &intr_state) != H_EOK) || 183 (intr_state == HV_INTR_NOTVALID) || 184 (cpuid = intr_dist_cpuid()) == ih_p->ih_cpuid) 185 continue; 186 187 (void) hvio_intr_setvalid(sysino, HV_INTR_NOTVALID); 188 (void) hvio_intr_settarget(sysino, cpuid); 189 (void) hvio_intr_setvalid(sysino, HV_INTR_VALID); 190 ih_p->ih_cpuid = cpuid; 191 } 192 mutex_exit(lock_p); 193 } 194 195 /* 196 * Hypervisor INTR services information for the NIU nexus driver. 197 */ 198 static uint64_t niumx_intr_min_ver; /* Neg. API minor version */ 199 static hsvc_info_t niumx_hv_intr = { 200 HSVC_REV_1, NULL, HSVC_GROUP_INTR, NIUMX_INTR_MAJOR_VER, 201 NIUMX_INTR_MINOR_VER, "NIUMX" 202 }; 203 204 static int 205 niumx_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 206 { 207 int instance = ddi_get_instance(dip); 208 niumx_devstate_t *niumxds_p; /* devstate pointer */ 209 niu_regspec_t *reg_p; 210 uint_t reglen; 211 int ret = DDI_SUCCESS; 212 213 switch (cmd) { 214 case DDI_ATTACH: 215 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 216 DDI_PROP_DONTPASS, "reg", (int **)®_p, ®len) 217 != DDI_PROP_SUCCESS) { 218 DBG(DBG_ATTACH, dip, "reg lookup failed\n"); 219 ret = DDI_FAILURE; 220 goto done; 221 } 222 223 /* 224 * Allocate and get soft state structure. 225 */ 226 if (ddi_soft_state_zalloc(niumx_state, instance) 227 != DDI_SUCCESS) { 228 ret = DDI_FAILURE; 229 goto prop_free; 230 } 231 niumxds_p = (niumx_devstate_t *)ddi_get_soft_state(niumx_state, 232 instance); 233 niumxds_p->dip = dip; 234 mutex_init(&niumxds_p->niumx_mutex, NULL, MUTEX_DRIVER, NULL); 235 236 DBG(DBG_ATTACH, dip, "soft state alloc'd instance = %d, " 237 "niumxds_p = %p\n", instance, niumxds_p); 238 239 /* 240 * Negotiate the API version for HV INTR services. 241 */ 242 if ((ret = hsvc_register(&niumx_hv_intr, &niumx_intr_min_ver)) 243 != H_EOK) { 244 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 245 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 246 niumx_hv_intr.hsvc_modname, niumx_hv_intr.hsvc_group, 247 niumx_hv_intr.hsvc_major, niumx_hv_intr.hsvc_minor, ret); 248 ret = DDI_FAILURE; 249 goto cleanup; 250 } 251 252 DBG(DBG_ATTACH, dip, "neg. HV API major 0x%lx minor 0x%lx\n", 253 niumx_hv_intr.hsvc_major, niumx_intr_min_ver); 254 255 /* hv devhdl: low 28-bit of 1st "reg" entry's addr.hi */ 256 niumxds_p->niumx_dev_hdl = (devhandle_t)(reg_p->addr_high & 257 NIUMX_DEVHDLE_MASK); 258 259 /* add interrupt redistribution callback */ 260 intr_dist_add(niumx_intr_dist, &niumxds_p->niumx_mutex); 261 262 ret = DDI_SUCCESS; 263 goto prop_free; 264 cleanup: 265 mutex_destroy(&niumxds_p->niumx_mutex); 266 ddi_soft_state_free(niumx_state, ddi_get_instance(dip)); 267 prop_free: 268 ddi_prop_free(reg_p); 269 done: 270 return (ret); 271 272 case DDI_RESUME: 273 default: 274 break; 275 } 276 return (ret); 277 } 278 279 static int 280 niumx_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 281 { 282 niumx_devstate_t *niumxds_p; 283 284 switch (cmd) { 285 case DDI_DETACH: 286 (void) hsvc_unregister(&niumx_hv_intr); 287 288 niumxds_p = (niumx_devstate_t *) 289 ddi_get_soft_state(niumx_state, ddi_get_instance(dip)); 290 291 intr_dist_rem(niumx_intr_dist, &niumxds_p->niumx_mutex); 292 mutex_destroy(&niumxds_p->niumx_mutex); 293 ddi_soft_state_free(niumx_state, ddi_get_instance(dip)); 294 return (DDI_SUCCESS); 295 296 case DDI_SUSPEND: 297 default: 298 break; 299 } 300 return (DDI_FAILURE); 301 } 302 303 /*ARGSUSED*/ 304 int 305 niumx_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 306 off_t offset, off_t len, caddr_t *vaddrp) 307 { 308 struct regspec p_regspec; 309 ddi_map_req_t p_mapreq; 310 niu_regspec_t *reg_p; 311 int i, rn = mp->map_obj.rnumber, reglen, rnglen, rngnum, ret; 312 niumx_ranges_t *rng_p; 313 314 uint32_t reg_begin, rng_begin; 315 316 DBG(DBG_MAP, dip, "%s%d: mapping %s%d reg %d\n", NAMEINST(dip), 317 NAMEINST(rdip), rn); 318 319 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 320 "reg", (caddr_t)®_p, ®len) != DDI_SUCCESS) 321 return (DDI_FAILURE); 322 323 if (rn < 0 || (rn >= reglen / sizeof (niu_regspec_t))) { 324 DBG(DBG_MAP, dip, "rnumber out of range: %d\n", rn); 325 kmem_free(reg_p, reglen); 326 return (DDI_ME_RNUMBER_RANGE); 327 } 328 329 /* build regspec up for parent */ 330 p_mapreq = *mp; /* dup the whole structure */ 331 p_mapreq.map_type = DDI_MT_REGSPEC; 332 p_mapreq.map_obj.rp = &p_regspec; 333 334 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 335 (caddr_t)&rng_p, &rnglen) != DDI_SUCCESS) { 336 DBG(DBG_MAP, dip, "%s%d: no ranges property\n", 337 ddi_driver_name(dip), ddi_get_instance(dip)); 338 kmem_free(reg_p, reglen); 339 return (DDI_FAILURE); 340 } 341 342 /* locate matching ranges record */ 343 rngnum = rnglen / sizeof (niumx_ranges_t); 344 for (i = 0, reg_p += rn; i < rngnum; rng_p++, i++) { 345 if (reg_p->addr_high == rng_p->child_hi) 346 break; 347 } 348 349 if (i >= rngnum) { 350 DBG(DBG_MAP, dip, "ranges record for reg[%d] not found.\n", rn); 351 ret = DDI_ME_REGSPEC_RANGE; 352 goto err; 353 } 354 355 /* 356 * validate request has matching bus type and within 4G 357 * limit by comparing addr.hi of "ranges" and child "reg". 358 */ 359 360 ASSERT(reg_p->size_high == 0); 361 362 rng_begin = rng_p->child_lo; 363 reg_begin = reg_p->addr_low; 364 /* check to verify reg bounds are within rng bounds */ 365 if (reg_begin < rng_begin || (reg_begin + (reg_p->size_low - 1)) > 366 (rng_begin + (rng_p->size_lo - 1))) { 367 DBG(DBG_MAP, dip, "size out of range for reg[%d].\n", rn); 368 ret = DDI_ME_REGSPEC_RANGE; 369 goto err; 370 } 371 372 p_regspec.regspec_bustype = rng_p->parent_hi; 373 p_regspec.regspec_addr = reg_begin - rng_begin + rng_p->parent_lo; 374 p_regspec.regspec_size = reg_p->size_low; 375 DBG(DBG_MAP, dip, "regspec:bus,addr,size = (%x,%x,%x)\n", 376 p_regspec.regspec_bustype, p_regspec.regspec_addr, 377 p_regspec.regspec_size); 378 ret = ddi_map(dip, &p_mapreq, 0, 0, vaddrp); 379 DBG(DBG_MAP, dip, "niumx_map: ret %d.\n", ret); 380 err: 381 kmem_free(rng_p - i, rnglen); 382 kmem_free(reg_p - rn, reglen); 383 return (ret); 384 } 385 386 /* 387 * niumx_ctlops 388 */ 389 int 390 niumx_ctlops(dev_info_t *dip, dev_info_t *rdip, 391 ddi_ctl_enum_t ctlop, void *arg, void *result) 392 { 393 niu_regspec_t *reg_p; 394 int reglen, totreg; 395 396 DBG(DBG_CTLOPS, dip, "niumx_ctlops ctlop=%d.\n", ctlop); 397 if (rdip == (dev_info_t *)0) 398 return (DDI_FAILURE); 399 400 switch (ctlop) { 401 case DDI_CTLOPS_REPORTDEV: 402 cmn_err(CE_NOTE, "device: %s@%s, %s%d\n", 403 ddi_node_name(rdip), ddi_get_name_addr(rdip), 404 NAMEINST(rdip)); 405 return (DDI_SUCCESS); 406 407 case DDI_CTLOPS_INITCHILD: 408 return (niumx_initchild((dev_info_t *)arg)); 409 410 case DDI_CTLOPS_UNINITCHILD: 411 niumx_removechild((dev_info_t *)arg); 412 return (DDI_SUCCESS); 413 414 case DDI_CTLOPS_REGSIZE: 415 case DDI_CTLOPS_NREGS: 416 /* fall through */ 417 break; 418 default: 419 DBG(DBG_CTLOPS, dip, "just pass to ddi_cltops.\n"); 420 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 421 } 422 423 /* REGSIZE/NREGS */ 424 425 *(int *)result = 0; 426 427 if (ddi_getlongprop(DDI_DEV_T_NONE, rdip, DDI_PROP_DONTPASS | 428 DDI_PROP_CANSLEEP, "reg", (caddr_t)®_p, ®len) 429 != DDI_SUCCESS) 430 return (DDI_FAILURE); 431 432 totreg = reglen / sizeof (niu_regspec_t); 433 if (ctlop == DDI_CTLOPS_NREGS) { 434 DBG(DBG_CTLOPS, (dev_info_t *)dip, "niumx_ctlops NREGS=%d.\n", 435 totreg); 436 *(int *)result = totreg; 437 } else if (ctlop == DDI_CTLOPS_REGSIZE) { 438 int rn; 439 rn = *(int *)arg; 440 if (rn >= totreg) { 441 kmem_free(reg_p, reglen); 442 return (DDI_FAILURE); 443 } 444 *(off_t *)result = (reg_p + rn)->size_low; 445 DBG(DBG_CTLOPS, (dev_info_t *)dip, "rn = %d, REGSIZE=%x.\n", 446 rn, *(off_t *)result); 447 } 448 449 kmem_free(reg_p, reglen); 450 return (DDI_SUCCESS); 451 } 452 453 static int 454 niumx_initchild(dev_info_t *child) 455 { 456 char name[MAXNAMELEN]; 457 niu_regspec_t *r; 458 uint_t n; 459 460 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 461 "reg", (int **)&r, &n) != DDI_SUCCESS) { 462 return (DDI_FAILURE); 463 } 464 (void) snprintf(name, MAXNAMELEN, "%x", (r[0].addr_high & 465 NIUMX_FUNC_NUM_MASK)); 466 ddi_prop_free(r); 467 ddi_set_name_addr(child, name); 468 return (DDI_SUCCESS); 469 } 470 471 static void 472 niumx_removechild(dev_info_t *dip) 473 { 474 ddi_set_name_addr(dip, NULL); 475 ddi_remove_minor_node(dip, NULL); 476 impl_rem_dev_props(dip); 477 } 478 479 480 481 /* 482 * bus dma alloc handle entry point: 483 */ 484 /*ARGSUSED*/ 485 int 486 niumx_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 487 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 488 { 489 ddi_dma_impl_t *mp; 490 int sleep = (waitfp == DDI_DMA_SLEEP) ? KM_SLEEP : KM_NOSLEEP; 491 492 DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", NAMEINST(rdip)); 493 494 if (attrp->dma_attr_version != DMA_ATTR_V0) { 495 DBG(DBG_DMA_ALLOCH, (dev_info_t *)dip, "DDI_DMA_BADATTR\n"); 496 return (DDI_DMA_BADATTR); 497 } 498 499 /* Caution: we don't use zalloc to enhance performance! */ 500 if ((mp = kmem_alloc(sizeof (ddi_dma_impl_t), sleep)) == 0) { 501 DBG(DBG_DMA_ALLOCH, dip, "can't alloc ddi_dma_impl_t\n"); 502 return (DDI_FAILURE); 503 } 504 mp->dmai_rdip = rdip; 505 mp->dmai_pfnlst = NULL; 506 mp->dmai_cookie = NULL; 507 mp->dmai_fault = 0; 508 mp->dmai_fault_check = NULL; 509 mp->dmai_fault_notify = NULL; 510 511 mp->dmai_attr = *attrp; /* set requestors attr info */ 512 513 DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 514 515 *handlep = (ddi_dma_handle_t)mp; 516 return (DDI_SUCCESS); 517 } 518 519 520 /* 521 * bus dma free handle entry point: 522 */ 523 /*ARGSUSED*/ 524 int 525 niumx_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 526 { 527 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 528 529 if (mp->dmai_cookie) 530 kmem_free(mp->dmai_cookie, sizeof (ddi_dma_cookie_t)); 531 kmem_free(mp, sizeof (ddi_dma_impl_t)); 532 533 return (DDI_SUCCESS); 534 } 535 536 537 /* 538 * bus dma bind handle entry point: 539 * 540 * check/enforce DMA type, setup pfn0 and some other key pieces 541 * of this dma request. 542 * Note: this only works with DMA_OTYP_VADDR, and makes use of the known 543 * fact that only contiguous memory blocks will be passed in. 544 * Therefore only one cookie will ever be returned. 545 * 546 * return values: 547 * DDI_DMA_NOMAPPING - can't get valid pfn0, or bad dma type 548 * DDI_DMA_NORESOURCES 549 * DDI_SUCCESS 550 * 551 * dma handle members affected (set on exit): 552 * mp->dmai_object - dmareq->dmar_object 553 * mp->dmai_rflags - dmareq->dmar_flags 554 * mp->dmai_pfn0 - 1st page pfn (if va/size pair and not shadow) 555 * mp->dmai_roffset - initialized to starting page offset 556 * mp->dmai_size - # of total pages of entire object 557 * mp->dmai_cookie - new cookie alloc'd 558 */ 559 /*ARGSUSED*/ 560 int 561 niumx_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 562 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 563 ddi_dma_cookie_t *cookiep, uint_t *ccountp) 564 { 565 int (*waitfp)(caddr_t) = dmareq->dmar_fp; 566 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 567 ddi_dma_obj_t *dobj_p = &dmareq->dmar_object; 568 uint32_t offset; 569 pfn_t pfn0; 570 int ret; 571 572 DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", NAMEINST(rdip), 573 mp, dmareq); 574 575 /* first check dma type */ 576 mp->dmai_rflags = dmareq->dmar_flags & DMP_DDIFLAGS | DMP_NOSYNC; 577 switch (dobj_p->dmao_type) { 578 case DMA_OTYP_VADDR: { 579 caddr_t vaddr = dobj_p->dmao_obj.virt_obj.v_addr; 580 struct as *as_p = dobj_p->dmao_obj.virt_obj.v_as; 581 struct hat *hat_p = as_p ? as_p->a_hat : kas.a_hat; 582 offset = (ulong_t)vaddr & NIUMX_PAGE_OFFSET; 583 pfn0 = hat_getpfnum(hat_p, vaddr); 584 } 585 break; 586 587 case DMA_OTYP_BUFVADDR: 588 case DMA_OTYP_PAGES: 589 case DMA_OTYP_PADDR: 590 default: 591 cmn_err(CE_WARN, "%s%d requested unsupported dma type %x", 592 NAMEINST(mp->dmai_rdip), dobj_p->dmao_type); 593 ret = DDI_DMA_NOMAPPING; 594 goto err; 595 } 596 if (pfn0 == PFN_INVALID) { 597 cmn_err(CE_WARN, "%s%d: invalid pfn0 for DMA object %p", 598 NAMEINST(dip), (void *)dobj_p); 599 ret = DDI_DMA_NOMAPPING; 600 goto err; 601 } 602 mp->dmai_object = *dobj_p; /* whole object */ 603 mp->dmai_pfn0 = (void *)pfn0; /* cache pfn0 */ 604 mp->dmai_roffset = offset; /* pg0 offset */ 605 mp->dmai_mapping = mp->dmai_roffset | NIUMX_PTOB(pfn0); 606 mp->dmai_size = mp->dmai_object.dmao_size; 607 608 DBG(DBG_DMA_BINDH, dip, "check pfn: mp=%p pfn0=%x\n", 609 mp, mp->dmai_pfn0); 610 if (!(mp->dmai_cookie = kmem_zalloc(sizeof (ddi_dma_cookie_t), 611 waitfp == DDI_DMA_SLEEP ? KM_SLEEP : KM_NOSLEEP))) { 612 ret = DDI_DMA_NORESOURCES; 613 goto err; 614 } 615 mp->dmai_cookie->dmac_laddress = mp->dmai_mapping; 616 mp->dmai_cookie->dmac_size = mp->dmai_size; 617 *ccountp = 1; 618 *cookiep = *mp->dmai_cookie; 619 DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x, count=%d\n", 620 cookiep->dmac_address, cookiep->dmac_size, *ccountp); 621 return (DDI_DMA_MAPPED); 622 623 err: 624 DBG(DBG_DMA_BINDH, (dev_info_t *)dip, 625 "niumx_dma_bindhdl error ret=%d\n", ret); 626 return (ret); 627 } 628 629 /* 630 * bus dma unbind handle entry point: 631 */ 632 /*ARGSUSED*/ 633 int 634 niumx_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 635 { 636 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 637 638 DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 639 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 640 if (mp->dmai_cookie) { 641 kmem_free(mp->dmai_cookie, sizeof (ddi_dma_cookie_t)); 642 mp->dmai_cookie = NULL; 643 } 644 645 return (DDI_SUCCESS); 646 } 647 648 /*ARGSUSED*/ 649 int 650 niumx_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 651 ddi_intr_handle_impl_t *hdlp, void *result) 652 { 653 654 int ret = DDI_SUCCESS; 655 656 DBG(DBG_INTROPS, dip, "niumx_intr_ops: dip=%p rdip=%p intr_op=%x " 657 "handle=%p\n", dip, rdip, intr_op, hdlp); 658 659 switch (intr_op) { 660 661 case DDI_INTROP_SUPPORTED_TYPES: 662 *(int *)result = DDI_INTR_TYPE_FIXED; 663 break; 664 case DDI_INTROP_GETCAP: 665 *(int *)result = DDI_INTR_FLAG_LEVEL; 666 break; 667 case DDI_INTROP_SETCAP: 668 ret = DDI_ENOTSUP; 669 break; 670 case DDI_INTROP_ALLOC: 671 /* scratch1 = count, # of intrs from DDI framework */ 672 *(int *)result = hdlp->ih_scratch1; 673 break; 674 case DDI_INTROP_FREE: 675 /* Do we need to do anything here? */ 676 break; 677 case DDI_INTROP_GETPRI: 678 *(int *)result = NIUMX_DEFAULT_PIL; 679 break; 680 case DDI_INTROP_SETPRI: 681 ret = DDI_ENOTSUP; 682 break; 683 case DDI_INTROP_ADDISR: 684 ret = niumx_add_intr(dip, rdip, hdlp); 685 break; 686 case DDI_INTROP_REMISR: 687 ret = niumx_rem_intr(dip, rdip, hdlp); 688 break; 689 case DDI_INTROP_ENABLE: 690 ret = niumx_set_intr(dip, rdip, hdlp, HV_INTR_VALID); 691 break; 692 case DDI_INTROP_DISABLE: 693 ret = niumx_set_intr(dip, rdip, hdlp, HV_INTR_NOTVALID); 694 break; 695 case DDI_INTROP_SETMASK: 696 ret = DDI_ENOTSUP; 697 break; 698 case DDI_INTROP_CLRMASK: 699 ret = DDI_ENOTSUP; 700 break; 701 case DDI_INTROP_GETPENDING: 702 ret = DDI_ENOTSUP; 703 break; 704 case DDI_INTROP_NINTRS: 705 case DDI_INTROP_NAVAIL: { 706 devino_t *inos_p; 707 int inoslen; 708 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 709 "interrupts", (caddr_t)&inos_p, &inoslen) 710 != DDI_SUCCESS) { 711 ret = DDI_FAILURE; 712 break; 713 } 714 *(int *)result = inoslen / sizeof (uint32_t); 715 kmem_free(inos_p, inoslen); 716 } 717 break; 718 default: 719 ret = DDI_ENOTSUP; 720 break; 721 } 722 723 DBG(DBG_INTROPS, dip, "niumx_intr_ops: ret=%d\n", ret); 724 return (ret); 725 } 726 727 int 728 niumx_set_intr(dev_info_t *dip, dev_info_t *rdip, 729 ddi_intr_handle_impl_t *hdlp, int valid) 730 { 731 niumx_ih_t *ih_p; 732 devino_t *inos_p; 733 int inoslen, ret = DDI_SUCCESS; 734 uint64_t hvret; 735 736 DBG(DBG_A_INTX, dip, "niumx_set_intr: rdip=%s%d, valid=%d\n", 737 NAMEINST(rdip), valid); 738 739 ASSERT(hdlp->ih_inum < NIUMX_MAX_INTRS); 740 741 /* find the appropriate slot from the fixed table */ 742 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 743 "interrupts", (caddr_t)&inos_p, &inoslen) != DDI_SUCCESS) { 744 ret = DDI_FAILURE; 745 goto fail; 746 } 747 ih_p = niumx_ihtable + inos_p[hdlp->ih_inum]; 748 DBG(DBG_A_INTX, dip, "enabling (%x,%x,%x)\n", ih_p->ih_inum, 749 ih_p->ih_ino, ih_p->ih_sysino); 750 751 if ((hvret = hvio_intr_setvalid(ih_p->ih_sysino, valid)) 752 != H_EOK) { 753 DBG(DBG_A_INTX, dip, "hvio_intr_setvalid failed, ret 0x%x\n", 754 hvret); 755 ret = DDI_FAILURE; 756 } 757 kmem_free(inos_p, inoslen); 758 fail: 759 return (ret); 760 } 761 762 763 764 /* 765 * niumx_add_intr: 766 * 767 * This is the leaf/nexus/HV mapping, now read from "interrupts": 768 * 769 * we have a range of 64 to work with: 770 * [0-15] - reserved 771 * [16] - mac0 772 * [17] - MIF 773 * [18] - SYSERR 774 * [19-26] - func0 Rx (qty. 8) 775 * [27-34] - func0 Tx (qty. 8) 776 * [35] - mac1 777 * [36-43] - func1 Rx (qty. 8) 778 * [44-51] - func1 Tx (qty. 8) 779 * 780 * [52] - Error Interrupt hook 781 */ 782 int 783 niumx_add_intr(dev_info_t *dip, dev_info_t *rdip, 784 ddi_intr_handle_impl_t *hdlp) 785 { 786 niumx_ih_t *ih_p; 787 int inoslen, ret = DDI_SUCCESS; 788 uint64_t hvret; 789 devino_t *inos_p; 790 sysino_t sysino; 791 792 /* FMA Err handling hook */ 793 if (dip == rdip) { 794 /* 795 * this is not the leaf calling us, so hardwire in the 796 * FMA interrupt details. 797 */ 798 ih_p = niumx_ihtable + NIUMX_EI_IH; 799 ih_p->ih_ino = NIUMX_EI_IH; 800 goto get_sysino; 801 } 802 803 /* get new ino */ 804 if (hdlp->ih_inum >= NIUMX_MAX_INTRS) { 805 DBG(DBG_INTR, dip, "error: inum %d out of range\n", 806 hdlp->ih_inum); 807 ret = DDI_FAILURE; 808 goto done; 809 } 810 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 811 "interrupts", (caddr_t)&inos_p, &inoslen) != DDI_SUCCESS) { 812 ret = DDI_FAILURE; 813 goto done; 814 } 815 ih_p = niumx_ihtable + inos_p[hdlp->ih_inum]; 816 ih_p->ih_ino = inos_p[hdlp->ih_inum]; 817 kmem_free(inos_p, inoslen); 818 get_sysino: 819 if ((hvret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 820 ih_p->ih_ino, &sysino)) != H_EOK) { 821 DBG(DBG_INTR, dip, "hvio_intr_devino_to_sysino failed, " 822 "ret 0x%x\n", hvret); 823 ret = DDI_FAILURE; 824 goto done; 825 } 826 ih_p->ih_sysino = sysino; 827 ih_p->ih_dip = dip; 828 ih_p->ih_inum = hdlp->ih_inum; 829 ih_p->ih_hdlr = hdlp->ih_cb_func; 830 ih_p->ih_arg1 = hdlp->ih_cb_arg1; 831 ih_p->ih_arg2 = hdlp->ih_cb_arg2; 832 833 DBG(DBG_A_INTX, dip, "niumx_add_intr: rdip=%s%d inum=0x%x " 834 "handler=%p arg1=%p arg2=%p, new ih_p = %p\n", NAMEINST(rdip), 835 hdlp->ih_inum, hdlp->ih_cb_func, hdlp->ih_cb_arg1, 836 hdlp->ih_cb_arg2, ih_p); 837 838 if (hdlp->ih_pri == 0) 839 hdlp->ih_pri = NIUMX_DEFAULT_PIL; 840 841 /* Save sysino value in hdlp */ 842 hdlp->ih_vector = ih_p->ih_sysino; 843 844 /* swap in our handler & arg */ 845 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, (ddi_intr_handler_t *)niumx_intr_hdlr, 846 (void *)ih_p, NULL); 847 848 DBG(DBG_A_INTX, dip, "adding (%x,%x,%x)\n", ih_p->ih_inum, 849 ih_p->ih_ino, ih_p->ih_sysino); 850 ret = i_ddi_add_ivintr(hdlp); 851 852 /* Restore orig. interrupt handler & args in handle. */ 853 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_hdlr, ih_p->ih_arg1, 854 ih_p->ih_arg2); 855 856 if (ret != DDI_SUCCESS) { 857 DBG(DBG_A_INTX, dip, "i_ddi_add_ivintr error ret=%x\n", ret); 858 goto done; 859 } 860 861 /* select cpu, saving it for removal */ 862 ih_p->ih_cpuid = intr_dist_cpuid(); 863 864 if ((hvret = hvio_intr_settarget(ih_p->ih_sysino, ih_p->ih_cpuid)) 865 != H_EOK) { 866 DBG(DBG_A_INTX, dip, "hvio_intr_settarget failed, ret 0x%x\n", 867 hvret); 868 ret = DDI_FAILURE; 869 } 870 done: 871 DBG(DBG_A_INTX, dip, "done, ret = %d, ih_p 0x%p, hdlp 0x%p\n", ih_p, 872 hdlp, ret); 873 return (ret); 874 } 875 876 /* 877 * niumx_rem_intr: 878 * 879 * This function is called to unregister interrupts. 880 */ 881 int 882 niumx_rem_intr(dev_info_t *dip, dev_info_t *rdip, 883 ddi_intr_handle_impl_t *hdlp) 884 { 885 niumx_ih_t *ih_p; 886 cpuid_t curr_cpu; 887 devino_t *inos_p; 888 int inoslen, ret = DDI_SUCCESS; 889 uint64_t hvret; 890 891 ASSERT(hdlp->ih_inum < NIUMX_MAX_INTRS); 892 893 /* find the appropriate slot from the fixed table */ 894 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 895 "interrupts", (caddr_t)&inos_p, &inoslen) != DDI_SUCCESS) { 896 ret = DDI_FAILURE; 897 goto fail1; 898 } 899 ih_p = niumx_ihtable + inos_p[hdlp->ih_inum]; 900 DBG(DBG_R_INTX, dip, "removing (%x,%x,%x)\n", ih_p->ih_inum, 901 ih_p->ih_ino, ih_p->ih_sysino); 902 903 /* Get the current cpu */ 904 if ((hvret = hvio_intr_gettarget(ih_p->ih_sysino, &curr_cpu)) 905 != H_EOK) { 906 DBG(DBG_R_INTX, dip, "hvio_intr_gettarget failed, ret 0x%x\n", 907 hvret); 908 ret = DDI_FAILURE; 909 goto fail2; 910 } 911 912 intr_dist_cpuid_rem_device_weight(ih_p->ih_cpuid, rdip); 913 914 hdlp->ih_vector = ih_p->ih_sysino; 915 if (hdlp->ih_vector != NULL) i_ddi_rem_ivintr(hdlp); 916 917 /* clear out this entry */ 918 ih_p->ih_ino = NULL; 919 fail2: 920 kmem_free(inos_p, inoslen); 921 fail1: 922 return (ret); 923 } 924 925 /* 926 * niumx_intr_hdlr (our interrupt handler) 927 */ 928 uint_t 929 niumx_intr_hdlr(void *arg) 930 { 931 niumx_ih_t *ih_p = (niumx_ih_t *)arg; 932 uint_t r; 933 934 DTRACE_PROBE4(interrupt__start, dev_info_t, ih_p->ih_dip, void *, 935 ih_p->ih_hdlr, caddr_t, ih_p->ih_arg1, caddr_t, ih_p->ih_arg2); 936 937 r = (*ih_p->ih_hdlr)(ih_p->ih_arg1, ih_p->ih_arg2); 938 939 DTRACE_PROBE4(interrupt__complete, dev_info_t, ih_p->ih_dip, void *, 940 ih_p->ih_hdlr, caddr_t, ih_p->ih_arg1, int, r); 941 return (r); 942 } 943 944 #ifdef DEBUG 945 uint64_t niumx_debug_flags = 0; 946 947 static char *niumx_debug_sym [] = { /* same sequence as niumx_debug_bit */ 948 /* 0 */ "attach", 949 /* 1 */ "map", 950 /* 2 */ "nex-ctlops", 951 /* 3 */ "introps", 952 /* 4 */ "intr-add", 953 /* 5 */ "intr-rem", 954 /* 6 */ "intr", 955 /* 7 */ "dma-alloc", 956 /* 8 */ "dma-bind", 957 /* 9 */ "dma-unbind", 958 /* 10 */ "chk-dma-mode" 959 }; 960 961 /*ARGSUSED*/ 962 void 963 niumx_dbg(niumx_debug_bit_t bit, dev_info_t *dip, char *fmt, ...) 964 { 965 va_list ap; 966 char msgbuf[1024]; 967 968 if (!(1ull << bit & niumx_debug_flags)) 969 return; 970 va_start(ap, fmt); 971 (void) vsprintf(msgbuf, fmt, ap); 972 va_end(ap); 973 cmn_err(CE_NOTE, "%s: %s", niumx_debug_sym[bit], msgbuf); 974 } 975 976 #endif /* DEBUG */ 977