1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCISCH_H 27 #define _SYS_PCISCH_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Performance counters information. 37 */ 38 #define SCHIZO_SHIFT_PIC0 4 39 #define SCHIZO_SHIFT_PIC1 11 40 41 /* 42 * Schizo-specific register offsets & bit field positions. 43 */ 44 45 /* 46 * [msb] [lsb] 47 * 0x00 <chip_type> <version#> <module-revision#> 48 */ 49 #define SCHIZO_VER_10 CHIP_ID(PCI_CHIP_SCHIZO, 0x00, 0x00) 50 #define SCHIZO_VER_20 CHIP_ID(PCI_CHIP_SCHIZO, 0x02, 0x00) 51 #define SCHIZO_VER_21 CHIP_ID(PCI_CHIP_SCHIZO, 0x03, 0x00) 52 #define SCHIZO_VER_22 CHIP_ID(PCI_CHIP_SCHIZO, 0x04, 0x00) 53 #define SCHIZO_VER_23 CHIP_ID(PCI_CHIP_SCHIZO, 0x05, 0x00) 54 #define SCHIZO_VER_24 CHIP_ID(PCI_CHIP_SCHIZO, 0x06, 0x00) 55 #define SCHIZO_VER_25 CHIP_ID(PCI_CHIP_SCHIZO, 0x07, 0x00) 56 #define XMITS_VER_10 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x01) 57 #define XMITS_VER_21 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x03) 58 #define XMITS_VER_30 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x04) 59 #define TOMATILLO_VER_10 CHIP_ID(PCI_CHIP_TOMATILLO, 0x00, 0x00) 60 #define TOMATILLO_VER_20 CHIP_ID(PCI_CHIP_TOMATILLO, 0x01, 0x00) 61 #define TOMATILLO_VER_21 CHIP_ID(PCI_CHIP_TOMATILLO, 0x02, 0x00) 62 #define TOMATILLO_VER_22 CHIP_ID(PCI_CHIP_TOMATILLO, 0x03, 0x00) 63 #define TOMATILLO_VER_23 CHIP_ID(PCI_CHIP_TOMATILLO, 0x04, 0x00) 64 #define TOMATILLO_VER_24 CHIP_ID(PCI_CHIP_TOMATILLO, 0X05, 0X00) 65 66 /* 67 * Offsets of Control Block registers ("reg" property 2nd entry) 68 */ 69 #define SCHIZO_CB_CSR_OFFSET 0x0 /* reg 1 */ 70 #define SCHIZO_CB_ERRCTRL_OFFSET 0x8 71 #define SCHIZO_CB_INTCTRL_OFFSET 0x10 72 #define SCHIZO_CB_ERRLOG_OFFSET 0x18 73 #define SCHIZO_CB_ECCCTRL_OFFSET 0x20 74 #define SCHIZO_CB_UEAFSR_OFFSET 0x30 75 #define SCHIZO_CB_UEAFAR_OFFSET 0x38 76 #define SCHIZO_CB_CEAFSR_OFFSET 0x40 77 #define SCHIZO_CB_CEAFAR_OFFSET 0x48 78 #define SCHIZO_CB_ESTRCTRL_OFFSET 0x50 79 #define XMITS_CB_SOFT_PAUSE_OFFSET 0x58 80 #define XMITS_CB_IO_LOOPBACK_CONTROL_OFFSET 0x60 81 #define XMITS_CB_SAF_PED_CONTROL_OFFSET 0x68 82 #define XMITS_CB_SAF_PED_LOG_OFFSET 0x70 83 #define XMITS_CB_SAF_PAR_INJECT_IMM_OFFSET 0x78 84 #define XMITS_CB_SAF_PAR_INJECT_1_OFFSET 0x80 85 #define XMITS_CB_SAF_PAR_INJECT_0_OFFSET 0x88 86 #define XMITS_CB_FIRST_ERROR_LOG 0x90 87 #define XMITS_CB_FIRST_ERROR_ADDR 0x98 88 #define XMITS_CB_PCI_LEAF_STATUS 0xA0 89 90 /* 91 * Tomatillo only bits in IOMMU control registers. 92 */ 93 #define TOMATILLO_IOMMU_SEG_DISP_SHIFT 4 94 #define TOMATILLO_IOMMU_TSB_MAX 7 95 #define TOMATIILO_IOMMU_ERR_REG_SHIFT 24 96 #define TOMATILLO_IOMMU_ERRSTS_SHIFT 25 97 #define TOMATILLO_IOMMU_ERR (1ull << 24) 98 #define TOMATILLO_IOMMU_ERRSTS (3ull << 25) 99 #define TOMATILLO_IOMMU_ERR_ILLTSBTBW (1ull << 27) 100 #define TOMATILLO_IOMMU_ERR_BAD_VA (1ull << 28) 101 102 #define TOMATILLO_IOMMU_PROTECTION_ERR 0x0 103 #define TOMATILLO_IOMMU_INVALID_ERR 0x1 104 #define TOMATILLO_IOMMU_TIMEOUT_ERR 0x2 105 #define TOMATILLO_IOMMU_ECC_ERR 0x3 106 107 /* 108 * Offsets of performance monitoring registers. 109 */ 110 #define SCHIZO_PERF_PCI_PCR_OFFSET 0x00000100 111 #define SCHIZO_PERF_PCI_PIC_OFFSET 0x00000108 112 #define SCHIZO_PERF_PCI_ICD_OFFSET 0x00000110 113 #define SCHIZO_PERF_SAF_PCR_OFFSET 0x00007000 114 #define SCHIZO_PERF_SAF_PIC_OFFSET 0x00007008 115 116 /* 117 * Offsets of registers in the PBM block: 118 */ 119 #define SCHIZO_PCI_CTRL_REG_OFFSET 0x2000 120 #define SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET 0x2010 121 #define SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET 0x2018 122 #define SCHIZO_PCI_DIAG_REG_OFFSET 0x2020 123 #define SCHIZO_PCI_ESTAR_REG_OFFSET 0x2028 124 #define TOMATILLO_TGT_ADDR_SPACE_OFFSET 0x2490 125 #define TOMATILLO_TGT_ERR_VALOG_OFFSET 0x2498 126 127 #define XMITS10_PCI_X_ERROR_STATUS_REG_OFFSET 0x2030 128 #define XMITS10_PCI_X_DIAG_REG_OFFSET 0x2038 129 #define XMITS_PCI_X_ERROR_STATUS_REG_OFFSET 0x2300 130 #define XMITS_PCI_X_DIAG_REG_OFFSET 0x2308 131 #define XMITS_PARITY_DETECT_REG_OFFSET 0x2040 132 #define XMITS_PARITY_LOG_REG_OFFSET 0x2048 133 #define XMITS_PARITY_INJECT_REG_OFFSET 0x2050 134 #define XMITS_PARITY_INJECT_1_REG_OFFSET 0x2058 135 #define XMITS_PARITY_INJECT_0_REG_OFFSET 0x2060 136 #define XMITS_UPPER_RETRY_COUNTER_REG_OFFSET 0x2310 137 138 /* 139 * Offsets of IO Cache Registers: 140 */ 141 #define TOMATILLO_IOC_CSR_OFF 0x2248 142 #define TOMATILLO_IOC_TAG_OFF 0x2250 143 #define TOMATIILO_IOC_DAT_OFF 0x2290 144 145 /* 146 * Offsets of registers in the iommu block: 147 */ 148 #define SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET 0x00000218 149 #define TOMATILLO_IOMMU_ERR_TFAR_OFFSET 0x0220 150 151 /* 152 * Offsets of registers in the streaming cache block: 153 */ 154 #define SCHIZO_SC_CTRL_REG_OFFSET 0x00002800 155 #define SCHIZO_SC_INVL_REG_OFFSET 0x00002808 156 #define SCHIZO_SC_SYNC_REG_OFFSET 0x00002810 157 #define SCHIZO_SC_CTX_INVL_REG_OFFSET 0x00002818 158 #define SCHIZO_SC_CTX_MATCH_REG_OFFSET 0x00010000 159 #define SCHIZO_SC_DATA_DIAG_OFFSET 0x0000b000 160 #define SCHIZO_SC_TAG_DIAG_OFFSET 0x0000ba00 161 #define SCHIZO_SC_LTAG_DIAG_OFFSET 0x0000bb00 162 163 /* 164 * MAX_PRF when enabled will always prefetch the max of 8 165 * prefetches if possible. 166 */ 167 #define XMITS_SC_MAX_PRF (0x1ull << 7) 168 169 /* 170 * Offsets of registers in the PCI Idle Check Diagnostics Register. 171 */ 172 #define SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE 0x4000 173 #define SCHIZO_PERF_PCI_ICD_PCI_2_0_COMPATIBLE 0x8000 174 175 /* 176 * Offsets of registers in the interrupt block: 177 */ 178 #define SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET 0x1100 179 #define SCHIZO_IB_INTR_MAP_REG_OFFSET 0x1000 180 #define SCHIZO_IB_CLEAR_INTR_REG_OFFSET 0x1400 181 #define SCHIZO_PBM_DMA_SYNC_REG_OFFSET 0x1A08 182 #define PBM_DMA_SYNC_COMP_REG_OFFSET 0x1A10 183 #define PBM_DMA_SYNC_PEND_REG_OFFSET 0x1A18 184 185 /* 186 * Address space offsets and sizes: 187 */ 188 #define SCHIZO_SIZE 0x0000800000000000ull 189 190 /* 191 * Schizo-specific fields of interrupt mapping register: 192 */ 193 #define SCHIZO_INTR_MAP_REG_NID 0x0000000003E00000ull 194 #define SCHIZO_INTR_MAP_REG_NID_SHIFT 21 195 196 /* 197 * schizo ECC UE AFSR bit definitions: 198 */ 199 #define SCHIZO_ECC_UE_AFSR_ERRPNDG 0x0300000000000000ull 200 #define SCHIZO_ECC_UE_AFSR_MASK 0x000003ff00000000ull 201 #define SCHIZO_ECC_UE_AFSR_MASK_SHIFT 32 202 #define SCHIZO_ECC_UE_AFSR_QW_OFFSET 0x00000000C0000000ull 203 #define SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT 30 204 #define SCHIZO_ECC_UE_AFSR_AGENT_MID 0x000000001f000000ull 205 #define SCHIZO_ECC_UE_AFSR_AGENT_MID_SHIFT 24 206 #define SCHIZO_ECC_UE_AFSR_PARTIAL 0x0000000000800000ull 207 #define SCHIZO_ECC_UE_AFSR_OWNED_IN 0x0000000000400000ull 208 #define SCHIZO_ECC_UE_AFSR_MTAG_SYND 0x00000000000f0000ull 209 #define SCHIZO_ECC_UE_AFSR_MTAG_SYND_SHIFT 16 210 #define SCHIZO_ECC_UE_AFSR_MTAG 0x000000000000e000ull 211 #define SCHIZO_ECC_UE_AFSR_MTAG_SHIFT 13 212 #define SCHIZO_ECC_UE_AFSR_SYND 0x00000000000001ffull 213 #define SCHIZO_ECC_UE_AFSR_SYND_SHIFT 0 214 215 /* 216 * schizo ECC CE AFSR bit definitions: 217 */ 218 #define SCHIZO_ECC_CE_AFSR_ERRPNDG 0x0300000000000000ull 219 #define SCHIZO_ECC_CE_AFSR_MASK 0x000003ff00000000ull 220 #define SCHIZO_ECC_CE_AFSR_MASK_SHIFT 32 221 #define SCHIZO_ECC_CE_AFSR_QW_OFFSET 0x00000000C0000000ull 222 #define SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT 30 223 #define SCHIZO_ECC_CE_AFSR_AGENT_MID 0x000000001f000000ull 224 #define SCHIZO_ECC_CE_AFSR_AGENT_MID_SHIFT 24 225 #define SCHIZO_ECC_CE_AFSR_PARTIAL 0x0000000000800000ull 226 #define SCHIZO_ECC_CE_AFSR_OWNED_IN 0x0000000000400000ull 227 #define SCHIZO_ECC_CE_AFSR_MTAG_SYND 0x00000000000f0000ull 228 #define SCHIZO_ECC_CE_AFSR_MTAG_SYND_SHIFT 16 229 #define SCHIZO_ECC_CE_AFSR_MTAG 0x000000000000e000ull 230 #define SCHIZO_ECC_CE_AFSR_MTAG_SHIFT 13 231 #define SCHIZO_ECC_CE_AFSR_SYND 0x00000000000001ffull 232 #define SCHIZO_ECC_CE_AFSR_SYND_SHIFT 0 233 234 /* 235 * schizo ECC UE/CE AFAR bit definitions: 236 */ 237 #define SCHIZO_ECC_AFAR_IO_TXN 0x0000080000000000ull 238 #define SCHIZO_ECC_AFAR_PIOW_MASK 0x0000078000000000ull 239 #define SCHIZO_ECC_AFAR_PIOW_UPA64S 0x0000078000000000ull 240 #define SCHIZO_ECC_AFAR_PIOW_NL_REG 0x0000040000000000ull 241 #define SCHIZO_ECC_AFAR_PIOW_NL 0x0000050000000000ull 242 #define SCHIZO_ECC_AFAR_PIOW_NL_ALT 0x0000051000000000ull 243 #define SCHIZO_ECC_AFAR_PIOW_PCIA_REG 0x0000020000000000ull 244 #define SCHIZO_ECC_AFAR_PIOW_PCIA_MEM 0x0000030000000000ull 245 #define SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO 0x0000031000000000ull 246 #define SCHIZO_ECC_AFAR_PIOW_PCIB_REG 0x0000000000000000ull 247 #define SCHIZO_ECC_AFAR_PIOW_PCIB_MEM 0x0000010000000000ull 248 #define SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO 0x0000011000000000ull 249 #define SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS 0x0000060000000000ull 250 #define SCHIZO_ECC_AFAR_PIOW_ADDR_MASK 0x0000000fffffffffull 251 #define SCHIZO_ECC_AFAR_ADDR_MASK 0x000007ffffffffffull 252 253 /* 254 * schizo pci control register bits: 255 */ 256 #define SCHIZO_PCI_CTRL_BUS_UNUSABLE (1ull << 63) 257 #define TOMATILLO_PCI_CTRL_PCI_DTO_ERR (1ull << 62) 258 #define TOMATILLO_PCI_CTRL_DTO_INT_EN (1ull << 61) 259 #define SCHIZO_PCI_CTRL_ERR_SLOT_LOCK (1ull << 51) 260 #define SCHIZO_PCI_CTRL_ERR_SLOT (7ull << 48) 261 #define SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT 48 262 #define SCHIZO_PCI_CTRL_PCI_TTO_ERR (1ull << 38) 263 #define SCHIZO_PCI_CTRL_PCI_RTRY_ERR (1ull << 37) 264 #define SCHIZO_PCI_CTRL_PCI_MMU_ERR (1ull << 36) 265 #define TOMATILLO_PCI_CTRL_PEN_RD_MLTPL (1ull << 30) 266 #define TOMATILLO_PCI_CTRL_PEN_RD_ONE (1ull << 29) 267 #define TOMATILLO_PCI_CTRL_PEN_RD_LINE (1ull << 28) 268 #define TOMATILLO_PCI_CTRL_FRC_TRGT_ABRT (1ull << 27) 269 #define TOMATILLO_PCI_CTRL_FRC_TRGT_RTRY (1ull << 26) 270 #define SCHIZO_PCI_CTRL_PTO (3ull << 24) 271 #define SCHIZO_PCI_CTRL_PTO_SHIFT 24 272 #define TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT (3ull << 21) 273 #define TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT_SHIFT 21 274 #define SCHIZO_PCI_CTRL_MMU_INT_EN (1ull << 19) 275 #define SCHIZO_PCI_CTRL_SBH_INT_EN (1ull << 18) 276 #define SCHIZO_PCI_CTRL_ERR_INT_EN (1ull << 17) 277 #define SCHIZO_PCI_CTRL_ARB_PARK (1ull << 16) 278 #define SCHIZO_PCI_CTRL_RST (1ull << 8) 279 #define SCHIZO_PCI_CTRL_ARB_EN_MASK 0xffull 280 281 #define XMITS10_PCI_CTRL_ARB_EN_MASK 0x0full 282 #define XMITS_PCI_CTRL_X_MODE (0x1ull << 32) 283 #define XMITS_PCI_CTRL_X_ERRINT_EN (0x1ull << 20) 284 #define XMITS_PCI_CTRL_DMA_WR_PERR (0x1ull << 51) 285 286 /* 287 * schizo PCI asynchronous fault status register bit definitions: 288 */ 289 #define SCHIZO_PCI_AFSR_PE_SHIFT 58 290 #define SCHIZO_PCI_AFSR_SE_SHIFT 52 291 #define SCHIZO_PCI_AFSR_E_MA 0x0000000000000020ull 292 #define SCHIZO_PCI_AFSR_E_TA 0x0000000000000010ull 293 #define SCHIZO_PCI_AFSR_E_RTRY 0x0000000000000008ull 294 #define SCHIZO_PCI_AFSR_E_PERR 0x0000000000000004ull 295 #define SCHIZO_PCI_AFSR_E_TTO 0x0000000000000002ull 296 #define SCHIZO_PCI_AFSR_E_UNUSABLE 0x0000000000000001ull 297 #define SCHIZO_PCI_AFSR_E_MASK 0x000000000000003full 298 #define SCHIZO_PCI_AFSR_DWORDMASK 0x0000030000000000ull 299 #define SCHIZO_PCI_AFSR_DWORDMASK_SHIFT 40 300 #define SCHIZO_PCI_AFSR_BYTEMASK 0x000000ff00000000ull 301 #define SCHIZO_PCI_AFSR_BYTEMASK_SHIFT 32 302 #define SCHIZO_PCI_AFSR_BLK 0x0000000080000000ull 303 #define SCHIZO_PCI_AFSR_CONF_SPACE 0x0000000040000000ull 304 #define SCHIZO_PCI_AFSR_MEM_SPACE 0x0000000020000000ull 305 #define SCHIZO_PCI_AFSR_IO_SPACE 0x0000000010000000ull 306 307 /* Schizo/Xmits control block Safari Error log bits */ 308 #define SCHIZO_CB_ELOG_BAD_CMD (0x1ull << 62) 309 #define SCHIZO_CB_ELOG_SSM_DIS (0x1ull << 61) 310 #define SCHIZO_CB_ELOG_BAD_CMD_PCIA (0x1ull << 60) 311 #define SCHIZO_CB_ELOG_BAD_CMD_PCIB (0x1ull << 59) 312 #define XMITS_CB_ELOG_PAR_ERR_INT_PCIB (0x1ull << 19) 313 #define XMITS_CB_ELOG_PAR_ERR_INT_PCIA (0x1ull << 18) 314 #define XMITS_CB_ELOG_PAR_ERR_INT_SAF (0x1ull << 17) 315 #define XMITS_CB_ELOG_PLL_ERR_PCIB (0x1ull << 16) 316 #define XMITS_CB_ELOG_PLL_ERR_PCIA (0x1ull << 15) 317 #define XMITS_CB_ELOG_PLL_ERR_SAF (0x1ull << 14) 318 #define SCHIZO_CB_ELOG_CPU1_PAR_SINGLE (0x1ull << 13) 319 #define SCHIZO_CB_ELOG_CPU1_PAR_BIDI (0x1ull << 12) 320 #define SCHIZO_CB_ELOG_CPU0_PAR_SINGLE (0x1ull << 11) 321 #define SCHIZO_CB_ELOG_CPU0_PAR_BIDI (0x1ull << 10) 322 #define SCHIZO_CB_ELOG_SAF_CIQ_TO (0x1ull << 9) 323 #define SCHIZO_CB_ELOG_SAF_LPQ_TO (0x1ull << 8) 324 #define SCHIZO_CB_ELOG_SAF_SFPQ_TO (0x1ull << 7) 325 #define SCHIZO_CB_ELOG_SAF_UFPQ_TO (0x1ull << 6) 326 #define SCHIZO_CB_ELOG_ADDR_PAR_ERR (0x1ull << 5) 327 #define SCHIZO_CB_ELOG_UNMAP_ERR (0x1ull << 4) 328 #define SCHIZO_CB_ELOG_BUS_ERR (0x1ull << 2) 329 #define SCHIZO_CB_ELOG_TO_ERR (0x1ull << 1) 330 #define SCHIZO_CB_ELOG_DSTAT_ERR 0x1ull 331 332 /* Used for the tomatillo micro tlb bug. errata #82 */ 333 #define SCHIZO_VPN_MASK ((1 << 19) - 1) 334 335 /* Tomatillo control block JBUS error log bits */ 336 #define TOMATILLO_CB_ELOG_SNOOP_ERR_GR (0x1ull << 21) 337 #define TOMATILLO_CB_ELOG_SNOOP_ERR_PCI (0x1ull << 20) 338 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RD (0x1ull << 19) 339 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDS (0x1ull << 17) 340 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA (0x1ull << 16) 341 #define TOMATILLO_CB_ELOG_SNOOP_ERR_OWN (0x1ull << 15) 342 #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDO (0x1ull << 14) 343 #define TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR (0x1ull << 13) 344 #define TOMATILLO_CB_ELOG_CTL_PAR_ERR (0x1ull << 12) 345 #define TOMATILLO_CB_ELOG_SNOOP_ERR (0x1ull << 11) 346 #define TOMATILLO_CB_ELOG_ILL_BYTE_EN (0x1ull << 10) 347 #define TOMATILLO_CB_ELOG_ILL_COH_IN (0x1ull << 8) 348 #define TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR (0x1ull << 6) 349 #define TOMATILLO_CB_ELOG_TO_EXP_ERR (0x1ull << 3) 350 351 /* Tomatillo control block JBUS control/status bits */ 352 #define TOMATILLO_CB_CSR_CTRL_PERR_GEN (0x1ull << 29) 353 354 #define XMITS_PCI_X_AFSR_P_SC_ERR (0x1ull << 51) 355 #define XMITS_PCI_X_AFSR_S_SC_ERR (0x1ull << 50) 356 357 #define XMITS_PCIX_MSG_CLASS_MASK 0xf00 358 #define XMITS_PCIX_MSG_INDEX_MASK 0xff 359 #define XMITS_PCIX_MSG_MASK \ 360 (XMITS_PCIX_MSG_CLASS_MASK | XMITS_PCIX_MSG_INDEX_MASK) 361 362 #define XMITS_PCI_X_P_MSG_SHIFT 16 363 #define XMITS_PCI_X_S_MSG_SHIFT 4 364 365 #define PBM_AFSR_TO_PRIERR(afsr) \ 366 (afsr >> SCHIZO_PCI_AFSR_PE_SHIFT & SCHIZO_PCI_AFSR_E_MASK) 367 #define PBM_AFSR_TO_SECERR(afsr) \ 368 (afsr >> SCHIZO_PCI_AFSR_SE_SHIFT & SCHIZO_PCI_AFSR_E_MASK) 369 #define PBM_AFSR_TO_BYTEMASK(afsr) \ 370 ((afsr & SCHIZO_PCI_AFSR_BYTEMASK) >> SCHIZO_PCI_AFSR_BYTEMASK_SHIFT) 371 #define PBM_AFSR_TO_DWORDMASK(afsr) \ 372 ((afsr & SCHIZO_PCI_AFSR_DWORDMASK) >> \ 373 SCHIZO_PCI_AFSR_DWORDMASK_SHIFT) 374 375 /* 376 * XMITS Upper Retry Counter Register (bits 15:0) 377 */ 378 #define XMITS_UPPER_RETRY_MASK 0xFFFF 379 380 /* 381 * XMITS PCI-X Diagnostic Register bit definitions 382 */ 383 #define XMITS_PCI_X_DIAG_DIS_FAIR (0x1ull << 19) 384 #define XMITS_PCI_X_DIAG_CRCQ_VALID (0x1ull << 18) 385 #define XMITS_PCI_X_DIAG_SRCQ_VALID_SHIFT 10 386 #define XMITS_PCI_X_DIAG_SRCQ_ONE (0x1ull << 9) 387 #define XMITS_PCI_X_DIAG_CRCQ_FLUSH (0x1ull << 8) 388 #define XMITS_PCI_X_DIAG_SRCQ_FLUSH_SHIFT 0 389 390 #define XMITS_PCI_X_DIAG_SRCQ_MASK 0xff 391 392 /* 393 * XMITS PCI-X Error Status Register bit definitions 394 */ 395 396 #define XMITS_PCI_X_STATUS_PE_SHIFT 58 397 #define XMITS_PCI_X_STATUS_SE_SHIFT 50 398 #define XMITS_PCI_X_STATUS_E_MASK 0x3f 399 #define XMITS_PCI_X_STATUS_PFAR_MASK 0xffffffff 400 #define XMITS_PCIX_STAT_SC_DSCRD 0x20ull 401 #define XMITS_PCIX_STAT_SC_TTO 0x10ull 402 #define XMITS_PCIX_STAT_SMMU 0x8ull 403 #define XMITS_PCIX_STAT_SDSTAT 0x4ull 404 #define XMITS_PCIX_STAT_CMMU 0x2ull 405 #define XMITS_PCIX_STAT_CDSTAT 0x1ull 406 #define XMITS_PCIX_STAT_SERR_ON_PERR (1ull << 32) 407 #define XMITS_PCIX_STAT_PERR_RECOV_INT_EN (1ull << 33) 408 #define XMITS_PCIX_STAT_PERR_RECOV_INT (1ull << 34) 409 410 /* 411 * PCI-X Message Classes and Indexes 412 */ 413 #define PCIX_CLASS_WRITE_COMPLETION 0x000 414 #define PCIX_WRITE_COMPLETION_NORMAL 0x00 415 416 #define PCIX_CLASS_BRIDGE 0x100 417 #define PCIX_BRIDGE_MASTER_ABORT 0x00 418 #define PCIX_BRIDGE_TARGET_ABORT 0x01 419 #define PCIX_BRIDGE_WRITE_DATA_PARITY 0x02 420 421 #define PCIX_CLASS_CPLT 0x200 422 #define PCIX_CPLT_OUT_OF_RANGE 0x00 423 #define PCIX_CPLT_SPLIT_WRITE_DATA 0x01 424 #define XMITS_CPLT_NO_ERROR 0x80 425 #define XMITS_CPLT_STREAM_DSTAT 0x81 426 #define XMITS_CPLT_STREAM_MMU 0x82 427 #define XMITS_CPLT_CONSIST_DSTAT 0x85 428 #define XMITS_CPLT_CONSIST_MMU 0x86 429 430 #define PCIX_NO_CLASS 0x999 431 #define PCIX_MULTI_ERR 1 432 #define PCIX_SINGLE_ERR 0 433 434 #define PBM_PCIX_TO_PRIERR(pcix_stat) \ 435 (pcix_stat >> XMITS_PCI_X_STATUS_PE_SHIFT & XMITS_PCI_X_STATUS_E_MASK) 436 #define PBM_PCIX_TO_SECERR(pcix_stat) \ 437 (pcix_stat >> XMITS_PCI_X_STATUS_SE_SHIFT & XMITS_PCI_X_STATUS_E_MASK) 438 #define PBM_AFSR_TO_PRISPLIT(afsr) \ 439 ((afsr >> XMITS_PCI_X_P_MSG_SHIFT) & XMITS_PCIX_MSG_MASK) 440 #define PBM_AFSR_TO_SECSPLIT(afsr) \ 441 ((afsr >> XMITS_PCI_X_S_MSG_SHIFT) & XMITS_PCIX_MSG_MASK) 442 443 #define PCIX_ERRREG_OFFSET (XMITS_PCI_X_ERROR_STATUS_REG_OFFSET -\ 444 SCHIZO_PCI_CTRL_REG_OFFSET) 445 446 /* 447 * Nested message structure to allow for storing all the PCI-X 448 * split completion messages in tabular form. 449 */ 450 typedef struct pcix_err_msg_rec { 451 uint32_t msg_key; 452 char *msg_class; 453 char *msg_str; 454 } pcix_err_msg_rec_t; 455 456 typedef struct pcix_err_tbl { 457 uint32_t err_class; 458 uint32_t err_rec_num; 459 pcix_err_msg_rec_t *err_msg_tbl; 460 } pcix_err_tbl_t; 461 462 463 /* 464 * Tomatillo IO Cache CSR bit definitions: 465 */ 466 467 #define TOMATILLO_WRT_PEN (1ull << 19) 468 #define TOMATILLO_NC_PEN_RD_MLTPL (1ull << 18) 469 #define TOMATILLO_NC_PEN_RD_ONE (1ull << 17) 470 #define TOMATILLO_NC_PEN_RD_LINE (1ull << 16) 471 #define TOMATILLO_PLEN_RD_MTLPL (3ull << 14) 472 #define TOMATILLO_PLEN_RD_ONE (3ull << 12) 473 #define TOMATILLO_PLEN_RD_LINE (3ull << 10) 474 #define TOMATILLO_POFFSET_SHIFT 3 475 #define TOMATILLO_POFFSET (0x7full << TOMATILLO_POFFSET_SHIFT) 476 #define TOMATILLO_C_PEN_RD_MLTPL (1ull << 2) 477 #define TOMATILLO_C_PEN_RD_ONE (1ull << 1) 478 #define TOMATILLO_C_PEN_RD_LINE (1ull << 0) 479 480 /* 481 * schizo PCI diagnostic register bit definitions: 482 */ 483 #define SCHIZO_PCI_DIAG_DIS_RTRY_ARB 0x0000000000000080ull 484 485 /* 486 * schizo IOMMU TLB TAG diagnostic register bits 487 */ 488 #define TLBTAG_CONTEXT_SHIFT 25 489 #define TLBTAG_ERRSTAT_SHIFT 23 490 #define TLBTAG_CONTEXT_BITS (0xfffull << TLBTAG_CONTEXT_SHIFT) 491 #define TLBTAG_ERRSTAT_BITS (0x3ull << TLBTAG_ERRSTAT_SHIFT) 492 #define TLBTAG_ERR_BIT (0x1ull << 22) 493 #define TLBTAG_WRITABLE_BIT (0x1ull << 21) 494 #define TLBTAG_STREAM_BIT (0x1ull << 20) 495 #define TLBTAG_PGSIZE_BIT (0x1ull << 19) 496 #define TLBTAG_PCIVPN_BITS 0x7ffffull 497 498 #define TLBTAG_ERRSTAT_PROT 0 499 #define TLBTAG_ERRSTAT_INVALID 1 500 #define TLBTAG_ERRSTAT_TIMEOUT 2 501 #define TLBTAG_ERRSTAT_ECCUE 3 502 503 /* 504 * schizo IOMMU TLB Data RAM diagnostic register bits 505 */ 506 #define TLBDATA_VALID_BIT (0x1ull << 32) 507 #define TLBDATA_CACHE_BIT (0x1ull << 30) 508 #define TLBDATA_MEMPA_BITS ((0x1ull << 30) - 1) 509 510 extern uint_t cb_buserr_intr(caddr_t a); 511 512 /* 513 * pbm_cdma_flag(schizo only): consistent dma sync handshake 514 */ 515 #define PBM_CDMA_DONE 0xcc /* arbitrary pattern set by interrupt handler */ 516 #define PBM_CDMA_PEND 0x55 /* arbitrary pattern set by sync requester */ 517 #define PBM_CDMA_INO_BASE 0x35 /* ino can be used for cdma sync */ 518 519 /* 520 * Estar control bit for schizo estar reg 521 */ 522 #define SCHIZO_PCI_CTRL_BUS_SPEED 0x0000000000000001ull 523 524 #define PCI_CMN_ID(chip_type, id) \ 525 ((chip_type) == PCI_CHIP_TOMATILLO ? ((id) >> 1) << 1 : (id)) 526 #define PCI_ID_TO_IGN(pci_id) ((pci_ign_t)((pci_id) & 0x1f)) 527 #define PCI_ID_TO_NODEID(pci_id) ((cb_nid_t)((pci_id) >> PCI_IGN_BITS)) 528 529 #define PCI_BRIDGE_TYPE(cmn_p) \ 530 (((cmn_p->pci_chip_id >> 16) == PCI_CHIP_SCHIZO) ? PCI_SCHIZO : \ 531 ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_TOMATILLO) ? PCI_TOMATILLO : \ 532 ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_XMITS) ? PCI_XMITS : "") 533 /* 534 * Tomatillo only 535 */ 536 #define NBIGN(ib_p) ((ib_p)->ib_ign ^ 1) 537 #define IB_INO_TO_NBMONDO(ib_p, ino) IB_IGN_TO_MONDO(NBIGN(ib_p), ino) 538 539 /* 540 * Mask to tell which PCI Side we are on 541 */ 542 #define PCI_SIDE_ADDR_MASK 0x100000ull 543 544 /* 545 * Offset from Schizo Base of Schizo CSR Base 546 */ 547 #define PBM_CTRL_OFFSET 0x410000ull 548 549 /* 550 * The following macro defines the 42-bit bus width support for SAFARI bus 551 * and JBUS in DVMA and iommu bypass transfers: 552 */ 553 554 #define SAFARI_JBUS_IOMMU_BYPASS_END 0xFFFC03FFFFFFFFFFull 555 556 #ifdef __cplusplus 557 } 558 #endif 559 560 #endif /* _SYS_PCISCH_H */ 561