1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCI_SPACE_H 27 #define _SYS_PCI_SPACE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define PCI_SPURINTR_MSG_DEFAULT -1ull 36 37 extern uint_t tomatillo_disallow_bypass; 38 39 extern uint_t pci_interrupt_priorities_property; 40 extern uint_t pci_config_space_size_zero; 41 extern int pci_pbm_dma_sync_wait; 42 extern int pci_dvma_sync_before_unmap; 43 extern int pci_sync_lock; 44 extern int tomatillo_store_store_wrka; 45 extern uint_t tm_mtlb_maxpgs; 46 extern uint_t tm_mtlb_gc; 47 extern uint_t tm_mtlb_gc_manual; 48 extern uint32_t pci_spurintr_duration; 49 extern uint64_t pci_spurintr_msgs; 50 51 52 extern ushort_t pci_command_default; 53 extern uint_t pci_set_latency_timer_register; 54 extern uint_t pci_set_cache_line_size_register; 55 56 #ifdef DEBUG 57 extern uint64_t pci_debug_flags; 58 extern uint_t pci_warn_pp0; 59 #endif 60 extern uint_t pci_disable_pass1_workarounds; 61 extern uint_t pci_disable_pass2_workarounds; 62 extern uint_t pci_disable_pass3_workarounds; 63 extern uint_t pci_disable_plus_workarounds; 64 extern uint_t pci_disable_default_workarounds; 65 extern uint_t ecc_error_intr_enable; 66 extern uint_t pci_sbh_error_intr_enable; 67 extern uint_t pci_mmu_error_intr_enable; 68 extern uint_t pci_stream_buf_enable; 69 extern uint_t pci_stream_buf_exists; 70 extern uint_t pci_rerun_disable; 71 extern uint_t pci_enable_periodic_loopback_dma; 72 extern uint_t pci_enable_retry_arb; 73 74 extern uint_t pci_bus_parking_enable; 75 extern uint_t pci_error_intr_enable; 76 extern uint_t pci_retry_disable; 77 extern uint_t pci_retry_enable; 78 extern uint_t pci_dwsync_disable; 79 extern uint_t pci_intsync_disable; 80 extern uint_t pci_b_arb_enable; 81 extern uint_t pci_a_arb_enable; 82 extern uint_t pci_ecc_afsr_retries; 83 84 extern uint_t pci_intr_retry_intv; 85 extern uint8_t pci_latency_timer; 86 extern uint_t pci_panic_on_sbh_errors; 87 extern uint_t pci_panic_on_fatal_errors; 88 extern uint_t pci_thermal_intr_fatal; 89 extern uint_t pci_buserr_interrupt; 90 extern uint_t pci_set_dto_value; 91 extern uint_t pci_dto_value; 92 extern uint_t pci_lock_sbuf; 93 extern uint_t pci_use_contexts; 94 extern uint_t pci_sc_use_contexts; 95 extern uint_t pci_context_minpages; 96 extern uint_t pci_ctx_flush_warn; 97 extern uint_t pci_ctx_unsuccess_count; 98 extern uint_t pci_ctx_no_active_flush; 99 extern uint_t pci_ctx_no_compat; 100 101 extern uint_t pci_check_all_handlers; 102 extern uint_t pci_unclaimed_intr_max; 103 extern ulong_t pci_iommu_dvma_end; 104 extern uint_t pci_lock_tlb; 105 106 extern uint64_t pci_dvma_debug_on; 107 extern uint64_t pci_dvma_debug_off; 108 extern uint32_t pci_dvma_debug_rec; 109 extern uint_t pci_dvma_page_cache_entries; 110 extern uint_t pci_dvma_page_cache_clustsz; 111 #ifdef PCI_DMA_PROF 112 extern uint_t pci_dvmaft_npages; 113 extern uint_t pci_dvmaft_limit; 114 extern uint_t pci_dvmaft_free; 115 extern uint_t pci_dvmaft_success; 116 extern uint_t pci_dvmaft_exhaust; 117 extern uint_t pci_dvma_vmem_alloc; 118 extern uint_t pci_dvma_vmem_xalloc; 119 extern uint_t pci_dvma_vmem_free; 120 extern uint_t pci_dvma_vmem_xfree; 121 #endif 122 extern uint_t pci_disable_fdvma; 123 124 extern uint_t pci_iommu_ctx_lock_failure; 125 extern uint_t pci_preserve_iommu_tsb; 126 127 extern uint64_t pci_perr_enable; 128 extern uint64_t pci_serr_enable; 129 extern uint64_t pci_perr_fatal; 130 extern uint64_t pci_serr_fatal; 131 extern hrtime_t pci_intrpend_timeout; 132 extern hrtime_t pci_sync_buf_timeout; 133 extern hrtime_t pci_cdma_intr_timeout; 134 extern uint32_t pci_cdma_intr_count; 135 136 extern uint32_t pci_dto_fault_warn; 137 extern uint64_t pci_dto_intr_enable; 138 extern uint64_t pci_dto_count; 139 extern uint64_t pci_errtrig_pa; 140 141 extern uintptr_t pci_kmem_clid; 142 extern uint_t pci_intr_dma_sync; 143 extern uint_t pci_xmits_sc_max_prf; 144 extern uint64_t xmits_error_intr_enable; 145 extern uint_t xmits_perr_recov_int_enable; 146 extern uint_t xmits_max_transactions; 147 extern uint_t xmits_max_read_bytes; 148 extern uint_t xmits_upper_retry_counter; 149 extern uint_t xmits_pcix_diag_bugcntl_pcix; 150 extern uint_t xmits_pcix_diag_bugcntl_pci; 151 extern uint_t pci_mi_enable; 152 extern uint64_t pci_mi_intr_clr; 153 154 extern int pci_dvma_remap_enabled; 155 extern kthread_t *pci_reloc_thread; 156 extern kmutex_t pci_reloc_mutex; 157 extern kcondvar_t pci_reloc_cv; 158 extern int pci_reloc_presuspend; 159 extern int pci_reloc_suspend; 160 extern id_t pci_dvma_cbid; 161 extern id_t pci_fast_dvma_cbid; 162 extern int pci_dma_panic_on_leak; 163 164 #ifdef __cplusplus 165 } 166 #endif 167 168 #endif /* _SYS_PCI_SPACE_H */ 169