1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1994-1998 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_PCI_SIMBA_H 28 #define _SYS_PCI_SIMBA_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * This files contains info specific to Simba (pci to pci bridge) 38 * The rest of info common to simba and DecNet are in "pci.h" 39 */ 40 41 /* 42 * Simba configuration space registers. 43 */ 44 #define PCI_BCNF_SECSTATUS 0x1e /* secondary status */ 45 46 /* 47 * Simba device specific registers. 48 */ 49 #define PCI_BCNF_MATER_RETRY_LIMIT 0xc0 /* primary master retry limit */ 50 #define PCI_BCNF_DMA_AFSR 0xc8 /* dma afsr */ 51 #define PCI_BCNF_DMA_AFAR 0xd0 /* dma afar */ 52 #define PCI_BCNF_PIOTGT_RTY_LIMIT 0xd8 /* pio target retry limit */ 53 #define PCI_BCNF_PIOTGT_LATE_TIMER 0xd9 /* pio target retry limit */ 54 #define PCI_BCNF_DMATGT_RTY_LIMIT 0xda /* dma target retry limit */ 55 #define PCI_BCNF_DMATGT_LATE_TIMER 0xdb /* dma target retry limit */ 56 #define PCI_BCNF_TGT_RETRY_LIMIT 0xdc /* primary master retry limit */ 57 #define PCI_BCNF_SECBRIDGE_CTL 0xdd /* secondary bridge control */ 58 #define PCI_BCNF_ADDR_MAP 0xdf /* address map */ 59 60 /* 61 * Psycho compatible registers. 62 */ 63 #define PCI_BCNF_CTL_STAT 0xe0 /* control-status */ 64 #define PCI_BCNF_PIO_AFSR 0xe8 /* pio afsr */ 65 #define PCI_BCNF_PIO_AFAR 0xf0 /* pio afar */ 66 67 /* 68 * Simba device specific registers. 69 */ 70 #define PCI_BCNF_DIAGNOSTICS 0xf8 /* diagnostics */ 71 72 73 /* 74 * primary/secondary timer reg mask(addrs = 0x0d/0x1b). 75 */ 76 #define PCI_LATENCY_TMR_LO 0x7 /* read only part, 0x0 */ 77 #define PCI_LATENCY_TMR_HI 0xf8 /* programable part */ 78 79 /* 80 * PCI secondary status register bits. 81 * All bit definitions are the same as primary status register, 82 * but the meaning of bit 14 relates to secondary bus. 83 */ 84 85 86 /* 87 * Secondary control bit defines(addrs = 0xdd). 88 */ 89 #define PCI_SEC_CNTL_PIO_PREF 0x1 /* prefetch dma reads as pio */ 90 #define PCI_SEC_CNTL_CONVT_MRM 0x2 /* convert mem multiple read */ 91 92 /* 93 * Psycho ctrl/status reg bit defines(addrs = 0xe0). 94 */ 95 #define PCI_PSYCHO_SLOT_ENAM_MASK 0xf /* slot arbiter enable mask */ 96 #define PCI_PSYCHO_SEC_ERRINIT_ENAB 0x100 /* 1=forward SERR to primary */ 97 #define PCI_PSYCHO_WAKEUP_ENAB 0x200 /* not used, reads as 0 */ 98 #define PCI_PSYCHO_SBH_INT_ENAB 0x400 /* not used, reads as 0 */ 99 #define PCI_PSYCHO_SLOT_PRIORITY 0xf0000 /* slot arb priority mask */ 100 #define PCI_PSYCHO_CPU_PRIORITY 0x100000 /* pio arb priority (simba) */ 101 #define PCI_PSYCHO_PBUS_PARK_ENAB 0x200000 /* pci bus parking enable */ 102 #define PCI_PSYCHO_INTER_ARB_ENAB 0x100000000 /* enable internal arb */ 103 #define PCI_PSYCHO_PCI_SPEED 0x200000000 /* not used, reads as 0 */ 104 #define PCI_PSYCHO_PCI_SYS_ERROR 0x800000000 /* set, if err on 2ndary */ 105 #define PCI_PSYCHO_PCI_SBH_ERROR 0x1000000000 /* not used, reads as 0 */ 106 107 /* 108 * Psycho AFSR reg bit defines(addrs = 0xe8). 109 */ 110 #define PCI_PSYCHO_ERR_NUM 0xff /* error index number */ 111 #define PCI_PSYCHO_MID_MASK (0x1f<<25) /* mid mask, reads 0 */ 112 #define PCI_PSYCHO_BLK (1<<31) /* block, reads 0 */ 113 #define PCI_PSYCHO_BYTE_MASK (0xffff<<32) /* byte mask, reads 0 */ 114 #define PCI_PSYCHO_SEC_APERR (1<<54) /* 2ndary adr par err */ 115 #define PCI_PSYCHO_PRI_APERR (1<<55) /* pri addr par err */ 116 #define PCI_PSYCHO_SEC_PERR (1<<56) /* 2nd data par err */ 117 #define PCI_PSYCHO_SEC_RTRY_ERR (1<<57) /* 2nd retry err */ 118 #define PCI_PSYCHO_SEC_TA_ERR (1<<58) /* 2nd tgt abort err */ 119 #define PCI_PSYCHO_SEC_MA_ERR (1<<59) /* 2nd mstr abort err */ 120 #define PCI_PSYCHO_PRI_PERR (1<<60) /* pri data par error */ 121 #define PCI_PSYCHO_PRI_RTRY_ERR (1<<61) /* pri retry error */ 122 #define PCI_PSYCHO_PRI_TA_ERR (1<<62) /* mstr tgt abort err */ 123 #define PCI_PSYCHO_PRI_MA_ERR (1<<63) /* mstr mstr abrt err */ 124 125 126 /* 127 * notice: In Simba, AFAR will log statring address of transaction with error 128 * The byte offset will be logged in [7:0] of AFSR. 129 */ 130 131 /* 132 * Diagnostics reg bit defines(size=d word)(addrs = 0xf8). 133 */ 134 #define PCI_DIAG_IDMA_WDATA_PAR 0x1 /* invert dma wr data parity */ 135 #define PCI_DIAG_IDMA_RDATA_PAR 0x2 /* invert dma rd data parity */ 136 #define PCI_DIAG_IDMA_ADDR_PAR 0x4 /* invert dma addr parity */ 137 #define PCI_DIAG_IPIO_WDATA_PAR 0x10 /* invert pio wr data parity */ 138 #define PCI_DIAG_IPIO_RDATA_PAR 0x20 /* invert pio rd data parity */ 139 #define PCI_DIAG_IPIO_ADDR_PAR 0x40 /* invert pio addr parity */ 140 141 /* 142 * usefull defines. 143 */ 144 #define PCI_UNLIMITED_RETRY 0x0 /* unlimitted retry */ 145 #define PCI_UNLIMITED_LATENCY 0x0 /* unlimitted latency */ 146 147 /* 148 * vendor & device id for simba. 149 */ 150 #define PCI_SIMBA_VENID 0x108e /* vendor id for simba */ 151 #define PCI_SIMBA_DEVID 0x5000 /* device id for simba */ 152 153 /* 154 * programming interface for simba. 155 */ 156 #define PCI_SIMBA_PRI 0x0 /* prog interface for simba */ 157 158 /* 159 * master/secondary latency timer value. 160 */ 161 #define PCI_LATENCY_TIMER_VAL 0x28 /* timer value for simba */ 162 163 /* 164 * primary bus number for simba. 165 */ 166 #define PCI_BCNF_PRIBUS_NUM 0x0 /* primary bus # for simba */ 167 168 /* 169 * secondary bus number for simba. 170 */ 171 #define PCI_BCNF_SECBUS_NUM_ONE 0x1 /* secondary bus number one */ 172 #define PCI_BCNF_SECBUS_NUM_TWO 0x2 /* secondary bus number two */ 173 174 175 #ifdef __cplusplus 176 } 177 #endif 178 179 #endif /* _SYS_PCI_SIMBA_H */ 180