1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_PBM_H 28 #define _SYS_PCI_PBM_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/types.h> 33 #include <sys/dditypes.h> 34 #include <sys/ontrap.h> 35 #include <sys/callb.h> 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /* 42 * The following structure represents the pci configuration header 43 * for a psycho or schizo PBM. 44 */ 45 typedef struct config_header config_header_t; 46 struct config_header { 47 volatile uint16_t ch_vendor_id; 48 volatile uint16_t ch_device_id; 49 volatile uint16_t ch_command_reg; 50 volatile uint16_t ch_status_reg; 51 volatile uint8_t ch_revision_id_reg; 52 volatile uint8_t ch_programming_if_code_reg; 53 volatile uint8_t ch_sub_class_reg; 54 volatile uint8_t ch_base_class_reg; 55 volatile uint8_t ch_cache_line_size_reg; 56 volatile uint8_t ch_latency_timer_reg; 57 volatile uint8_t ch_header_type_reg; 58 }; 59 60 typedef enum { PBM_SPEED_33MHZ, PBM_SPEED_66MHZ } pbm_speed_t; 61 62 /* 63 * Bit fields of ch_status_reg for cmn_err's %b 64 */ 65 #define PCI_STATUS_BITS "\020\ 66 \11signaled-parity-error\ 67 \14signaled-target-abort\ 68 \15received-target-abort\ 69 \16received-master-abort\ 70 \17signaled-system-error\ 71 \20detected-parity-error" 72 73 /* 74 * pbm block soft state structure: 75 * 76 * Each pci node has its own private pbm block structure. 77 */ 78 struct pbm { 79 pci_t *pbm_pci_p; /* link back to pci soft state */ 80 pbm_speed_t pbm_speed; /* PCI bus speed (33 or 66 Mhz) */ 81 82 /* 83 * PBM control and error registers: 84 */ 85 volatile uint64_t *pbm_ctrl_reg; 86 volatile uint64_t *pbm_async_flt_status_reg; 87 volatile uint64_t *pbm_async_flt_addr_reg; 88 volatile uint64_t *pbm_diag_reg; 89 volatile uint64_t *pbm_estar_reg; 90 volatile uint64_t *pbm_pcix_err_stat_reg; 91 volatile uint64_t *pbm_pci_ped_ctrl; 92 volatile uint64_t *pbm_upper_retry_counter_reg; /* for xmits */ 93 94 /* 95 * PCI configuration header block for the PBM: 96 */ 97 config_header_t *pbm_config_header; 98 99 /* 100 * Memory address range on this PBM used to determine DMA on this pbm 101 */ 102 iopfn_t pbm_base_pfn; 103 iopfn_t pbm_last_pfn; 104 105 /* 106 * pbm Interrupt Mapping Register save area 107 */ 108 uint64_t pbm_imr_save; 109 110 /* To save CDMA interrupt state across CPR */ 111 uint64_t pbm_cdma_imr_save; 112 113 /* 114 * pbm error interrupt priority: 115 */ 116 ddi_iblock_cookie_t pbm_iblock_cookie; 117 118 /* 119 * Consistent Mode DMA Sync 120 */ 121 uint64_t pbm_sync_reg_pa; /* pending reg for xmits/tomatillo */ 122 ib_ino_t pbm_sync_ino; 123 124 volatile uint32_t pbm_cdma_flag; 125 126 /* 127 * DMA sync lock to serialize access to sync hardware. 128 * Used for schizo (>= 2.3) and xmits. Tomatillo does not require 129 * serialization. 130 */ 131 kmutex_t pbm_sync_mutex; 132 133 /* 134 * support for ddi_poke: 135 */ 136 on_trap_data_t *pbm_ontrap_data; 137 138 kmutex_t pbm_pokefault_mutex; 139 140 /* 141 * Support for cautious IO accesses 142 */ 143 ddi_acc_handle_t pbm_excl_handle; 144 145 /* 146 * Support for PCI bus quiesce/unquiesce 147 */ 148 uint64_t pbm_saved_ctrl_reg; 149 uint_t pbm_quiesce_count; 150 callb_id_t pbm_panic_cb_id; 151 callb_id_t pbm_debug_cb_id; 152 uint64_t pbm_anychild_cfgpa; 153 154 /* 155 * Sun Fire 15k PIO limiting semaphore 156 */ 157 uint32_t pbm_pio_limit; 158 volatile uint32_t pbm_pio_counter; 159 160 #define PBM_NAMESTR_BUFLEN 64 161 /* driver name & instance */ 162 char pbm_nameinst_str[PBM_NAMESTR_BUFLEN]; 163 164 /* nodename & node_addr */ 165 char *pbm_nameaddr_str; 166 }; 167 168 /* 169 * forward declarations (object creation and destruction): 170 */ 171 172 extern void pbm_create(pci_t *pci_p); 173 extern void pbm_destroy(pci_t *pci_p); 174 extern void pbm_configure(pbm_t *pbm_p); 175 extern void pbm_clear_error(pbm_t *pbm_p); 176 extern void pbm_enable_intr(pbm_t *pbm_p); 177 extern void pbm_suspend(pbm_t *pbm_p); 178 extern void pbm_resume(pbm_t *pbm_p); 179 extern void pbm_intr_dist(void *arg); 180 extern int pbm_register_intr(pbm_t *pbm_p); 181 extern int pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena, 182 pbm_errstate_t *pbm_err_p); 183 184 #ifdef __cplusplus 185 } 186 #endif 187 188 #endif /* _SYS_PCI_PBM_H */ 189