1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_DB21554_CTRL_H 28 #define _SYS_DB21554_CTRL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* definitions for device state */ 37 #define DB_SECONDARY_NEXUS 0x80000000 /* secondary towards host */ 38 #define DB_PRIMARY_NEXUS 0x40000000 /* primary towards host */ 39 #define DB_ATTACHED 0x00000001 /* driver attached */ 40 #define DB_SUSPENDED 0x00100000 41 #define DB_DEBUG_MODE_ON 0x01000000 42 43 #define DB_PCI_CONF_RNUMBER 0 44 #define DB_PCI_CONF_OFFSET 0 45 #define DB_CSR_MEMBAR_RNUMBER 1 46 #define DB_CSR_MEM_OFFSET 0 47 #define DB_CSR_SIZE 0x1000 /* 4K CSR space */ 48 #define DB_CSR_IOBAR_RNUMBER 2 49 #define DB_CSR_IO_OFFSET 0 50 #define DB_PCI_TIMEOUT 10000 /* 10 ms */ 51 #define DB_PCI_WAIT_MS 0 52 #define DB_CONF_FAILURE -1 53 54 #define DB_PIF_SECONDARY_TO_HOST 0x80 55 #define DB_PIF_PRIMARY_TO_HOST 0x40 56 57 /* 58 * The following definition could have been inherited from sys/pci/pci_var.h 59 * but that runs into including many other dependent files which are 60 * host-pci nexus specific. So declaring our own bus_range structure makes 61 * it lot easier and simpler. This is ok as bus-range format is in the 62 * pci bindings. 63 */ 64 typedef struct bus_range { 65 uint32_t lo; 66 uint32_t hi; 67 } db_pci_bus_range_t; 68 69 /* 70 * the following definition is used to save the state of all PCI children 71 * under us. 72 */ 73 typedef struct db_cfg_state { 74 dev_info_t *dip; 75 uchar_t cache_line_size; 76 uchar_t latency_timer; 77 uchar_t header_type; 78 uchar_t sec_latency_timer; 79 ushort_t command; 80 ushort_t bridge_control; 81 } db_cfg_state_t; 82 83 /* the main control structure of our device */ 84 typedef struct db_ctrl { 85 dev_info_t *dip; 86 uint32_t dev_state; /* device state */ 87 caddr_t csr_mem; /* pointer to CSR map in memory space */ 88 caddr_t csr_io; /* pointer to CSR map in IO space */ 89 caddr_t conf_io; /* pointer to Conf indirect map */ 90 91 /* our bus range information */ 92 db_pci_bus_range_t range; 93 94 /* any device tuning parameters here. */ 95 uint16_t p_command; 96 uint16_t s_command; 97 int8_t p_latency_timer; 98 int8_t p_cache_line_size; 99 int8_t s_latency_timer; 100 int8_t s_cache_line_size; 101 int8_t p_pwrite_threshold; 102 int8_t s_pwrite_threshold; 103 int8_t p_dread_threshold; 104 int8_t s_dread_threshold; 105 int8_t delayed_trans_order; 106 int8_t serr_fwd_enable; 107 108 /* for child initialization */ 109 uint8_t latency_timer; 110 uint8_t cache_line_size; 111 112 /* error holders */ 113 uint32_t db_pci_err_count; /* indirect cycle timeout count */ 114 #ifdef DEBUG 115 uint32_t db_pci_max_wait_count; /* indirect cycle wait count */ 116 #endif 117 /* cpr related. */ 118 uint_t config_state_index; 119 db_cfg_state_t *db_config_state_p; 120 121 /* all map handles below */ 122 ddi_acc_handle_t csr_mem_handle; /* CSR memory handle */ 123 ddi_acc_handle_t csr_io_handle; /* CSR IO handle */ 124 ddi_acc_handle_t conf_handle; /* config space handle */ 125 ddi_iblock_cookie_t i_block_cookie; /* interrupt cookie */ 126 kmutex_t db_busown; /* bus config own mutex */ 127 kmutex_t db_mutex; 128 uint_t db_soft_state; 129 #define DB_SOFT_STATE_CLOSED 0x00 130 #define DB_SOFT_STATE_OPEN 0x01 131 #define DB_SOFT_STATE_OPEN_EXCL 0x02 132 int fm_cap; 133 ddi_iblock_cookie_t fm_ibc; 134 }db_ctrl_t; 135 136 typedef struct db_acc_cfg_addr { 137 uchar_t c_busnum; /* bus number */ 138 uchar_t c_devnum; /* device number */ 139 uchar_t c_funcnum; /* function number */ 140 uchar_t c_fill; /* reserve field */ 141 } db_acc_cfg_addr_t; 142 143 typedef struct db_acc_pvt { 144 db_acc_cfg_addr_t dev_addr; /* pci device address */ 145 uint32_t *addr; /* upstream/downstream config addr */ 146 uint32_t *data; /* upstream/downstream config data */ 147 uint8_t *bus_own; /* reg to check if bus owned */ 148 uint8_t *bus_release; /* reg to check if bus released */ 149 uint8_t mask; /* bitmask for upstream/downstream */ 150 ushort_t access_mode; /* access through IO or Config */ 151 db_ctrl_t *dbp; 152 ddi_acc_handle_t handle; /* handle for bus access DDI calls */ 153 } db_acc_pvt_t; 154 155 /* We can use the following modes for generating indirect PCI transcations */ 156 #define DB_IO_MAP_DIRECT 1 /* memory mapped IO */ 157 #define DB_IO_MAP_INDIRECT 2 /* indirect map IO */ 158 #define DB_CONF_MAP_INDIRECT_CONF 4 /* access config via config regs */ 159 #define DB_CONF_MAP_INDIRECT_IO 8 /* access config via IO regs */ 160 #define DB_PCI_CONF_CYCLE_TYPE0 0x100 /* type 0 conf cycle */ 161 #define DB_PCI_CONF_CYCLE_TYPE1 0x200 /* type 1 conf cycle */ 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif /* _SYS_DB21554_CTRL_H */ 168