xref: /titanic_50/usr/src/uts/sun4u/sys/pci/db21554_csr.h (revision c5c4113dfcabb1eed3d4bdf7609de5170027a794)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1999 by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #ifndef	_SYS_DB21554_CSR_H
28 #define	_SYS_DB21554_CSR_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 /* CSR Register Offset  definitions */
37 #define	DB_CSR_DS_CONF_ADDR		0x000	/* DownStream config addres */
38 #define	DB_CSR_DS_CONF_DATA		0x004	/* downstream config data */
39 #define	DB_CSR_US_CONF_ADDR		0x008	/* UpStream config address */
40 #define	DB_CSR_US_CONF_DATA		0x00C	/* UpStream config data */
41 #define	DB_CSR_CONF_OWN			0x010   /* config own bits - word reg */
42 #define	DB_CSR8_DS_CONF_OWN		0x010   /* config own bits - byte reg */
43 #define	DB_CSR8_US_CONF_OWN		0x011   /* config own bits - byte reg */
44 #define	DB_CSR_CONF_CSR			0x012   /* config ctrl/status - word */
45 #define	DB_CSR8_DS_CONF_CSR		0x012   /* DS config csr - byte */
46 #define	DB_CSR8_US_CONF_CSR		0x013   /* US config csr - byte */
47 #define	DB_CSR_DS_IO_ADDR		0x014	/* DS io address */
48 #define	DB_CSR_DS_IO_DATA		0x018	/* DS io data */
49 #define	DB_CSR_US_IO_ADDR		0x01C	/* US io address */
50 #define	DB_CSR_US_IO_DATA		0x020	/* US io data */
51 #define	DB_CSR_IO_OWN			0x024	/* IO Own bits - word reg */
52 #define	DB_CSR8_DS_IO_OWN		0x024	/* DS IO Own bits - byte reg */
53 #define	DB_CSR8_US_IO_OWN		0x025	/* DS IO Own bits - byte reg */
54 #define	DB_CSR_IO_CSR			0x026	/* IO csr  - word reg */
55 #define	DB_CSR8_DS_IO_CSR		0x026	/* DS IO csr - byte reg */
56 #define	DB_CSR8_US_IO_CSR		0x027	/* US IO csr - byte reg */
57 #define	DB_CSR_LUT_OFFSET		0x028	/* Lookup Table offset */
58 #define	DB_CSR_LUT_DATA			0x02C	/* LookUp Table Data */
59 
60 #define	DB_CSR_I2O_OB_PL_STATUS		0x030	/* I2O outbound postlist stat */
61 #define	DB_CSR_I2O_OB_PL_INTR_MASK	0x034	/* I2O outbound postlistImask */
62 #define	DB_CSR_I2O_IB_PL_STATUS		0x038	/* I2O inbound postlist stat */
63 #define	DB_CSR_I2O_IB_PL_INTR_MASK	0x03C	/* I2O inbound postlist Imask */
64 
65 #define	DB_CSR_CHIP_STATUS_CSR		0x082	/* chip status CSR */
66 #define	DB_CSR_CHIP_SET_IRQ_MASK	0x084	/* chip set IRQ mask */
67 #define	DB_CSR_CHIP_CLR_IRQ_MASK	0x086	/* chip clear IRQ mask */
68 #define	DB_CSR_US_PAGEBOUND_IRQ0	0x088	/* US page boundary IRQ 0 */
69 #define	DB_CSR_US_PAGEBOUND_IRQ1	0x08C	/* US page boundary IRQ 1 */
70 #define	DB_CSR_US_PAGEBOUND_IRQ_MASK0	0x090	/* US page boundary IRQ mask0 */
71 #define	DB_CSR_US_PAGEBOUND_IRQ_MASK1	0x094	/* US page boundary IRQ mask1 */
72 #define	DB_CSR_PRIM_CLR_IRQ		0x098	/* Primary Clear IRQ */
73 #define	DB_CSR_SEC_CLR_IRQ		0x09A	/* Secondary Clear IRQ */
74 #define	DB_CSR_PRIM_SET_IRQ		0x09C	/* Primary Set IRQ */
75 #define	DB_CSR_SEC_SET_IRQ		0x09E	/* Secondary Set IRQ */
76 #define	DB_CSR_PRIM_CLR_IRQ_MASK	0x0A0	/* Primary Clear IRQ Mask */
77 #define	DB_CSR_SEC_CLR_IRQ_MASK		0x0A2	/* Secondary Clear IRQ Mask */
78 #define	DB_CSR_PRIM_SET_IRQ_MASK	0x0A4	/* Primary Set IRQ Mask */
79 #define	DB_CSR_SEC_SET_IRQ_MASK		0x0A6	/* Secondary Set IRQ Mask */
80 #define	DB_CSR_SCRATCHPAD_0		0x0A8	/* Scratchpad 0 */
81 #define	DB_CSR_SCRATCHPAD_1		0x0AC	/* Scratchpad 1 */
82 #define	DB_CSR_SCRATCHPAD_2		0x0B0	/* Scratchpad 2 */
83 #define	DB_CSR_SCRATCHPAD_3		0x0B4	/* Scratchpad 3 */
84 #define	DB_CSR_SCRATCHPAD_4		0x0B8	/* Scratchpad 4 */
85 #define	DB_CSR_SCRATCHPAD_5		0x0BC	/* Scratchpad 5 */
86 #define	DB_CSR_SCRATCHPAD_6		0x0C0	/* Scratchpad 6 */
87 #define	DB_CSR_SCRATCHPAD_7		0x0C4	/* Scratchpad 7 */
88 #define	DB_CSR_ROM_SETUP		0x0C8	/* ROM setup register */
89 #define	DB_CSR_ROM_DATA			0x0CA	/* ROM Data register */
90 #define	DB_CSR_ROM_ADDR			0x0CC	/* ROM Address register */
91 #define	DB_CSR_ROM_CTRL			0x0CF	/* ROM control */
92 #define	DB_CSR_US_MEM2_LUT		0x100	/* US Memory 2 Lookup Table */
93 
94 /* Configuration Own Bits register definition */
95 #define	DS_IO_OWN			0x0001
96 #define	US_IO_OWN			0x0100
97 /* the following is a 8bit register bit definitions for IO own */
98 #define	DS8_IO_OWN			0x01
99 #define	US8_IO_OWN			0x01
100 
101 /* IO control status register bits: Register offset 0x26-27 */
102 #define	IO_DS_OWN_STAT 0x0001  /* downstream config own status */
103 #define	IO_DS_ENABLE   0x0002  /* enable downstream config cycles */
104 #define	IO_US_OWN_STAT 0x0100  /* upstream config own status */
105 #define	IO_US_ENABLE   0x0200  /* enable upstream config cycles */
106 
107 typedef volatile struct us_mem2_tbl {
108 	uchar_t		unimpl[256];		/* currently unimplemented */
109 } us_mem2_tbl_t;
110 
111 #ifdef	__cplusplus
112 }
113 #endif
114 
115 #endif	/* _SYS_DB21554_CSR_H */
116