1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_CHEETAHREGS_H 28 #define _SYS_CHEETAHREGS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/machasi.h> 33 #ifdef _KERNEL 34 #include <sys/fpras.h> 35 #endif /* _KERNEL */ 36 37 /* 38 * This file is cpu dependent. 39 */ 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * Definitions of UltraSparc III cpu implementations as specified 47 * in version register 48 */ 49 #define CHEETAH_IMPL 0x14 50 #define IS_CHEETAH(impl) ((impl) == CHEETAH_IMPL) 51 #define CHEETAH_MAJOR_VERSION(rev) (((rev) >> 4) & 0xf) 52 #define CHEETAH_MINOR_VERSION(rev) ((rev) & 0xf) 53 54 /* 55 * Definitions of UltraSPARC III+ cpu implementation as specified 56 * in version register 57 */ 58 #define CHEETAH_PLUS_IMPL 0x15 59 #define IS_CHEETAH_PLUS(impl) ((impl) == CHEETAH_PLUS_IMPL) 60 #define CHEETAH_PLUS_MAJOR_VERSION(rev) CHEETAH_MAJOR_VERSION(rev) 61 #define CHEETAH_PLUS_MINOR_VERSION(rev) CHEETAH_MINOR_VERSION(rev) 62 63 /* 64 * Definitions of UltraSPARC IIIi cpu implementation as specified 65 * in version register. Jalapeno major and minor rev's are in 66 * the same location and are the same size as Cheetah/Cheetah+. 67 */ 68 #define JALAPENO_IMPL 0x16 69 #define IS_JALAPENO(impl) ((impl) == JALAPENO_IMPL) 70 #define JALAPENO_MAJOR_VERSION(rev) CHEETAH_MAJOR_VERSION(rev) 71 #define JALAPENO_MINOR_VERSION(rev) CHEETAH_MINOR_VERSION(rev) 72 73 /* 74 * Definitions of UltraSPARC IV cpu implementation as specified 75 * in version register. Jaguar major and minor rev's are in 76 * the same location and are the same size as Cheetah/Cheetah+. 77 */ 78 #define JAGUAR_IMPL 0x18 79 #define IS_JAGUAR(impl) ((impl) == JAGUAR_IMPL) 80 #define JAGUAR_MAJOR_VERSION(rev) CHEETAH_MAJOR_VERSION(rev) 81 #define JAGUAR_MINOR_VERSION(rev) CHEETAH_MINOR_VERSION(rev) 82 83 /* 84 * Definitions of UltraSPARC IIIi+ cpu implementation as specified 85 * in version register. Serrano major and minor rev's are in 86 * the same location and are the same size as Cheetah/Cheetah+. 87 */ 88 #define SERRANO_IMPL 0x22 89 #define IS_SERRANO(impl) ((impl) == SERRANO_IMPL) 90 #define SERRANO_MAJOR_VERSION(rev) CHEETAH_MAJOR_VERSION(rev) 91 #define SERRANO_MINOR_VERSION(rev) CHEETAH_MINOR_VERSION(rev) 92 93 /* 94 * Definitions of UltraSPARC IV+ cpu implementation as specified 95 * in version register. Panther major and minor rev's are in 96 * the same location and are the same size as Cheetah/Cheetah+. 97 */ 98 #define PANTHER_IMPL 0x19 99 #define IS_PANTHER(impl) ((impl) == PANTHER_IMPL) 100 #define PANTHER_MAJOR_VERSION(rev) CHEETAH_MAJOR_VERSION(rev) 101 #define PANTHER_MINOR_VERSION(rev) CHEETAH_MINOR_VERSION(rev) 102 103 #define CPU_IMPL_IS_CMP(impl) (IS_JAGUAR(impl) || IS_PANTHER(impl)) 104 105 /* 106 * Cheetah includes the process info in its mask to make things 107 * more difficult. The process is the low bit of the major mask, 108 * so to convert to the netlist major: 109 * netlist_major = ((mask_major >> 1) + 1) 110 */ 111 #define REMAP_CHEETAH_MASK(x) (((((x) >> 1) + 0x10) & 0xf0) | ((x) & 0xf)) 112 113 #ifdef _ASM 114 /* 115 * assembler doesn't understand the 'ull' suffix for C constants so 116 * use the inttypes.h macros and undefine them here for assembly code 117 */ 118 #undef INT64_C 119 #undef UINT64_C 120 #define INT64_C(x) (x) 121 #define UINT64_C(x) (x) 122 #endif /* _ASM */ 123 124 /* 125 * DCU Control Register 126 * 127 * +------+----+----+----+----+----+-----+-----+----+----+----+ 128 * | Resv | CP | CV | ME | RE | PE | HPE | SPE | SL | WE | PM | 129 * +------+----+----+----+----+----+-----+-----+----+----+----+ 130 * 63:50 49 48 47 46 45 44 43 42 41 40:33 131 * 132 * +----+----+----+----+----+----------+-----+----+----+----+---+ 133 * | VM | PR | PW | VR | VW | Reserved | WIH | DM | IM | DC | IC| 134 * +----+----+----+----+----+----------+-----+----+----+----+---+ 135 * 32:25 24 23 22 21 20:5 4 3 2 1 0 136 */ 137 138 #define ASI_DCU ASI_LSU /* same as spitfire ASI_LSU 0x45 */ 139 #define DCU_IC INT64_C(0x0000000000000001) /* icache enable */ 140 #define DCU_DC INT64_C(0x0000000000000002) /* dcache enable */ 141 #define DCU_IM INT64_C(0x0000000000000004) /* immu enable */ 142 #define DCU_DM INT64_C(0x0000000000000008) /* dmmu enable */ 143 #define DCU_WIH INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */ 144 #define DCU_VW INT64_C(0x0000000000200000) /* virt watchpoint write enable */ 145 #define DCU_VR INT64_C(0x0000000000400000) /* virt watchpoint read enable */ 146 #define DCU_PW INT64_C(0x0000000000800000) /* phys watchpoint write enable */ 147 #define DCU_PR INT64_C(0x0000000001000000) /* phys watchpoint read enable */ 148 #define DCU_VM INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */ 149 #define DCU_PM INT64_C(0x000001FE00000000) /* phys watchpoint write mask */ 150 #define DCU_WE INT64_C(0x0000020000000000) /* write cache enable */ 151 #define DCU_SL INT64_C(0x0000040000000000) /* second load control */ 152 #define DCU_SPE INT64_C(0x0000080000000000) /* software prefetch enable */ 153 #define DCU_HPE INT64_C(0x0000100000000000) /* hardware prefetch enable */ 154 #define DCU_PE INT64_C(0x0000200000000000) /* prefetch enable */ 155 #define DCU_RE INT64_C(0x0000400000000000) /* RAW bypass enable */ 156 #define DCU_ME INT64_C(0x0000800000000000) /* noncache store merging enable */ 157 #define DCU_CV INT64_C(0x0001000000000000) /* virt cacheability when DM=0 */ 158 #define DCU_CP INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0 */ 159 #define DCU_CACHE (DCU_IC|DCU_DC|DCU_WE|DCU_SPE|DCU_HPE|DCU_PE) 160 161 /* 162 * bit shifts for the prefetch enable bit 163 */ 164 #define DCU_PE_SHIFT 45 165 166 /* 167 * Safari Configuration Register 168 */ 169 #define ASI_SAFARI_CONFIG ASI_UPA_CONFIG /* Safari Config Reg, 0x4A */ 170 #define SAFARI_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */ 171 #define SAFARI_CONFIG_ECLK_1_DIV 1 /* clock divisor: 1 */ 172 #define SAFARI_CONFIG_ECLK_2 INT64_C(0x0000000040000000) /* 1/2 clock */ 173 #define SAFARI_CONFIG_ECLK_2_DIV 2 /* clock divisor: 2 */ 174 #define SAFARI_CONFIG_ECLK_32 INT64_C(0x0000000080000000) /* 1/32 clock */ 175 #define SAFARI_CONFIG_ECLK_32_DIV 32 /* clock divisor: 32 */ 176 #define SAFARI_CONFIG_ECLK_MASK (SAFARI_CONFIG_ECLK_32 | SAFARI_CONFIG_ECLK_2) 177 178 #if defined(JALAPENO) || defined(SERRANO) 179 /* 180 * JBUS Configuration Register 181 */ 182 #define ASI_JBUS_CONFIG ASI_UPA_CONFIG /* JBUS Config Reg, 0x4A */ 183 #define JBUS_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */ 184 #define JBUS_CONFIG_ECLK_1_DIV 1 /* clock divisor: 1 */ 185 #define JBUS_CONFIG_ECLK_2 INT64_C(0x0000000000002000) /* 1/2 clock */ 186 #define JBUS_CONFIG_ECLK_2_DIV 2 /* clock divisor: 2 */ 187 #define JBUS_CONFIG_ECLK_32 INT64_C(0x0000000000004000) /* 1/32 clock */ 188 #define JBUS_CONFIG_ECLK_32_DIV 32 /* clock divisor: 32 */ 189 #define JBUS_CONFIG_ECLK_MASK (JBUS_CONFIG_ECLK_32 | JBUS_CONFIG_ECLK_2) 190 #define JBUS_CONFIG_ECLK_SHIFT 13 191 192 /* 193 * Jalapeno/Serrano MCU control registers and ASI 194 */ 195 #define ASI_MCU_CTRL 0x72 /* MCU Control Reg ASI */ 196 #define JP_MCU_FSM_MASK INT64_C(0x0000000006000000) /* 26..25 */ 197 #define JP_MCU_FSM_SHIFT 25 198 #endif /* JALAPENO || SERRANO */ 199 200 #if defined(SERRANO) 201 #define ASI_MCU_AFAR2_VA 0x18 /* captures FRC/FRU addr */ 202 #endif /* SERRANO */ 203 204 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 205 /* 206 * Tomatillo Estar control registers (for JP Errataum 85) 207 */ 208 #define JBUS_SLAVE_T_PORT_BIT 48 209 #define TOM_HIGH_PA 0x400 /* Hi 32 bit of Tom reg PA */ 210 #define M_T_ESTAR_CTRL_PA 0x0f410050 /* M T estar PA */ 211 #define S_T_ESTAR_CTRL_PA 0x0e410050 /* S T estar PA */ 212 #define M_T_J_CHNG_INIT_PA 0x0f410058 /* Master T estar PA */ 213 #define TOM_ESTAR_ELCK_MASK 0x23 /* bit 5,1,0 */ 214 #define TOM_FULL_SPEED 0x1 215 #define TOM_HALF_SPEED 0x2 216 #define TOM_SLOW_SPEED 0x20 217 #define TOM_TRIGGER_MASK 0x18 218 #define TOM_TRIGGER 0x10 219 220 #endif /* JALAPENO && JALAPENO_ERRATA_85 */ 221 222 223 /* 224 * Miscellaneous ASI definitions not in machasi.h 225 */ 226 #define ASI_DC_UTAG 0x43 /* Dcache Microtag Fields */ 227 #define ASI_DC_SNP_TAG 0x44 /* Dcache Snoop Tag Fields */ 228 #define ASI_IC_SNP_TAG 0x68 /* Icache Snoop Tag Fields */ 229 #define ASI_IPB_DATA 0x69 /* Instruction Prefetch Buffer Data */ 230 #define ASI_IPB_TAG 0x6A /* Instruction Prefetch Buffer Tag */ 231 #define ASI_MC_DECODE 0x72 /* Memory Address Decoding Registers */ 232 #define ASI_EC_CFG_TIMING 0x73 /* Jaguar shared Ecache Control Reg */ 233 #define ASI_EC_DATA 0x74 /* Ecache Data Staging Registers */ 234 #define ASI_EC_CTRL 0x75 /* Ecache Control Register */ 235 #define ASI_PC_STATUS_DATA 0x30 /* Pcache Status Data Access */ 236 #define ASI_PC_DATA 0x31 /* Pcache Diagnostic Data Register */ 237 #define ASI_PC_TAG 0x32 /* Pcache Virtual Tag/Valid Field */ 238 #define ASI_PC_SNP_TAG 0x33 /* Pcache Snoop Tag Register */ 239 #define ASI_L2_DATA 0x6B /* L2 cache Data Diagnostic Access */ 240 #define ASI_L2_TAG 0x6C /* L2 cache Tag Diagnostic Access */ 241 242 /* 243 * Bits of Cheetah Asynchronous Fault Status Register 244 * 245 * +---+--+----+----+----+----+---+---+---+---+--+---- 246 * |rsv|ME|PRIV|PERR|IERR|ISAP|EMC|EMU|IVC|IVU|TO|BERR 247 * +---+--+----+----+----+----+---+---+---+---+--+---- 248 * 63:54 53 52 51 50 49 48 47 46 45 44 43 249 * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+ 250 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|rsv|M_SYND|rsv||E_SYND| 251 * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+ 252 * 42 41 40 39 38 37 36 35 34 33 32:20 19:16 15:9 8:0 253 * 254 */ 255 #if defined(CHEETAH_PLUS) 256 /* 257 * Bits of Cheetah+ Asynchronous Fault Status Register 258 * 259 * +------------------+---------------------------- 260 * |rsv|TUE_SH|IMC|IMU|DTO|DBERR|THCE|TSCE|TUE|DUE| 261 * +------------------+---------------------------- . . . 262 * 63 62 61 60 59 58 57 56 55 54 263 * 264 * Note that bits 60-62 are only implemented in Panther (reserved 265 * in Cheetah+ and Jaguar. Also, bit 56 is reserved in Panther instead 266 * of TSCE since those errors are HW corrected in Panther. 267 */ 268 #define C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE */ 269 #define C_AFSR_IMC INT64_C(0x2000000000000000) /* intr vector MTAG ECC */ 270 #define C_AFSR_IMU INT64_C(0x1000000000000000) /* intr vector MTAG ECC */ 271 #define C_AFSR_DTO INT64_C(0x0800000000000000) /* disrupting TO error */ 272 #define C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */ 273 #define C_AFSR_THCE INT64_C(0x0200000000000000) /* h/w correctable E$ tag err */ 274 #define C_AFSR_TSCE INT64_C(0x0100000000000000) /* s/w correctable E$ tag err */ 275 #define C_AFSR_TUE INT64_C(0x0080000000000000) /* uncorrectable E$ tag error */ 276 #define C_AFSR_DUE INT64_C(0x0040000000000000) /* disrupting UE error */ 277 #endif /* CHEETAH_PLUS */ 278 #define C_AFSR_ME INT64_C(0x0020000000000000) /* errors > 1, same type!=CE */ 279 #define C_AFSR_PRIV INT64_C(0x0010000000000000) /* priv code access error */ 280 #define C_AFSR_PERR INT64_C(0x0008000000000000) /* system interface protocol */ 281 #define C_AFSR_IERR INT64_C(0x0004000000000000) /* internal system interface */ 282 #define C_AFSR_ISAP INT64_C(0x0002000000000000) /* system request parity err */ 283 #define C_AFSR_EMC INT64_C(0x0001000000000000) /* mtag with CE error */ 284 #define C_AFSR_EMU INT64_C(0x0000800000000000) /* mtag with UE error */ 285 #define C_AFSR_IVC INT64_C(0x0000400000000000) /* intr vector with CE error */ 286 #define C_AFSR_IVU INT64_C(0x0000200000000000) /* intr vector with UE error */ 287 #define C_AFSR_TO INT64_C(0x0000100000000000) /* bus timeout from sys bus */ 288 #define C_AFSR_BERR INT64_C(0x0000080000000000) /* bus error from system bus */ 289 #define C_AFSR_UCC INT64_C(0x0000040000000000) /* E$ with software CE error */ 290 #define C_AFSR_UCU INT64_C(0x0000020000000000) /* E$ with software UE error */ 291 #define C_AFSR_CPC INT64_C(0x0000010000000000) /* copyout with CE error */ 292 #define C_AFSR_CPU INT64_C(0x0000008000000000) /* copyout with UE error */ 293 #define C_AFSR_WDC INT64_C(0x0000004000000000) /* writeback ecache CE error */ 294 #define C_AFSR_WDU INT64_C(0x0000002000000000) /* writeback ecache UE error */ 295 #define C_AFSR_EDC INT64_C(0x0000001000000000) /* ecache CE ECC error */ 296 #define C_AFSR_EDU INT64_C(0x0000000800000000) /* ecache UE ECC error */ 297 #define C_AFSR_UE INT64_C(0x0000000400000000) /* uncorrectable ECC error */ 298 #define C_AFSR_CE INT64_C(0x0000000200000000) /* correctable ECC error */ 299 #define C_AFSR_M_SYND INT64_C(0x00000000000f0000) /* mtag ECC syndrome */ 300 #define C_AFSR_E_SYND INT64_C(0x00000000000001ff) /* data ECC syndrome */ 301 302 /* AFSR bits that could result in CPU removal due to E$ error */ 303 #define C_AFSR_L2_SERD_FAIL_UE (C_AFSR_UCU | C_AFSR_CPU | C_AFSR_WDU | \ 304 C_AFSR_EDU) 305 #define C_AFSR_L2_SERD_FAIL_CE (C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \ 306 C_AFSR_EDC) 307 /* 308 * Bits of the Panther Extended Asynchronous Fault Status Register (AFSR_EXT) 309 * 310 * +-----+-------+-----------+-------+-------+---------+------+------+------+ 311 * | rsv |RED_ERR|EFA_PAR_ERR|L3_MECC|L3_THCE|L3_TUE_SH|L3_TUE|L3_EDC|L3_EDU| 312 * +-----+-------+-----------+-------+-------+---------+------+------+------+ 313 * 63:14 13 12 11 10 9 8 7 6 314 * 315 * +------+------+------+------+------+------+ 316 * |L3_UCC|L3_UCU|L3_CPC|L3_CPU|L3_WDC|L3_WDU| 317 * +------+------+------+------+------+------+ 318 * 5 4 3 2 1 0 319 * 320 * If the L3_MECC bit is set along with any of the L3 cache errors (bits 0-7) 321 * above, it indicates that an address parity error has occured. 322 */ 323 #define C_AFSR_RED_ERR INT64_C(0x0000000000002000) /* redunancy Efuse error */ 324 #define C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */ 325 #define C_AFSR_L3_MECC INT64_C(0x0000000000000800) /* L3 address parity */ 326 #define C_AFSR_L3_THCE INT64_C(0x0000000000000400) /* tag CE */ 327 #define C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */ 328 #define C_AFSR_L3_TUE INT64_C(0x0000000000000100) /* tag UE */ 329 #define C_AFSR_L3_EDC INT64_C(0x0000000000000080) /* L3 cache CE */ 330 #define C_AFSR_L3_EDU INT64_C(0x0000000000000040) /* L3 cache UE */ 331 #define C_AFSR_L3_UCC INT64_C(0x0000000000000020) /* software recover CE */ 332 #define C_AFSR_L3_UCU INT64_C(0x0000000000000010) /* software recover UE */ 333 #define C_AFSR_L3_CPC INT64_C(0x0000000000000008) /* copyout with CE */ 334 #define C_AFSR_L3_CPU INT64_C(0x0000000000000004) /* copyout with UE */ 335 #define C_AFSR_L3_WDC INT64_C(0x0000000000000002) /* writeback CE */ 336 #define C_AFSR_L3_WDU INT64_C(0x0000000000000001) /* writeback UE */ 337 338 #if defined(JALAPENO) || defined(SERRANO) 339 /* 340 * Bits of Jalapeno Asynchronous Fault Status Register 341 * 342 * +-----+------------------------------------------------------------------ 343 * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETP|OM|UMS|IVPE|TO|BERR| 344 * +-----+------------------------------------------------------------------ 345 * 63:58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 346 * 347 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 348 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU| 349 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 350 * 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 351 * 352 * +-----+-----+-----+------+-----------+-------+ 353 * | JREQ| ETW | rsv |B_SYND| rsv | AID | E_SYND| 354 * +-----+-----+-----+------+-----+-----+-------+ 355 * 26:24 23:22 21:20 19:16 15:14 13:9 8:0 356 * 357 */ 358 359 /* 360 * Bits of Serrano Asynchronous Fault Status Register 361 * 362 * +-----+------------------------------------------------------------------ 363 * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETU|OM|UMS|IVPE|TO|BERR| 364 * +-----+------------------------------------------------------------------ 365 * 63:58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 366 * 367 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 368 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU| 369 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 370 * 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 371 * 372 * +-----+-----+------+---+------+---+---+-----+-------+ 373 * | JREQ| ETW | EFES |ETS|B_SYND|ETI|ETC| AID | E_SYND| 374 * +-----+-----+------+---+------+---+---+-----+-------+ 375 * 26:24 23:22 21 20 19:16 15 14 13:9 8:0 376 * 377 */ 378 379 #define C_AFSR_JETO INT64_C(0x0200000000000000) /* JBus Timeout */ 380 #define C_AFSR_SCE INT64_C(0x0100000000000000) /* Snoop parity error */ 381 #define C_AFSR_JEIC INT64_C(0x0080000000000000) /* JBus Illegal Cmd */ 382 #define C_AFSR_JEIT INT64_C(0x0040000000000000) /* Illegal ADTYPE */ 383 #define C_AFSR_JEIS INT64_C(0x0008000000000000) /* Illegal Install State */ 384 #if defined(SERRANO) 385 #define C_AFSR_ETU INT64_C(0x0001000000000000) /* L2$ tag CE error */ 386 #elif defined(JALAPENO) 387 #define C_AFSR_ETP INT64_C(0x0001000000000000) /* L2$ tag parity error */ 388 #endif /* JALAPENO */ 389 #define C_AFSR_OM INT64_C(0x0000800000000000) /* out of range mem error */ 390 #define C_AFSR_UMS INT64_C(0x0000400000000000) /* Unsupported store */ 391 #define C_AFSR_IVPE INT64_C(0x0000200000000000) /* intr vector parity err */ 392 #define C_AFSR_RUE INT64_C(0x0000000100000000) /* remote mem UE error */ 393 #define C_AFSR_RCE INT64_C(0x0000000080000000) /* remote mem CE error */ 394 #define C_AFSR_BP INT64_C(0x0000000040000000) /* read data parity err */ 395 #define C_AFSR_WBP INT64_C(0x0000000020000000) /* wb/bs data parity err */ 396 #define C_AFSR_FRC INT64_C(0x0000000010000000) /* foregin mem CE error */ 397 #define C_AFSR_FRU INT64_C(0x0000000008000000) /* foregin mem UE error */ 398 #define C_AFSR_JREQ INT64_C(0x0000000007000000) /* Active JBus req at err */ 399 #define C_AFSR_ETW INT64_C(0x0000000000c00000) /* AID causing UE/CE */ 400 401 #if defined(SERRANO) 402 #define C_AFSR_EFES INT64_C(0x0000000000200000) /* E-fuse error summary */ 403 #define C_AFSR_ETS INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */ 404 #endif /* SERRANO */ 405 406 #define C_AFSR_B_SYND INT64_C(0x00000000000f0000) /* jbus parity syndrome */ 407 408 #if defined(SERRANO) 409 #define C_AFSR_ETI INT64_C(0x0000000000008000) /* L2$ tag intermittent */ 410 #define C_AFSR_ETC INT64_C(0x0000000000004000) /* L2$ tag CE */ 411 #endif /* SERRANO */ 412 413 #define C_AFSR_AID INT64_C(0x0000000000003e00) /* AID causing UE/CE */ 414 415 /* bit shifts for selected errors */ 416 #define C_AFSR_WDU_SHIFT 37 417 #define C_AFSR_UCU_SHIFT 41 418 #define C_AFSR_UCC_SHIFT 42 419 #define C_AFSR_JREQ_SHIFT 24 420 #define C_AFSR_AID_SHIFT 9 421 422 /* 423 * Overloaded AFSR fields. During error processing, some of the reserved 424 * fields within the saved AFSR are overwritten with extra information. 425 */ 426 #define C_AFSR_PANIC_SHIFT 62 427 #define C_AFSR_IPE_SHIFT 59 428 #define C_AFSR_DPE_SHIFT 58 429 430 #else /* JALAPENO || SERRANO */ 431 432 /* bit shifts for selected errors */ 433 #define C_AFSR_WDU_SHIFT 37 434 #define C_AFSR_UCU_SHIFT 41 435 #define C_AFSR_UCC_SHIFT 42 436 #define C_AFSR_L3_UCU_SHIFT 4 437 438 /* 439 * Overloaded AFSR fields. During error processing, some of the reserved fields 440 * within the saved AFSR are overwritten with extra information. 441 */ 442 #define C_AFSR_FIRSTFLT_SHIFT 63 443 #define C_AFSR_PANIC_SHIFT 30 444 #define C_AFSR_DPE_SHIFT 20 445 #define C_AFSR_IPE_SHIFT 21 446 447 #endif /* JALAPENO || SERRANO */ 448 449 #if defined(JALAPENO) || defined(SERRANO) 450 /* 451 * Jalapeno L2 Cache Control Register Bits. 452 * 453 * Bit# Name Description 454 * 63-24 - reserved 455 * 23:20 EC_ACT_WAY (read only) indicates which sets are present 456 * 19:16 EC_BLK_WAY Bit mask indicating which sets are blocked 457 * from replacement 458 * 15:14 EC_SIZE L2 cache size 459 * 13:12 - reserved 460 * 11 EC_PAR_EN Enables parity checking on L2 cache tags 461 * 10 EC_ECC_EN Enables ECC checking on L2 cache data 462 * 9 EC_ECC_FORCE Enables EC_CHECK[8:0] onto L2 cache ECC bits 463 * 8:0 EC_CHECK ECC check vector to force onto ECC bits 464 */ 465 466 #define JP_ECCTRL_ECSIZE_MASK 0xc000 467 #define JP_ECCTRL_ECSIZE_SHIFT 14 468 #define JP_ECCTRL_ECSIZE_MIN 0x80000 469 470 /* 471 * Jalapeno L2 Cache Error Enable Register Bits 472 * 473 * Bit# Name Description 474 * 63-33 - reserved 475 * 32 SCDE Enable detection of JBUS control parity error 476 * 31:24 - reserved 477 * 23 IAEN Enable trap on illegal physical address 478 * 22 IERREN Enable FERR system reset on CPU internal errors 479 * 21 PERREN Enable FERR system reset on JBUS protocol errors 480 * 20 SCEN Enable FERR system reset on JBUS control parity error 481 * 19:11 FMED Forced error on the memory ECC 482 * 10 FME Force error on memory ECC 483 * 9:6 FPD Bits to use when FSP forces JBUS addr/data parity error 484 * 5 FSP Force error on outgoing JBUS addr/data parity 485 * 4 ETPEN Enable FERR system reset on L2 tags parity error 486 * 3 UCEEN Enable trap on SW handled external cache error 487 * 2 ISAPEN Enable FERR system reset on request parity error 488 * 1 NCEEN Enable trap on uncorrectable ECC error and system err 489 * 0 CEEN Enable trap on correctable ECC errors 490 */ 491 492 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */ 493 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */ 494 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */ 495 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */ 496 497 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */ 498 #define EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN) 499 #define EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN) 500 #define EN_REG_ENABLE \ 501 (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN) 502 503 #else /* JALAPENO || SERRANO */ 504 #if defined(CHEETAH_PLUS) 505 /* 506 * Cheetah+ External Cache Control Register Bits. 507 */ 508 #define ECCR_ASSOC INT64_C(0x0000000001000000) /* Ecache Assoc. */ 509 #define ECCR_ASSOC_SHIFT 24 510 #endif /* CHEETAH_PLUS */ 511 512 /* 513 * Bits of Cheetah External Cache Error Enable Register 514 * 515 * +-----+-----+-------+-----+-------+-------+--------+-------+------+ 516 * | rsv | FMT | FMECC | FMD | FDECC | UCEEN | ISAPEN | NCEEN | CEEN | 517 * +-----+-----+-------+-----+-------+-------+--------+-------+------+ 518 * 63:19 18 17 14 13 12:4 3 2 1 0 519 * 520 */ 521 #define EN_REG_FMT INT64_C(0x0000000000040000) /* force system mtag ECC */ 522 #define EN_REG_FMECC INT64_C(0x000000000003C000) /* forced mtag ECC vector */ 523 #define EN_REG_FMD INT64_C(0x0000000000002000) /* force system data ECC */ 524 #define EN_REG_FDECC INT64_C(0x0000000000001ff0) /* forced data ECC vector */ 525 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */ 526 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */ 527 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */ 528 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */ 529 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */ 530 #define EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN) 531 #define EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN) 532 #define EN_REG_ENABLE \ 533 (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN) 534 #endif /* JALAPENO || SERRANO */ 535 536 /* 537 * bit shifts for selected bits 538 */ 539 #define EN_REG_CEEN_SHIFT 0 540 541 /* Cheetah/Cheetah+ Dcache size */ 542 #define CH_DCACHE_SIZE 0x10000 543 544 /* Cheetah/Cheetah+ Dcache linesize */ 545 #define CH_DCACHE_LSIZE 0x20 546 547 /* Cheetah/Cheetah+/Jaguar Icache size */ 548 #define CH_ICACHE_SIZE 0x8000 549 550 /* Cheetah/Cheetah+/Jaguar Icache linesize */ 551 #define CH_ICACHE_LSIZE 0x20 552 553 /* Panther Icache size */ 554 #define PN_ICACHE_SIZE 0x10000 555 556 /* Panther Icache linesize */ 557 #define PN_ICACHE_LSIZE 0x40 558 559 /* Pcache size for the cheetah family of CPUs */ 560 #define CH_PCACHE_SIZE 0x800 561 562 /* Pcache linesize for the cheetah family of CPUs */ 563 #define CH_PCACHE_LSIZE 0x40 564 565 /* 566 * The cheetah+ CPU module handles Cheetah+, Jaguar, and Panther so 567 * we have to pick max size and min linesize values for the Icache 568 * accordingly. 569 */ 570 #define CHP_ICACHE_MAX_SIZE PN_ICACHE_SIZE 571 #define CHP_ICACHE_MIN_LSIZE CH_ICACHE_LSIZE 572 573 /* 574 * The minimum size needed to ensure consistency on a virtually address 575 * cache. Computed by taking the largest virtually indexed cache and dividing 576 * by its associativity. 577 */ 578 #define CH_VAC_SIZE 0x4000 579 580 /* 581 * The following definitions give the syndromes that will be seen when attempts 582 * are made to read data that has been intentionally poisoned. Intentional 583 * poisoning is performed when an error has been detected, and is designed to 584 * allow software to effectively distinguish between root problems and secondary 585 * effects. The following syndromes and their descriptions are taken from the 586 * UltraSPARC-III Cu Error Manual, Section 5.4.3.1. 587 */ 588 589 /* 590 * For a DSTAT = 2 or 3 event (see Sec 5.3.4.4) from the system bus for a 591 * cacheable load, data bits [1:0] are inverted in the data stored in the 592 * L2-cache. The syndrome seen when one of these signalling words is read will 593 * be 0x11c. 594 */ 595 #define CH_POISON_SYND_FROM_DSTAT23 0x11c 596 597 /* 598 * For an uncorrectable data ECC error from the L2-cache, data bits [127:126] 599 * are inverted in data sent to the system bus as part of a writeback or 600 * copyout. The syndrome seen when one of these signalling words is read will 601 * be 0x071. 602 */ 603 #define CH_POISON_SYND_FROM_XXU_WRITE 0x71 604 605 /* 606 * For uncorrectable data ECC error on the L2-cache read done to complete a 607 * store merge event, where bytes written by the processor are merged with 608 * bytes from an L2-cache line, ECC check bits [1:0] are inverted in the data 609 * scrubbed back to the L2-cache. The syndrome seen when one of these 610 * signalling words is read will be 0x003. 611 */ 612 #define CH_POISON_SYND_FROM_XXU_WRMERGE 0x3 613 614 /* 615 * To help understand the following definitions, this block of comments 616 * provides information on Cheetah's E$. 617 * 618 * Cheetah supports three different E$ sizes (1MB, 4MB, and 8MB). The 619 * number of E$ lines remains constant regardless of the size of the E$ 620 * as does the subblock size, however the number of 64-byte subblocks per 621 * line varies depending on the E$ size. 622 * 623 * An E$ tag (for an E$ line) contains an EC_tag field, corresponding to the 624 * high order physical address bits of that E$ line's contents, and 1 to 8 625 * EC_state fields, indicating the state of each subblock. Due to the E$ line 626 * size variance depending on the total size of the E$, the number of bits in 627 * the EC_tag field varies as does the number of subblocks (and EC_state 628 * fields) per E$ line. 629 * 630 * A 1MB E$ has a line size of 64 bytes, containing 1 subblock per line. 631 * A 4MB E$ has a line size of 256 bytes, containing 4 subblocks per line. 632 * An 8MB E$ has a line size of 512 bytes, containing 8 subblocks per line. 633 * 634 * An E$ tag for a particular E$ line can be read via a diagnostic ASI 635 * as a 64-bit value. 636 * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows: 637 * - for a 1MB E$, the EC_tag is in bits <43:21> and corresponds 638 * to physical address bits <42:20> (bits <41:19> for Cheetah+) 639 * - for a 4MB E$, the EC_tag is in bits <43:23> and corresponds 640 * to physical address bits <42:22> (bits <41:21> for Cheetah+) 641 * - for an 8MB E$, the EC_tag is in bits <43:24> and corresponds 642 * to physical address bits <42:23> (bits <41:22> for Cheetah+) 643 * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted 644 * as follows: 645 * - for a 1MB E$, EC_state0 is in bits <2:0> 646 * - for a 4MB E$, EC_state0 is in bits <2:0>, EC_state1 is in 647 * bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is 648 * in bits <11:9> 649 * - for an 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in 650 * bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is 651 * in bits <11:9>, EC_state4 is in bits <14:12>, EC_state5 652 * is in bits <17:15>, EC_state6 is in bits <20:18>, 653 * EC_state7 is in bits <23:21> 654 * Note that each EC_state field contains a value representing the state 655 * of its corresponding subblock. 656 * 657 */ 658 /* 659 * Jaguar changes from Cheetah/Cheetah+ Ecache: 660 * 661 * The Jaguar Ecache is similiar to that used for Cheetah/Cheetah+ with a 662 * couple of differences : 663 * - Jaguar Ecache only comes in 4MB and 8MB versions. 664 * - 8MB E$ has 2 64 byte subblocks per line. 665 * - 4MB E$ has 1 64 byte subblock per line. 666 * 667 * An E$ tag for a particular E$ line can be read via a diagnostic ASI 668 * as a 64-bit value. 669 * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows: 670 * - for a 4MB E$, the EC_tag is in bits <41:21> and corresponds 671 * to physical address bits <41:21> 672 * - for a 8MB E$, the EC_tag is in bits <41:22> and corresponds 673 * to physical address bits <41:22> 674 * 675 * The Jaguar E$ tag also contains LRU field in bit <42> which must be 676 * masked off when the tag value is being compared to a PA. 677 * 678 * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted 679 * as follows: 680 * - for 4MB E$, EC_state0 is in bits <2:0> 681 * - for 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in bits <5:3>. 682 * Each EC_state field contains a value representing the state of its 683 * corresponding subblock. 684 * 685 * Note that the subblock size and state values are the same for both 686 * Cheetah/Cheetah+ and Jaguar. 687 */ 688 689 /* Ecache sizes */ 690 #define CH_ECACHE_8M_SIZE 0x800000 691 #define CH_ECACHE_4M_SIZE 0x400000 692 #define CH_ECACHE_1M_SIZE 0x100000 693 694 #define PN_L2_SIZE 0x200000 695 #define PN_L2_LINESIZE 64 696 #define PN_L2_ECC_WORDS 2 697 #define PN_L2_NWAYS 4 698 #define PN_L2_SET_SIZE (PN_L2_SIZE / PN_L2_NWAYS) 699 #define PN_L2_MAX_SET (PN_L2_SIZE - PN_L2_SET_SIZE) 700 #define PN_L2_DATA_ECC_SEL 0x200000 /* bit 21 selects ECC */ 701 #define PN_L2_ECC_LO_REG 0x20 /* bit 5 set for L2 tag access */ 702 #define PN_L2_INDEX_MASK 0x7ffc0 /* bits 18:6 */ 703 #define PN_L2_WAY_INCR 0x80000 /* l2-ec-way = <20:19> */ 704 #define PN_L2_WAY_LIM INT64_C(0x200000) 705 #define PN_L2_WAY_SHIFT 19 706 707 #define PN_L3_SIZE 0x2000000 708 #define PN_L3_LINESIZE 64 709 #define PN_L3_NWAYS 4 710 #define PN_L3_SET_SIZE (PN_L3_SIZE / PN_L3_NWAYS) 711 #define PN_L3_MAX_SET (PN_L3_SIZE - PN_L3_SET_SIZE) 712 #define PN_L3_WAY_SHIFT 23 713 #define PN_L3_TAG_RD_MASK 0x7fffc0 /* ec_tag = PA<22:6> */ 714 #define PN_L3_WAY_INCR 0x800000 /* ec_way = <24:23> */ 715 #define PN_L3_WAY_LIM INT64_C(0x2000000) 716 717 /* Pcache Defines */ 718 #define PN_PCACHE_ADDR_MASK 0x1c0 /* PC_addr = <8:6> */ 719 #define PN_PCACHE_WAY_INCR 0x200 /* PC_way = <10:9> */ 720 #define PN_PCACHE_WORD_SHIFT 3 /* PC_dbl_word = <5:3> */ 721 #define PN_PCACHE_NWAYS 4 722 723 /* Cheetah Ecache is direct-mapped, Cheetah+ can be 2-way or direct-mapped */ 724 #define CH_ECACHE_NWAY 1 725 #if defined(CHEETAH_PLUS) 726 #define CHP_ECACHE_NWAY 2 727 #define PN_ECACHE_NWAY 4 728 #endif /* CHEETAH_PLUS */ 729 #if defined(JALAPENO) || defined(SERRANO) 730 #define JP_ECACHE_NWAY 4 731 #define JP_ECACHE_NWAY_SHIFT 2 732 #endif /* JALAPENO || SERRANO */ 733 734 /* Maximum Ecache size */ 735 #define CH_ECACHE_MAX_SIZE CH_ECACHE_8M_SIZE 736 737 /* Minimum Ecache line size */ 738 #define CH_ECACHE_MIN_LSIZE 64 739 740 /* Maximum Ecache line size - 8Mb Ecache has 512 byte linesize */ 741 #define CH_ECACHE_MAX_LSIZE 512 742 743 /* Size of Ecache data staging register size (see Cheetah PRM 10.7.2) */ 744 #define CH_ECACHE_STGREG_SIZE 32 745 #define CH_ECACHE_STGREG_TOTALSIZE 40 /* data regs + ecc */ 746 747 /* The number of staging registers containing data, for ASI_EC_DATA */ 748 #define CH_ECACHE_STGREG_NUM (CH_ECACHE_STGREG_SIZE / sizeof (uint64_t)) 749 750 /* Size of Ecache data subblock which has state field in Ecache tag */ 751 #define CH_ECACHE_SUBBLK_SIZE 64 752 #define CH_ECACHE_SUBBLK_SHIFT 6 753 754 #if defined(JALAPENO) || defined(SERRANO) 755 #define JP_ECACHE_MAX_LSIZE CH_ECACHE_SUBBLK_SIZE 756 #define JP_ECACHE_MAX_SIZE 0x400000 757 #endif /* JALAPENO || SERRANO */ 758 759 /* 760 * Maximum ecache setsize to support page coloring of heterogenous 761 * cheetah+ cpus. Max ecache setsize is calculated to be the max ecache size 762 * divided by the minimum associativity of the max ecache. 763 * 764 * NOTE: CHP_ECACHE_MAX_SIZE and CHP_ECACHE_MIN_NWAY need to be updated with 765 * new cheetah+ cpus. The maximum setsize may not necessarily be associated with 766 * the max ecache size if the cache associativity is large. If so, MAX_SETSIZE 767 * needs to be updated accordingly. 768 */ 769 #if defined(CHEETAH_PLUS) 770 #define CHP_ECACHE_MIN_NWAY 1 /* direct-mapped */ 771 #define CHP_ECACHE_MAX_SIZE CH_ECACHE_MAX_SIZE 772 #define CHP_ECACHE_MAX_SETSIZE (CHP_ECACHE_MAX_SIZE / CHP_ECACHE_MIN_NWAY) 773 #endif /* CHEETAH_PLUS */ 774 775 /* 776 * Bits to shift EC_tag field of E$ tag to form PA 777 * (See Cheetah PRM 10.7.4, Cheetah+ Delta PRM 10.7) 778 */ 779 #if defined(JALAPENO) || defined(SERRANO) 780 #define CH_ECTAG_PA_SHIFT 18 781 #elif defined(CHEETAH_PLUS) 782 #define CH_ECTAG_PA_SHIFT 2 783 #else /* CHEETAH_PLUS */ 784 #define CH_ECTAG_PA_SHIFT 1 785 #endif /* CHEETAH_PLUS */ 786 #define PN_L3TAG_PA_SHIFT 1 787 #define PN_L3TAG_PA_MASK 0xfffff000000 /* tag bits[43:24] */ 788 #define PN_L2TAG_PA_MASK 0x7fffff80000 /* tag bits[42:19] */ 789 790 #if defined(JALAPENO) || defined(SERRANO) 791 /* 792 * Macros for Jalapeno L2 Cache Tag/State/Parity 793 * 794 * +-----------+--------+--------+----------------------+ 795 * | - | EC_par |EC_state| EC_tag = PA[42:18] | 796 * +-----------+--------+--------+----------------------+ 797 * 63:29 28 27:25 24:0 798 */ 799 /* 800 * Constants representing the complete Jalapeno Ecache tag state: 801 */ 802 #define JP_ECSTATE_SIZE 3 /* three bits */ 803 #define JP_ECSTATE_MASK 0x7 /* three bit field */ 804 #define JP_ECSTATE_INV 0x0 /* invalid */ 805 #define JP_ECSTATE_SHR 0x1 /* shared */ 806 #define JP_ECSTATE_RES1 0x2 /* reserved */ 807 #define JP_ECSTATE_EXL 0x3 /* exclusive */ 808 #define JP_ECSTATE_RES2 0x4 /* reserved */ 809 #define JP_ECSTATE_OWN 0x5 /* owner */ 810 #define JP_ECSTATE_MOD 0x7 /* modified */ 811 #define JP_ECSTATE_RES3 0x6 /* reserved */ 812 #define JP_ECTAG_STATE_SHIFT 25 813 814 #define CH_ECSTATE_SIZE JP_ECSTATE_SIZE 815 #define CH_ECSTATE_MASK JP_ECSTATE_MASK 816 #define CH_ECSTATE_INV JP_ECSTATE_INV 817 #define CH_ECSTATE_SHR JP_ECSTATE_SHR 818 #define CH_ECSTATE_EXL JP_ECSTATE_EXL 819 #define CH_ECSTATE_OWN JP_ECSTATE_OWN 820 #define CH_ECSTATE_MOD JP_ECSTATE_MOD 821 #define CH_ECSTATE_RES1 JP_ECSTATE_RES1 822 #define CH_ECSTATE_OWS JP_ECSTATE_RES3 823 #define CH_ECSTATE_RES2 JP_ECSTATE_RES2 824 825 /* Number of subblock states per Ecache line. */ 826 #define CH_ECTAG_NSUBBLKS(totalsize) 1 827 828 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 829 #define CH_ECTAG_STATE_SHIFT(subblk) JP_ECTAG_STATE_SHIFT 830 #define CH_ECTAG_STATE_MASK(totalsize) \ 831 ((uint64_t)(JP_ECSTATE_MASK<<JP_ECTAG_STATE_SHIFT)) 832 833 /* For a line to be invalid, all of its subblock states must be invalid. */ 834 #define CH_ECTAG_LINE_INVALID(totalsize, tag) \ 835 (((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0) 836 837 /* Build address mask for tag physical address bits. */ 838 #define CH_ECTAG_PA_MASK(setsize) P2ALIGN(C_AFAR_PA, (int)(setsize)) 839 840 /* Get physical address bits from the EC_tag field of an E$ tag */ 841 #define CH_ECTAG_TO_PA(setsize, tag) (((tag) << CH_ECTAG_PA_SHIFT) & \ 842 CH_ECTAG_PA_MASK(setsize)) 843 844 /* Given a physical address, compute index for subblock tag state. */ 845 #define CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) 1 846 847 /* Given a physical address and assoc. tag, get the subblock state. */ 848 #define CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 849 (((tag) >> JP_ECTAG_STATE_SHIFT) & JP_ECSTATE_MASK) 850 851 #else /* JALAPENO || SERRANO */ 852 853 /* 854 * Constants representing the complete Cheetah Ecache tag state: 855 */ 856 #define CH_ECSTATE_SIZE 3 /* three bits per subblock */ 857 #define CH_ECSTATE_MASK 0x7 /* three bit field */ 858 #define CH_ECSTATE_INV 0x0 /* invalid */ 859 #define CH_ECSTATE_SHR 0x1 /* shared */ 860 #define CH_ECSTATE_EXL 0x2 /* exclusive */ 861 #define CH_ECSTATE_OWN 0x3 /* owner */ 862 #define CH_ECSTATE_MOD 0x4 /* modified */ 863 #define CH_ECSTATE_RES1 0x5 /* reserved */ 864 #define CH_ECSTATE_OWS 0x6 /* owner/shared */ 865 #define CH_ECSTATE_RES2 0x7 /* reserved */ 866 867 /* 868 * Macros for Cheetah Ecache tags 869 */ 870 871 /* Number of subblock states per Ecache line. */ 872 #define CH_ECTAG_NSUBBLKS(totalsize) ((totalsize) / CH_ECACHE_1M_SIZE) 873 874 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 875 #define CH_ECTAG_STATE_SHIFT(subblk) (subblk * CH_ECSTATE_SIZE) 876 #define CH_ECTAG_STATE_MASK(totalsize) \ 877 ((uint64_t) \ 878 ((1 << (CH_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1)) 879 880 /* For a line to be invalid, all of its subblock states must be invalid. */ 881 #define CH_ECTAG_LINE_INVALID(totalsize, tag) \ 882 (((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0) 883 884 /* Build address mask for tag physical address bits. */ 885 #define CH_ECTAG_PA_MASK(setsize) P2ALIGN(C_AFAR_PA, (int)(setsize)) 886 887 /* Get physical address bits from the EC_tag field of an E$ tag */ 888 #define CH_ECTAG_TO_PA(setsize, tag) (((tag) >> CH_ECTAG_PA_SHIFT) & \ 889 CH_ECTAG_PA_MASK(setsize)) 890 891 /* Given a physical address, compute index for subblock tag state. */ 892 #define CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) \ 893 (((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (CH_ECTAG_NSUBBLKS(totalsize) - 1)) 894 895 /* Given a physical address and assoc. tag, get the subblock state. */ 896 #define CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 897 (((tag) >> \ 898 (CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) & \ 899 CH_ECSTATE_MASK) 900 #endif /* JALAPENO || SERRANO */ 901 902 /* Panther only has one EC_State field in the L3 tag */ 903 #define PN_L3_LINE_INVALID(tag) (((tag) & CH_ECSTATE_MASK) == 0) 904 905 /* Panther only has one State field in the L2 tag */ 906 #define PN_L2_LINE_INVALID(tag) (((tag) & CH_ECSTATE_MASK) == 0) 907 908 /* Get physical address bits from the EC_tag field of an L3$ tag */ 909 #define PN_L3TAG_TO_PA(tag) (((tag) & PN_L3TAG_PA_MASK) >> \ 910 PN_L3TAG_PA_SHIFT) 911 912 /* Get physical address bits from the tag field of an L2$ tag */ 913 #define PN_L2TAG_TO_PA(tag) ((tag) & PN_L2TAG_PA_MASK) 914 915 #if defined(JALAPENO) || defined(SERRANO) 916 /* 917 * Jalapeno L2 Cache ASI_ECACHE_FLUSH: 918 * +-------+-----------------+--------+---+-----+-------------+------+ 919 * | - | Port_ID | - | EC_Way | 1 | - | EC_Tag_Addr | - | 920 * +-------+-----------------+--------+---+-----+-------------+------+ 921 * 63:41 40:36 35:34 33:32 31 30:18 17:6 5:0 922 */ 923 924 #define JP_EC_TO_SET_SIZE_SHIFT 2 925 #define JP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000080000000) 926 #define JP_ECFLUSH_PORTID_SHIFT 36 927 #define JP_ECFLUSH_EC_WAY_SHIFT 32 928 #define JP_EC_TAG_DATA_WAY_SHIFT JP_ECFLUSH_EC_WAY_SHIFT 929 #endif /* JALAPENO || SERRANO */ 930 931 /* 932 * Macros for Jaguar Ecache tags 933 */ 934 935 /* Ecache sizes */ 936 #define JG_ECACHE_8M_SIZE 0x800000 937 #define JG_ECACHE_4M_SIZE 0x400000 938 939 /* Jaguar E$ tag LRU mask */ 940 #define JG_LRU_MASK UINT64_C(0x0000040000000000) /* PA<42> LRU bit */ 941 942 /* 943 * Note that Jaguar and Cheetah/Cheetah+ have the same subblock state size 944 * so rather than duplicating existing defn's we can use the Cheetah+ versions 945 * in the Jaguar defn's below. 946 */ 947 /* Number of subblock states per Ecache line. */ 948 #define JG_ECTAG_NSUBBLKS(cachesize) ((cachesize) / JG_ECACHE_4M_SIZE) 949 950 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 951 #define JG_ECTAG_STATE_MASK(totalsize) \ 952 ((uint64_t) \ 953 ((1 << (JG_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1)) 954 955 /* For a line to be invalid, all of its subblock states must be invalid. */ 956 #define JG_ECTAG_LINE_INVALID(totalsize, tag) \ 957 (((tag) & JG_ECTAG_STATE_MASK(totalsize)) == 0) 958 959 /* Build address mask for tag physical address bits. */ 960 #define JG_ECTAG_PA_MASK(setsize) P2ALIGN(((~JG_LRU_MASK) & C_AFAR_PA), \ 961 (int)(setsize)) 962 963 /* Get physical address bits from the EC_tag field of an E$ tag */ 964 #define JG_ECTAG_TO_PA(setsize, tag) ((tag & JG_ECTAG_PA_MASK(setsize))) 965 966 /* Given a physical address, compute index for subblock tag state. */ 967 #define JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) \ 968 (((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (JG_ECTAG_NSUBBLKS(totalsize) - 1)) 969 970 /* Given a physical address and assoc. tag, get the subblock state. */ 971 #define JG_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 972 (((tag) >> \ 973 (JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) & \ 974 CH_ECSTATE_MASK) 975 976 977 #if defined(CHEETAH_PLUS) 978 /* 979 * Cheetah+ Tag ECC Bit and Displacement Flush Bit in Ecache Tag Access. 980 * See Cheetah+ Delta PRM 10.7 981 */ 982 #define CHP_ECACHE_IDX_TAG_ECC INT64_C(0x0000000000800000) 983 #define CHP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000001000000) 984 #define PN_L2_IDX_DISP_FLUSH INT64_C(0x0000000000800000) 985 #define PN_L3_IDX_DISP_FLUSH INT64_C(0x0000000004000000) 986 #endif /* CHEETAH_PLUS */ 987 988 /* 989 * Macros for Cheetah Dcache diagnostic accesses. 990 */ 991 992 /* 993 * Dcache Index Mask for bits from *AFAR*. Note that Dcache is virtually 994 * indexed, so only bits [12:5] are valid from the AFAR. This 995 * means we have to search through the 4 ways + bit 13 (i.e. we have 996 * to try 8 indexes). 997 */ 998 #define CH_DCACHE_IDX_MASK 0x01fe0 999 #define CH_DCACHE_IDX_INCR 0x02000 1000 #define CH_DCACHE_IDX_LIMIT 0x10000 1001 #define CH_DCACHE_NWAY 4 1002 #define CH_DCACHE_WAY_MASK 0x0c000 1003 #define CH_DCACHE_WAY_SHIFT 14 1004 #define CH_DCIDX_TO_WAY(idx) (((idx) & CH_DCACHE_WAY_MASK) >> \ 1005 CH_DCACHE_WAY_SHIFT) 1006 #define CH_DCTAG_PA_MASK INT64_C(0x000007ffffffe000) 1007 #define CH_DCTAG_PA_SHIFT 12 1008 #define CH_DCTAG_VALID_BIT INT64_C(0x0000000000000001) 1009 #define CH_DCTAG_LINE_INVALID(tag) (((tag) & CH_DCTAG_VALID_BIT) == 0) 1010 #define CH_DCIDX_TO_ADDR(idx) ((idx) & CH_DCACHE_IDX_MASK) 1011 #define CH_DCTAG_TO_PA(tag) (((tag) << CH_DCTAG_PA_SHIFT) & \ 1012 CH_DCTAG_PA_MASK) 1013 #define CH_DCTAG_MATCH(tag, pa) (!CH_DCTAG_LINE_INVALID(tag) && \ 1014 ((pa) & CH_DCTAG_PA_MASK) == CH_DCTAG_TO_PA(tag)) 1015 #define CH_DCSNTAG_MASK INT64_C(0x000007ffffffe000) 1016 #define CH_DCSNTAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 1017 & CH_DCSNTAG_MASK) 1018 #define CH_DCUTAG_TO_UTAG(tag) ((tag) & 0xff) 1019 #define CH_DCUTAG_TO_VA(tag) ((tag & 0xff) << 14) 1020 #define CH_DCUTAG_IDX_MASK 0x03fe0 1021 #define CH_DC_DATA_REG_SIZE 32 1022 #define CH_DC_UTAG_MASK 0xff 1023 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO) 1024 #define CHP_DCTAG_PARMASK INT64_C(0x000000007ffffffe) 1025 #define CHP_DCSNTAG_PARMASK INT64_C(0x000000007ffffffe) 1026 #define CHP_DCTAG_MASK INT64_C(0x000003ffffffe000) 1027 #define CHP_DCSNTAG_MASK INT64_C(0x000003ffffffe000) 1028 #define CHP_DCWAY_MASK INT64_C(0x0000000000003fe0) 1029 #define CHP_DCUTAG_TO_UTAG(tag) ((tag) & 0xffff) 1030 #define CHP_DCPATAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 1031 & CHP_DCTAG_MASK) 1032 #define CHP_DCSNTAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 1033 & CHP_DCSNTAG_MASK) 1034 #define CHP_DC_IDX(dcp) ((dcp->dc_idx & 0x1fc0) >> 5) 1035 #define CHP_DCTAG_PARITY(tag) (tag & CHP_DC_TAG) 1036 #define CHP_DCSNTAG_PARITY(tag) (tag & CHP_DC_SNTAG) 1037 #define CHP_DC_TAG 0x1 1038 #define CHP_DC_SNTAG 0x2 1039 #define PN_DC_DATA_PARITY_SHIFT 8 1040 #define PN_DC_DATA_PARITY_MASK 0xff 1041 #define PN_DC_DATA_ALL_PARITY_MASK 0xffffffff 1042 #endif /* CHEETAH_PLUS || JALAPENO || SERRANO */ 1043 #define PN_DC_DATA_PARITY_BIT_SHIFT 16 1044 1045 /* 1046 * Macros for Cheetah Icache diagnostic accesses. 1047 */ 1048 1049 /* 1050 * Icache Index Mask for bits from *AFAR*. Note that the Icache is virtually 1051 * indexed for Panther and physically indexed for other CPUs. For Panther, 1052 * we obtain an index by looking at bits[12:6] of the AFAR PA and we check 1053 * both lines associated with bit 13 = 0 or 1 (total of 8 entries to check). 1054 * For non-Panther CPUs we get our index by just looking at bits[12:5] of 1055 * the AFAR PA (total of 4 entries to check). The Icache index is also 1056 * confusing because we need to shift the virtual address bits left by one 1057 * for the index. 1058 */ 1059 #define CH_ICACHE_IDX_MASK 0x01fe0 1060 #define PN_ICACHE_IDX_MASK 0x03fc0 1061 #define PN_ICACHE_VA_IDX_MASK 0x01fc0 1062 #define CH_ICACHE_IDX_SHIFT 1 1063 #define CH_ICACHE_IDX_INCR 0x04000 1064 #define PN_ICACHE_IDX_INCR 0x08000 1065 #define CH_ICACHE_IDX_LIMIT 0x10000 1066 #define PN_ICACHE_IDX_LIMIT 0x20000 1067 #define CH_ICACHE_NWAY 4 1068 #define CH_ICACHE_WAY_MASK 0x0c000 1069 #define CH_ICACHE_WAY_SHIFT 14 1070 #define PN_ICACHE_WAY_MASK 0x18000 1071 #define PN_ICACHE_WAY_SHIFT 15 1072 #define CH_ICTAG_PA 0x00 1073 #define CH_ICTAG_UTAG 0x08 1074 #define CH_ICTAG_UPPER 0x10 1075 #define CH_ICTAG_LOWER 0x30 1076 #define CH_ICTAG_TMASK 0x3f 1077 #define CH_ICPATAG_MASK INT64_C(0x000007ffffffe000) 1078 #define CH_ICPATAG_LBITS 0xff /* lower 8 bits undefined */ 1079 #define CH_ICPATAG_SHIFT 5 1080 #define CH_ICIDX_TO_WAY(idx) (((idx) & CH_ICACHE_WAY_MASK) >> \ 1081 CH_ICACHE_WAY_SHIFT) 1082 #define PN_ICIDX_TO_WAY(idx) (((idx) & PN_ICACHE_WAY_MASK) >> \ 1083 PN_ICACHE_WAY_SHIFT) 1084 #define CH_ICIDX_TO_ADDR(idx) (((idx) >> CH_ICACHE_IDX_SHIFT) & \ 1085 CH_ICACHE_IDX_MASK) 1086 #define PN_ICIDX_TO_ADDR(idx) (((idx) >> CH_ICACHE_IDX_SHIFT) & \ 1087 PN_ICACHE_IDX_MASK) 1088 #define CH_ICPATAG_TO_PA(tag) (((tag) << CH_ICPATAG_SHIFT) & \ 1089 CH_ICPATAG_MASK) 1090 #define CH_ICPATAG_MATCH(tag, pa) (CH_ICPATAG_TO_PA(tag) == \ 1091 ((pa) & CH_ICPATAG_MASK)) 1092 #define CH_ICUTAG_MASK INT64_C(0x00000000001fe000) 1093 #define CH_ICUTAG_TO_UTAG(tag) (((tag) >> 38) & 0xff) 1094 #define CH_ICUTAG_TO_VA(tag) (((tag) >> 25) & CH_ICUTAG_MASK) 1095 #define CH_ICSNTAG_MASK INT64_C(0x000007ffffffe000) 1096 #define CH_ICSNTAG_TO_PA(tag) (((tag) << 5) & CH_ICSNTAG_MASK) 1097 #define CH_ICLOWER_VALID INT64_C(0x0004000000000000) 1098 #define CH_ICUPPER_VALID INT64_C(0x0004000000000000) 1099 #define CH_ICLOWER_TO_VPRED(lower) (((lower) >> 46) & 0xf) 1100 #define CH_ICUPPER_TO_VPRED(upper) (((upper) >> 46) & 0xf) 1101 #if defined(CHEETAH_PLUS) 1102 #define CH_ICTAG_MATCH(icp, pa) (((icp->ic_lower | icp->ic_upper) & \ 1103 CH_ICLOWER_VALID) && \ 1104 CH_ICPATAG_MATCH(icp->ic_patag, pa)) 1105 #define PN_ICUTAG_TO_VA(tag) ((tag >> 24) & PN_ICUTAG_MASK) 1106 #else /* CHEETAH_PLUS */ 1107 #define CH_ICTAG_MATCH(icp, pa) ((icp->ic_lower & CH_ICLOWER_VALID) &&\ 1108 CH_ICPATAG_MATCH(icp->ic_patag, pa)) 1109 #define PN_ICUTAG_TO_VA(tag) 0 1110 #endif /* CHEETAH_PLUS */ 1111 1112 #define CH_IC_DATA_REG_SIZE 64 1113 #define PN_IC_DATA_REG_SIZE 128 1114 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO) 1115 #define CHP_IC_IDX(icp) ((icp->ic_idx & 0x3fc0) >> 6) 1116 #define PN_IC_IDX(icp) ((icp->ic_idx & 0x7f80) >> 7) 1117 #define CHP_ICPATAG_MASK INT64_C(0x000003ffffffe000) 1118 #define CHP_ICSNTAG_MASK INT64_C(0x000003ffffffe000) 1119 #define CHP_ICUTAG_MASK INT64_C(0x00000000001fe000) 1120 #define PN_ICUTAG_MASK INT64_C(0x00000000003fc000) 1121 #define CHP_ICWAY_MASK INT64_C(0x0000000000003fe0) 1122 #define CHP_ICPATAG_TO_PA(tag) ((tag << 5) & CHP_ICPATAG_MASK) 1123 #define CHP_ICSNTAG_TO_PA(tag) ((tag << 5) & CHP_ICSNTAG_MASK) 1124 #define CHP_ICUTAG_TO_VA(tag) ((tag >> 25) & CHP_ICUTAG_MASK) 1125 #define CHP_ICPATAG_PARMASK INT64_C(0x0000003fffffff00) 1126 #define CHP_ICSNTAG_PARMASK INT64_C(0x0000003fffffff00) 1127 1128 /* 1129 * Cheetah+ Icache data parity masks, see Cheetah+ Delta PRM 7.3 1130 * PC-relative instructions have different bits protected by parity. 1131 * Predecode bit 7 is not parity protected and indicates if the instruction 1132 * is PC-relative or not. 1133 */ 1134 #define CH_ICDATA_PRED_ISPCREL INT64_C(0x0000008000000000) 1135 #define CHP_ICDATA_PCREL_PARMASK INT64_C(0x0000039ffffff800) 1136 #define CHP_ICDATA_NPCREL_PARMASK INT64_C(0x000003bfffffffff) 1137 #define PN_ICDATA_PARITY_BIT_MASK INT64_C(0x40000000000) 1138 #define CHP_ICTAG_PARITY(tag) (tag & CHP_IC_TAG) 1139 #define CHP_ICSNTAG_PARITY(tag) (tag & CHP_IC_SNTAG) 1140 #define CHP_IC_TAG 0x1 1141 #define CHP_IC_SNTAG 0x2 1142 #endif /* CHEETAH_PLUS || JALAPENO || SERRANO */ 1143 #if defined(CHEETAH_PLUS) 1144 #define PN_IPB_TAG_ADDR_LINESIZE 0x40 1145 #define PN_IPB_TAG_ADDR_MAX 0x3c0 1146 #endif /* CHEETAH_PLUS */ 1147 1148 /* 1149 * Macros for Pcache diagnostic accesses. 1150 */ 1151 #define CH_PC_WAY_MASK 0x600 1152 #define CH_PC_WAY_SHIFT 9 1153 #define CH_PCIDX_TO_WAY(idx) (((idx) & CH_PC_WAY_MASK) >> \ 1154 CH_PC_WAY_SHIFT) 1155 #define CH_PC_DATA_REG_SIZE 64 1156 #define CH_PCACHE_NWAY 4 1157 #define PN_PC_PARITY_SHIFT 50 1158 #define PN_PC_PARITY_MASK 0xff 1159 #define PN_PC_PARITY_BITS(status) \ 1160 (((status) >> PN_PC_PARITY_SHIFT) & PN_PC_PARITY_MASK) 1161 #define CH_PC_IDX_ADR(pcp) ((pcp->pc_idx & 0x1c0) >> 6) 1162 #define CH_PCTAG_ADDR_SHIFT 6 1163 #define CH_PC_PA_MASK 0x7ffffffffc0 1164 #define CH_PCTAG_TO_VA(tag) ((tag) << CH_PCTAG_ADDR_SHIFT) 1165 #define CH_PCSTAG_TO_PA(tag) (((tag) << CH_PCTAG_ADDR_SHIFT) & \ 1166 CH_PC_PA_MASK) 1167 #define CH_PCTAG_BNK0_VALID_MASK 0x2000000000000000 1168 #define CH_PCTAG_BNK1_VALID_MASK 0x1000000000000000 1169 #define CH_PCTAG_BNK0_INVALID(tag) (((tag) & CH_PCTAG_BNK0_VALID_MASK) == \ 1170 0) 1171 #define CH_PCTAG_BNK1_INVALID(tag) (((tag) & CH_PCTAG_BNK1_VALID_MASK) == \ 1172 0) 1173 1174 /* 1175 * CPU Log Out Structure parameters. 1176 * This structure is filled in by the Error Trap handlers and captures the 1177 * Ecache/Dcache/Icache line(s) associated with the AFAR. 1178 * For Cheetah Phase II, this structure is filled in at the TL=0 code. For 1179 * Cheetah Phase III, this will be filled in at the trap handlers. 1180 */ 1181 1182 /* 1183 * We use this to mark the LOGOUT structure as invalid. Note that 1184 * this cannot be a valid AFAR, as AFAR bits outside of [41:5] should always 1185 * be zero. 1186 */ 1187 #define LOGOUT_INVALID_U32 0xecc1ecc1 1188 #define LOGOUT_INVALID_L32 0xecc1ecc1 1189 #define LOGOUT_INVALID UINT64_C(0xecc1ecc1ecc1ecc1) 1190 1191 /* 1192 * Max number of TLs to support for Fast ECC or Cache Parity Errors 1193 * at TL>0. Traps are OK from TL=1-2, at TL>=3, we will Red Mode. 1194 */ 1195 #define CH_ERR_TL1_TLMAX 2 1196 1197 /* 1198 * Software traps used by TL>0 handlers. 1199 */ 1200 #define SWTRAP_0 0 /* Used by Fast ECC */ 1201 #define SWTRAP_1 1 /* Used by Dcache Parity */ 1202 #define SWTRAP_2 2 /* Used by Icache Parity */ 1203 1204 /* 1205 * Bit mask defines for various Cheetah Error conditions. 1206 */ 1207 #define CH_ERR_FECC 0x01 /* Data/Event is Fast ECC */ 1208 #define CH_ERR_IPE 0x02 /* Data/Event is Icache Parity Error */ 1209 #define CH_ERR_DPE 0x04 /* Data/Event is Dcache Parity Error */ 1210 #define CH_ERR_PANIC 0x08 /* Fatal error in TL>0 handler */ 1211 #define CH_ERR_TL 0x10 /* Error occured at TL>0 */ 1212 #define CH_ERR_ME_SHIFT 8 /* If multiple errors, shift left newest */ 1213 #define CH_ERR_ME_FLAGS(x) ((x) >> CH_ERR_ME_SHIFT) 1214 1215 /* 1216 * Defines for Bit8 (CH_ERR_TSTATE_IC_ON) and Bit9 (CH_ERR_TSTATE_DC_ON) 1217 * in %tstate, which is used to remember D$/I$ state on Fast ECC handler 1218 * at TL>0. Note that DCU_IC=0x1, DCU_DC=0x2. 1219 */ 1220 #define CH_ERR_G2_TO_TSTATE_SHFT 10 1221 #define CH_ERR_DCU_TO_TSTATE_SHFT 8 1222 #define CH_ERR_TSTATE_IC_ON (DCU_IC << CH_ERR_DCU_TO_TSTATE_SHFT) 1223 #define CH_ERR_TSTATE_DC_ON (DCU_DC << CH_ERR_DCU_TO_TSTATE_SHFT) 1224 1225 /* 1226 * Multiple offset TL>0 handler structure elements 1227 */ 1228 #define CH_ERR_TL1_DATA (CH_ERR_TL1_LOGOUT + CH_CLO_DATA) 1229 #define CH_ERR_TL1_SDW_DATA (CH_ERR_TL1_LOGOUT + CH_CLO_SDW_DATA) 1230 #define CH_ERR_TL1_NEST_CNT (CH_ERR_TL1_LOGOUT + CH_CLO_NEST_CNT) 1231 #define CH_ERR_TL1_AFAR (CH_ERR_TL1_DATA + CH_CHD_AFAR) 1232 #define CH_ERR_TL1_AFSR (CH_ERR_TL1_DATA + CH_CHD_AFSR) 1233 #define CH_ERR_TL1_SDW_AFAR (CH_ERR_TL1_SDW_DATA + CH_CHD_AFAR) 1234 #define CH_ERR_TL1_SDW_AFSR (CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR) 1235 #define CH_ERR_TL1_SDW_AFSR_EXT (CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR_EXT) 1236 1237 /* 1238 * Interval for deferred CEEN reenable 1239 */ 1240 #define CPU_CEEN_DELAY_SECS 6 1241 1242 /* 1243 * flags for flt_trapped_ce variable 1244 */ 1245 #define CE_CEEN_DEFER 0x1 /* no CEEN reenable in trap handler */ 1246 #define CE_CEEN_NODEFER 0x2 /* reenable CEEN in handler */ 1247 #define CE_CEEN_TIMEOUT 0x4 /* CE caught by timeout */ 1248 #define CE_CEEN_TRAPPED 0x8 /* CE caught by trap */ 1249 1250 /* 1251 * default value for cpu_ce_not_deferred 1252 */ 1253 #if defined(JALAPENO) || defined(SERRANO) 1254 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \ 1255 ~(C_AFSR_CE | C_AFSR_FRC | C_AFSR_RCE | C_AFSR_EMC)) 1256 #else /* JALAPENO || SERRANO */ 1257 #define CPU_CE_NOT_DEFERRED C_AFSR_CECC_ERRS & \ 1258 ~(C_AFSR_CE | C_AFSR_EMC) 1259 #endif /* JALAPENO || SERRANO */ 1260 1261 #define CPU_CE_NOT_DEFERRED_EXT C_AFSR_EXT_CECC_ERRS 1262 1263 #if defined(CHEETAH_PLUS) 1264 1265 /* 1266 * VA for primary and shadow AFSR/AFAR/AFSR_EXT registers 1267 */ 1268 #define ASI_SHADOW_REG_VA 0x8 1269 #define ASI_AFSR_EXT_VA 0x10 1270 #define ASI_SHADOW_AFSR_EXT_VA 0x18 1271 1272 /* 1273 * Bitmask for keeping track of core parking in ECC error handlers. 1274 * We share a register that also saves the DCUCR value so we use 1275 * one of the reserved bit positions of the DCUCR register to keep 1276 * track of whether or not we have parked our sibling core. 1277 */ 1278 #define PN_PARKED_OTHER_CORE 0x20 1279 #define PN_BOTH_CORES_RUNNING 0x3 1280 1281 /* 1282 * Panther EMU Activity Status Register Bits. 1283 */ 1284 #define ASI_EMU_ACT_STATUS_VA 0x18 1285 #define MCU_ACT_STATUS INT64_C(0x0000000000000001) 1286 #define SIU_ACT_STATUS INT64_C(0x0000000000000002) 1287 #endif /* CHEETAH_PLUS */ 1288 1289 #define ASI_CESR_ID_VA 0x40 /* ASI_CESRD_ID per-core registers */ 1290 1291 #define ASR_DISPATCH_CONTROL %asr18 1292 #define ASR_DISPATCH_CONTROL_BPE 0x20 1293 1294 /* 1295 * Max number of E$ sets logged in ch_diag_data structure 1296 */ 1297 #define CHD_EC_DATA_SETS 4 /* max 4 sets of E$ data */ 1298 1299 /* 1300 * Definitions for Panther TLB parity handling. 1301 */ 1302 #define PN_ITLB_NWAYS 2 1303 #define PN_NUM_512_ITLBS 1 1304 #define PN_DTLB_NWAYS 2 1305 #define PN_NUM_512_DTLBS 2 1306 #define PN_SFSR_PARITY_SHIFT 12 1307 #define PN_ITLB_PGSZ_SHIFT 22 1308 #define PN_ITLB_PGSZ_MASK (7 << PN_ITLB_PGSZ_SHIFT) 1309 #define PN_DTLB_PGSZ0_SHIFT 16 1310 #define PN_DTLB_PGSZ0_MASK (7 << PN_DTLB_PGSZ0_SHIFT) 1311 #define PN_DTLB_PGSZ1_SHIFT 19 1312 #define PN_DTLB_PGSZ1_MASK (7 << PN_DTLB_PGSZ1_SHIFT) 1313 #define PN_DTLB_PGSZ_MASK (PN_DTLB_PGSZ1_MASK | PN_DTLB_PGSZ0_MASK) 1314 #define PN_DTLB_T512_0 (2 << 16) 1315 #define PN_DTLB_T512_1 (3 << 16) 1316 #define PN_TLO_INFO_IMMU_SHIFT 14 1317 #define PN_TLO_INFO_IMMU (1 << PN_TLO_INFO_IMMU_SHIFT) 1318 #define PN_TLO_INFO_TL1_SHIFT 13 1319 #define PN_TLO_INFO_TL1 (1 << PN_TLO_INFO_TL1_SHIFT) 1320 #define PN_ITLB_T512 (2 << 16) 1321 #define PN_TLB_ACC_IDX_SHIFT 3 1322 #define PN_TLB_ACC_WAY_BIT (1 << 11) 1323 #define PN_TLB_DIAGACC_OFFSET 0x40000 /* Diag Acc ASI VA offset */ 1324 /* 1325 * tag parity = XOR(Size[2:0],Global,VA[63:21],Context[12:0]) 1326 * which requires looking at both the tag and the data. 1327 */ 1328 #define PN_TLB_TAG_PARITY_TAG_MASK 0xffffffffffe01fff 1329 #define PN_TLB_TAG_PARITY_DATA_MASK 0x6001400000000001 1330 /* data parity = XOR(NFO,IE,PA[42:13],CP,CV,E,P,W) */ 1331 #define PN_TLB_DATA_PARITY_DATA_MASK 0x180087ffffffe03e 1332 1333 #ifdef _KERNEL 1334 1335 #ifndef _ASM 1336 1337 #include <sys/kstat.h> 1338 1339 /* 1340 * One Ecache data element, 32 bytes of data, 8 bytes of ECC. 1341 * See Cheetah PRM 10.7.2. 1342 */ 1343 typedef struct ec_data_elm { 1344 uint64_t ec_d8[CH_ECACHE_STGREG_NUM]; 1345 uint64_t ec_eccd; /* EC_data_ECC field */ 1346 } ec_data_elm_t; 1347 1348 /* 1349 * L2 and L3 cache data captured by cpu log out code. 1350 * See Cheetah PRM 10.7.4. 1351 */ 1352 typedef struct ch_ec_data { 1353 uint64_t ec_logflag; /* Flag indicates if data was logged */ 1354 uint64_t ec_idx; /* Ecache index */ 1355 uint64_t ec_way; /* Ecache way */ 1356 uint64_t ec_tag; /* Ecache Tag */ 1357 uint64_t ec_tag_ecc; /* Ecache Tag ECC (Cheetah+ only) */ 1358 ec_data_elm_t ec_data[CH_ECACHE_SUBBLK_SIZE/CH_ECACHE_STGREG_SIZE]; 1359 } ch_ec_data_t; 1360 1361 /* 1362 * Dcache data captured by cpu log out code and get_dcache_dtag. 1363 * See Cheetah PRM 10.6.[1-4]. 1364 */ 1365 typedef struct ch_dc_data { 1366 uint64_t dc_logflag; /* Flag indicates if data was logged */ 1367 uint64_t dc_idx; /* Dcache index */ 1368 uint64_t dc_way; /* Dcache way */ 1369 uint64_t dc_tag; /* Tag/Valid Fields */ 1370 uint64_t dc_utag; /* Microtag */ 1371 uint64_t dc_sntag; /* Snoop Tag */ 1372 uint64_t dc_data[CH_DC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1373 uint64_t dc_pn_data_parity; /* Data parity bits for Panther */ 1374 } ch_dc_data_t; 1375 1376 /* 1377 * Icache data captured by cpu log out code and get_icache_dtag. 1378 * See Cheetah PRM 10.4.[1-3]. 1379 */ 1380 typedef struct ch_ic_data { 1381 uint64_t ic_logflag; /* Flag indicates if data was logged */ 1382 uint64_t ic_idx; /* Icache index */ 1383 uint64_t ic_way; /* Icache way */ 1384 uint64_t ic_patag; /* Physical address tag */ 1385 uint64_t ic_utag; /* Microtag */ 1386 uint64_t ic_upper; /* Upper valid/predict tag */ 1387 uint64_t ic_lower; /* Lower valid/predict tag */ 1388 uint64_t ic_sntag; /* Snoop Tag */ 1389 uint64_t ic_data[PN_IC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1390 } ch_ic_data_t; 1391 1392 /* 1393 * Pcache data captured by get_pcache_dtag 1394 */ 1395 typedef struct ch_pc_data { 1396 uint64_t pc_logflag; /* Flag indicates if data was logged */ 1397 uint64_t pc_idx; /* Pcache index */ 1398 uint64_t pc_way; /* Pcache way */ 1399 uint64_t pc_status; /* Pcache status data */ 1400 uint64_t pc_tag; /* Tag/Valid Fields */ 1401 uint64_t pc_sntag; /* Snoop Tag */ 1402 uint64_t pc_data[CH_PC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1403 } ch_pc_data_t; 1404 1405 /* 1406 * CPU Error State 1407 */ 1408 typedef struct ch_cpu_errors { 1409 uint64_t afsr; /* AFSR */ 1410 uint64_t afar; /* AFAR */ 1411 /* 1412 * The following registers don't exist on cheetah 1413 */ 1414 uint64_t shadow_afsr; /* Shadow AFSR */ 1415 uint64_t shadow_afar; /* Shadow AFAR */ 1416 uint64_t afsr_ext; /* AFSR1_EXT */ 1417 uint64_t shadow_afsr_ext; /* AFSR2_EXT */ 1418 uint64_t afar2; /* AFAR2 - Serrano only */ 1419 } ch_cpu_errors_t; 1420 1421 /* 1422 * CPU logout structures. 1423 * NOTE: These structures should be the same for Cheetah, Cheetah+, 1424 * Jaguar, Panther, and Jalapeno since the assembler code relies 1425 * on one set of offsets. Panther is the only processor that 1426 * uses the chd_l2_data field since it has both L3 and L2 caches. 1427 */ 1428 typedef struct ch_diag_data { 1429 uint64_t chd_afar; /* AFAR */ 1430 uint64_t chd_afsr; /* AFSR */ 1431 uint64_t chd_afsr_ext; /* AFSR_EXT */ 1432 uint64_t chd_afar2; /* AFAR2 - Serrano only */ 1433 ch_ec_data_t chd_ec_data[CHD_EC_DATA_SETS]; /* Ecache data */ 1434 ch_ec_data_t chd_l2_data[PN_L2_NWAYS]; /* L2 cache data */ 1435 ch_dc_data_t chd_dc_data; /* Dcache data */ 1436 ch_ic_data_t chd_ic_data; /* Icache data */ 1437 } ch_diag_data_t; 1438 1439 1440 /* 1441 * Top level CPU logout structure. 1442 * clo_flags is used to hold information such as trap type, trap level, 1443 * CEEN value, etc that is needed by the individual trap handlers. Not 1444 * all fields in this flag are used by all trap handlers but when they 1445 * are used, here's how they are laid out: 1446 * 1447 * |-------------------------------------------------------| 1448 * | | trap type | trap level | |UCEEN| |NCEEN|CEEN| 1449 * |-------------------------------------------------------| 1450 * 63 19 12 11 8 3 2 1 0 1451 * 1452 * Note that the *CEEN bits correspond exactly to the same bit positions 1453 * that are used in the error enable register. 1454 */ 1455 typedef struct ch_cpu_logout { 1456 uint64_t clo_flags; /* Information about this trap */ 1457 uint64_t clo_nest_cnt; /* To force an upper bound */ 1458 ch_diag_data_t clo_data; /* Diag data for primary AFAR */ 1459 ch_diag_data_t clo_sdw_data; /* Diag data for shadow AFAR */ 1460 } ch_cpu_logout_t; 1461 1462 typedef struct ch_tte_entry { 1463 uint64_t ch_tte_tag; 1464 uint64_t ch_tte_data; 1465 } ch_tte_entry_t; 1466 1467 /* 1468 * Top level CPU logout structure for TLB parity errors. 1469 * 1470 * tlo_logflag - Flag indicates if data was logged 1471 * tlo_info - Used to keep track of a number of values: 1472 * itlb pgsz - Page size of the VA whose lookup in the ITLB caused 1473 * the exception (from ASI_IMMU_TAG_ACCESS_EXT.) 1474 * dtlb pgsz1 - Page size of the VA whose lookup in the DTLB T512_1 1475 * caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.). 1476 * dtlb pgsz0 - Page size of the VA whose lookup in the DTLB T512_0 1477 * caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.). 1478 * immu - Trap is the result of an ITLB exception if immu == 1. 1479 * Otherwise, for DTLB exceptions immu == 0. 1480 * tl1 - Set to 1 if the exception occured at TL>0. 1481 * context - Context of the VA whose lookup in the TLB caused the 1482 * exception (from ASI_[I|D]MMU_TAG_ACCESS.) 1483 * |---------------------------------------------------------------------| 1484 * |...| itlb pgsz | dtlb pgsz1 | dtlb pgsz0 |...| immu | tl1 | context | 1485 * |---------------------------------------------------------------------| 1486 * 24 22 21 19 18 16 14 13 12 0 1487 * 1488 * tlo_addr - VA that cause the MMU exception trap. 1489 * tlo_pc - PC where the exception occured. 1490 * tlo_itlb_tte - TTEs that were in the ITLB after the trap at the index 1491 * specific to the VA and page size in question. 1492 * tlo_dtlb_tte - TTEs that were in the DTLB after the trap at the index 1493 * specific to the VA and page size in question. 1494 */ 1495 typedef struct pn_tlb_logout { 1496 uint64_t tlo_logflag; 1497 uint64_t tlo_info; 1498 uint64_t tlo_addr; 1499 uint64_t tlo_pc; 1500 ch_tte_entry_t tlo_itlb_tte[PN_ITLB_NWAYS * PN_NUM_512_ITLBS]; 1501 ch_tte_entry_t tlo_dtlb_tte[PN_DTLB_NWAYS * PN_NUM_512_DTLBS]; 1502 } pn_tlb_logout_t; 1503 1504 #if defined(CPU_IMP_L1_CACHE_PARITY) 1505 /* 1506 * Parity error logging structure. 1507 */ 1508 typedef union ch_l1_parity_log { 1509 struct { 1510 int cpl_way; /* Faulty line way */ 1511 int cpl_off; /* Faulty line offset */ 1512 int cpl_tag; /* Faulty tags list */ 1513 int cpl_lcnt; /* Faulty cache lines */ 1514 ch_dc_data_t cpl_dc[CH_DCACHE_NWAY]; /* D$ data nWays */ 1515 ch_pc_data_t cpl_pc[CH_PCACHE_NWAY]; /* P$ data nWays */ 1516 int cpl_cache; /* error in D$ or P$? */ 1517 } dpe; /* D$ parity error */ 1518 struct { 1519 int cpl_way; /* Faulty line way */ 1520 int cpl_off; /* Faulty line offset */ 1521 int cpl_tag; /* Faulty tags list */ 1522 int cpl_lcnt; /* Faulty cache lines */ 1523 ch_ic_data_t cpl_ic[CH_ICACHE_NWAY]; /* I$ data nWays */ 1524 } ipe; /* I$ parity error */ 1525 } ch_l1_parity_log_t; 1526 1527 #endif /* CPU_IMP_L1_CACHE_PARITY */ 1528 1529 /* 1530 * Error at TL>0 CPU logout data. 1531 * Needs some extra space to save %g registers and miscellaneous info. 1532 */ 1533 typedef struct ch_err_tl1_data { 1534 uint64_t ch_err_tl1_g1; /* Saved %g1 */ 1535 uint64_t ch_err_tl1_g2; /* Saved %g2 */ 1536 uint64_t ch_err_tl1_g3; /* Saved %g3 */ 1537 uint64_t ch_err_tl1_g4; /* Saved %g4 */ 1538 uint64_t ch_err_tl1_g5; /* Saved %g5 */ 1539 uint64_t ch_err_tl1_g6; /* Saved %g6 */ 1540 uint64_t ch_err_tl1_g7; /* Saved %g7 */ 1541 uint64_t ch_err_tl1_tpc; /* Trap PC */ 1542 uint64_t ch_err_tl1_flags; /* miscellaneous flags */ 1543 uint64_t ch_err_tl1_tmp; /* some handlers may use as tmp */ 1544 ch_cpu_logout_t ch_err_tl1_logout; /* logout */ 1545 } ch_err_tl1_data_t; 1546 1547 /* Indices into chsm_outstanding and friends */ 1548 #define CACHE_SCRUBBER_INFO_E 0 1549 #define CACHE_SCRUBBER_INFO_D 1 1550 #define CACHE_SCRUBBER_INFO_I 2 1551 1552 /* We define 3 scrubbers: E$, D$, and I$ */ 1553 #define CACHE_SCRUBBER_COUNT 3 1554 1555 /* 1556 * The ch_scrub_misc structure contains miscellaneous bookkeeping 1557 * items for scrubbing the I$, D$, and E$. 1558 * 1559 * For a description of the use of chsm_core_state and why it's not needed 1560 * on Jaguar, see the comment above cpu_scrub_cpu_setup() in us3_cheetahplus.c. 1561 */ 1562 typedef struct ch_scrub_misc { 1563 uint32_t chsm_outstanding[CACHE_SCRUBBER_COUNT]; 1564 /* outstanding requests */ 1565 int chsm_flush_index[CACHE_SCRUBBER_COUNT]; 1566 /* next line to flush */ 1567 int chsm_enable[CACHE_SCRUBBER_COUNT]; 1568 /* is this scrubber enabled on this core? */ 1569 int chsm_ecache_nlines; /* no. of E$ lines */ 1570 int chsm_ecache_busy; /* keeps track if cpu busy */ 1571 int chsm_icache_nlines; /* no. of I$ lines */ 1572 int chsm_core_state; /* which core the scrubber is */ 1573 /* running on (Panther only) */ 1574 } ch_scrub_misc_t; 1575 1576 /* 1577 * Cheetah module private data structure. One of these is allocated for 1578 * each valid cpu at setup time and is pointed to by the machcpu 1579 * "cpu_private" pointer. For Cheetah, we have the miscellaneous scrubber 1580 * variables and cpu log out structures for Fast ECC traps at TL=0, 1581 * Disrupting (correctable) traps and Deferred (asynchronous) traps. For 1582 * Disrupting traps only one log out structure is needed because we cannot 1583 * get a TL>0 disrupting trap since it obeys IE. For Deferred traps we 1584 * cannot get a TL>0 because we turn off NCEEN during log out capture. E$ 1585 * set size (E$ size / nways) is saved here to avoid repeated calculations. 1586 * NB: The ch_err_tl1_data_t structures cannot cross a page boundary 1587 * because we use physical addresses to access them. We ensure this 1588 * by allocating them near the front of cheetah_private_t, which is 1589 * aligned on PAGESIZE (8192) via kmem_cache_create, and by ASSERTing 1590 * sizeof (chpr_tl1_err_data) <= CH_ECACHE_MAX_LSIZE in the 1591 * cpu_init_private routines. 1592 * NB: chpr_icache_size and chpr_icache_linesize need to be at the front 1593 * of cheetah_private_t because putting them after chpr_tl1_err_data 1594 * would make their offsets > 4195. 1595 */ 1596 typedef struct cheetah_private { 1597 int chpr_icache_size; 1598 int chpr_icache_linesize; 1599 ch_err_tl1_data_t chpr_tl1_err_data[CH_ERR_TL1_TLMAX]; 1600 ch_scrub_misc_t chpr_scrub_misc; 1601 int chpr_ec_set_size; 1602 ch_cpu_logout_t chpr_fecctl0_logout; 1603 ch_cpu_logout_t chpr_cecc_logout; 1604 ch_cpu_logout_t chpr_async_logout; 1605 pn_tlb_logout_t chpr_tlb_logout; 1606 uint64_t chpr_fpras_timestamp[FPRAS_NCOPYOPS]; 1607 hrtime_t chpr_ceptnr_seltime; 1608 int chpr_ceptnr_id; 1609 } cheetah_private_t; 1610 1611 #endif /* _ASM */ 1612 1613 #endif /* _KERNEL */ 1614 1615 #ifdef __cplusplus 1616 } 1617 #endif 1618 1619 #endif /* _SYS_CHEETAHREGS_H */ 1620