xref: /titanic_50/usr/src/uts/sun4u/sunfire/sys/fhc.h (revision 3eae19d9cf3390cf5b75e10c9c1945fd36ad856a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_FHC_H
28 #define	_SYS_FHC_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #include <sys/types32.h>
37 #include <sys/dditypes.h>
38 
39 /* useful debugging stuff */
40 #define	FHC_ATTACH_DEBUG	0x1
41 #define	FHC_INTERRUPT_DEBUG	0x2
42 #define	FHC_REGISTERS_DEBUG	0x4
43 #define	FHC_CTLOPS_DEBUG	0x8
44 
45 #define	FHC_BOARDS 0
46 #define	FHC_CLOCKS 1
47 
48 /*
49  * OBP supplies us with 6 register sets for the FHC. The code for the fhc
50  * driver relies on these register sets being presented by the PROM in the
51  * order specified below. If this changes, the following comments must be
52  * revised and the code in fhc_init() must be changed to reflect these
53  * revisions.
54  *
55  * They are:
56  * 	0	FHC internal registers
57  * 	1	IGR Interrupt Group Number
58  *	2	FanFail IMR, ISMR
59  *	3	System IMR, ISMR
60  *	4	UART IMR, ISMR
61  *	5	TOD IMR, ISMR
62  */
63 
64 /*
65  * The offsets are defined as offsets from the base of the OBP register
66  * set which the register belongs to.
67  */
68 
69 /* Register set 0 */
70 #define	FHC_OFF_ID		0x0	/* FHC ID register */
71 #define	FHC_OFF_RCTRL		0x10	/* FHC Reset Control and Status */
72 #define	FHC_OFF_CTRL		0x20	/* FHC Control and Status */
73 #define	FHC_OFF_BSR		0x30	/* FHC Board Status Register */
74 #define	FHC_OFF_JTAG_CTRL	0xF0	/* JTAG Control Register */
75 #define	FHC_OFF_JTAG_CMD	0x100	/* JTAG Comamnd Register */
76 
77 /* Register sets 2-5, the ISMR offset is the same */
78 #define	FHC_OFF_ISMR		0x10	/* FHC Interrupt State Machine */
79 
80 /* Bit field defines for FHC Control and Status Register */
81 #define	FHC_CENTERDIS		0x00100000
82 
83 /* NOTE: this bit is only used by firmware and must always be cleared by OS */
84 #define	FHC_CSR_SYNC		0x00010000
85 #define	FHC_MOD_OFF		0x00008000
86 #define	FHC_ACDC_OFF		0x00004000
87 #define	FHC_FHC_OFF		0x00002000
88 #define	FHC_EPDA_OFF		0x00001000
89 #define	FHC_EPDB_OFF		0x00000800
90 #define	FHC_PS_OFF		0x00000400
91 #define	FHC_NOT_BRD_PRES	0x00000200
92 #define	FHC_LED_LEFT		0x00000040
93 #define	FHC_LED_MID		0x00000020
94 #define	FHC_LED_RIGHT		0x00000010
95 
96 /* Bit field defines for FHC Reset Control and Status Register */
97 #define	FHC_POR			0x80000000
98 #define	FHC_SOFT_POR		0x40000000
99 #define	FHC_SOFT_XIR		0x20000000
100 
101 /* Bit field defines for the JTAG control register. */
102 #define	JTAG_MASTER_EN		0x80000000
103 #define	JTAG_MASTER_NPRES	0x40000000
104 
105 
106 /* Macros for decoding UPA speed pins from the Board Status Register */
107 #define	CPU_0_PINS(bsr)		(((bsr) >> 10) & 0x7)
108 #define	CPU_1_PINS(bsr)		(((bsr) >> 7) & 0x7)
109 
110 #define	CID_REV_MASK		0x0fffffff
111 #define	ULTRAI_COMPID		0x0002502f
112 #define	ULTRAII_COMPID		0x0003602f
113 
114 /* Macro for extracting the "plus" bit from the Board Status Register */
115 #define	ISPLUSBRD(bsr)		(((bsr) & 1) == 0)
116 
117 /* Macros for physical access */
118 #define	FHC_OFFSET		0xf8000000ull
119 #define	FHC_REGOFF		0x800000ull
120 #define	FHC_OFF_IGN		0x2000ull
121 #define	FHC_OFF_SIM		0x6000ull
122 #define	FHC_OFF_SSM		0x6010ull
123 #define	FHC_OFF_UIM		0x8000ull
124 #define	FHC_OFF_USM		0x8010ull
125 #define	FHC_CTRL(board)		(FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
126 				FHC_REGOFF + FHC_OFF_CTRL)
127 #define	FHC_JTAG_CTRL(board)	(FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
128 				FHC_REGOFF + FHC_OFF_JTAG_CTRL)
129 #define	FHC_IGN(board)		(FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
130 				FHC_REGOFF + FHC_OFF_IGN)
131 #define	FHC_SIM(board)		(FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
132 				FHC_REGOFF + FHC_OFF_SIM)
133 #define	FHC_SSM(board)		(FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
134 				FHC_REGOFF + FHC_OFF_SSM)
135 #define	FHC_UIM(board)		(FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
136 				FHC_REGOFF + FHC_OFF_UIM)
137 #define	FHC_USM(board)		(FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
138 				FHC_REGOFF + FHC_OFF_USM)
139 
140 /*
141  * the foolowing defines are used for trans phy-addr to board number
142  */
143 #define	BOARD_PHYADDR_SHIFT	24
144 #define	CLOCKBOARD_PHYADDR_BITS	0x1fff8
145 #define	IO_BOARD_NUMBER_SHIFT	10
146 #define	IO_BOARD_NUMBER_MASK	0xf
147 
148 /*
149  * The following defines are used by the fhc driver to determine the
150  * difference between IO and CPU type boards. This will be replaced
151  * later by JTAG scan to determine board type.
152  */
153 
154 /* XXX */
155 #define	FHC_UPADATA64A		0x40000
156 #define	FHC_UPADATA64B		0x20000
157 /* XXX */
158 
159 /* Bit field defines for Board Status Register */
160 #define	FHC_DIAG_MODE		0x40
161 
162 /* Bit field defines for the FHC Board Status Register when on a disk board */
163 #define	FHC_FANFAIL		0x00000040
164 #define	FHC_SCSI_VDD_OK		0x00000001
165 
166 /* Size of temperature recording array */
167 #define	MAX_TEMP_HISTORY	16
168 
169 /* Maximum number of boards in system */
170 #define	MAX_BOARDS		16
171 
172 /* Maximum number of Board Power Supplies. */
173 #define	MAX_PS_COUNT		8
174 
175 /* Use predefined strings to name the kstats from this driver. */
176 #define	FHC_KSTAT_NAME		"fhc"
177 #define	CSR_KSTAT_NAMED		"csr"
178 #define	BSR_KSTAT_NAMED		"bsr"
179 
180 /*
181  * The following defines are for the AC chip, but are needed to be global,
182  * so have been put in the fhc header file.
183  */
184 
185 /*
186  * Most Sunfire ASICs have the chip rev encoded into bits 31-28 of the
187  * component ID register.
188  */
189 #define	CHIP_REV(c)	((c) >> 28)
190 
191 #ifndef _ASM
192 
193 /* Use predefined strings to name the kstats from this driver. */
194 
195 /* Bit field defines for Interrupt Mapping registers */
196 #define	IMR_VALID	((uint_t)1 << INR_EN_SHIFT) /* Mondo valid bit */
197 
198 /* Bit defines for Interrupt State Machine Register */
199 #define	INT_PENDING	3	/* state of the interrupt dispatch */
200 
201 struct intr_regs {
202 	volatile uint_t *mapping_reg;
203 	volatile uint_t *clear_reg;
204 	uint_t mapping_reg_cache;	/* cache current value for CPR */
205 };
206 
207 #define	BD_IVINTR_SHFT		0x7
208 
209 /*
210  * Convert the Board Number field in the FHC Board Status Register to
211  * a board number. The field in the register is bits 0,3-1 of the board
212  * number. Therefore a macro is necessary to extract the board number.
213  */
214 #define	FHC_BSR_TO_BD(bsr)	((((bsr) >> 16) & 0x1)  | \
215 				(((bsr) >> 12) & 0xE))
216 
217 #define	FHC_INO(ino) ((ino) & 0x7)
218 #define	FHC_CPU2BOARD(cpuid) ((cpuid) >> 1)
219 #define	FHC_CPU_IS_A(cpuid) (!((cpuid) & 1))
220 #define	FHC_CPU_IS_B(cpuid) ((cpuid) & 1)
221 #define	FHC_BOARD2CPU_A(board) ((board) << 1)
222 #define	FHC_BOARD2CPU_B(board) (((board) << 1) + 1)
223 #define	FHC_PS2BOARD(ps) ((((ps) & 0x6) << 1) | ((ps) & 0x1))
224 #define	FHC_BOARD2PS(board) ((((board) & 0xc) >> 1) | ((board) & 0x1))
225 #define	FHC_OTHER_CPU_ID(cpuid) ((cpuid) ^ 1)
226 
227 /* this base address is assumed to never map to real memory */
228 #define	FHC_BASE_NOMEM		(1ull << 40)
229 #define	FHC_MAX_ECACHE_SIZE	(16 * 1024 * 1024)
230 
231 #define	FHC_BOARD_0		0x1c000000000ull
232 #define	FHC_BOARD_SPAN		0x200000000ull
233 #define	FHC_DTAG_OFFSET		0xfa000000ull
234 #define	FHC_BOARD_BASE(cpuid)	(FHC_BOARD_0 + (cpuid) * FHC_BOARD_SPAN)
235 #define	FHC_DTAG_BASE(cpuid)	(FHC_BOARD_BASE(cpuid) + FHC_DTAG_OFFSET)
236 #define	FHC_DTAG_LOW		0x300000000ull
237 #define	FHC_DTAG_HIGH		0x3ull
238 #define	FHC_DTAG_SIZE		(16 * 1024 * 1024)
239 #define	FHC_DTAG_SKIP		64
240 
241 /*
242  * Each Sunfire CPU Board has 32Kbytes of SRAM on the FireHose Bus.
243  *
244  * The SRAM is allocated as follows:
245  *
246  * 0x1ff.f020.0000 - 0x1ff.f020.5fff  scratch/stacks
247  * 0x1ff.f020.6000 - 0x1ff.f020.67ff  reset info     (2K bytes)
248  * 0x1ff.f020.6800 - 0x1ff.f020.6fff  POST private   (2K bytes)
249  * 0x1ff.f020.7000 - 0x1ff.f020.77ff  OS private     (2K bytes)
250  * 0x1ff.f020.7800 - 0x1ff.f020.7fff  OBP private    (2K bytes)
251  */
252 #define	FHC_LOCAL_SRAM_BASE	0x1fff0200000ull
253 #define	FHC_GLOBAL_SRAM_BASE	0x1c0f8200000ull
254 #define	FHC_CPU2GLOBAL_SRAM(mid) \
255 			(FHC_GLOBAL_SRAM_BASE + (mid) * 0x200000000ull)
256 
257 #define	FHC_SRAM_OS_BASE	0x7000
258 #define	FHC_LOCAL_OS_PAGEBASE	((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \
259 				MMU_PAGEMASK)
260 #define	FHC_SRAM_OS_OFFSET	((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \
261 				MMU_PAGEOFFSET)
262 
263 #define	FHC_SHUTDOWN_WAIT_MSEC	1000
264 
265 #define	FHC_MAX_INO	4
266 
267 #define	FHC_SYS_INO		0x0
268 #define	FHC_UART_INO		0x1
269 #define	FHC_TOD_INO		0x2
270 #define	FHC_FANFAIL_INO		0x3
271 
272 /*
273  * Defines for the kstats created for passing temperature values and
274  * history out to user level programs. All temperatures passed out
275  * will be in degrees Centigrade, corrected for the board type the
276  * temperature was read from. Since each Board type has a different
277  * response curve for the A/D convertor, the temperatures are all
278  * calibrated inside the kernel.
279  */
280 
281 #define	OVERTEMP_KSTAT_NAME	"temperature"
282 
283 /*
284  * This kstat is used for manually overriding temperatures.
285  */
286 
287 #define	TEMP_OVERRIDE_KSTAT_NAME	"temperature override"
288 
289 /*
290  * Time averaging based method of recording temperature history.
291  * Higher level temperature arrays are composed of temperature averages
292  * of the array one level below. When the lower array completes a
293  * set of data, the data is averaged and placed into the higher
294  * level array. Then the lower level array is overwritten until
295  * it is once again complete, where the process repeats.
296  *
297  * This method gives a user a fine grained view of the last minute,
298  * and larger grained views of the temperature as one goes back in
299  * time.
300  *
301  * The time units for the longer samples are based on the value
302  * of the OVERTEMP_TIMEOUT_SEC and the number of elements in each
303  * of the arrays between level 1 and the higher level.
304  */
305 
306 #define	OVERTEMP_TIMEOUT_SEC	2
307 
308 /* definition of the clock board index */
309 #define	CLOCK_BOARD_INDEX	16
310 
311 #define	L1_SZ		30	/* # of OVERTEMP_TIMEOUT_SEC samples */
312 #define	L2_SZ		15	/* size of array for level 2 samples */
313 #define	L3_SZ		12	/* size of array for level 3 samples */
314 #define	L4_SZ		4	/* size of array for level 4 samples */
315 #define	L5_SZ		2	/* size of array for level 5 samples */
316 
317 /*
318  * Macros for determining when to do the temperature averaging of arrays.
319  */
320 #define	L2_INDEX(i)	((i) / L1_SZ)
321 #define	L2_REM(i)	((i) % L1_SZ)
322 #define	L3_INDEX(i)	((i) / (L1_SZ * L2_SZ))
323 #define	L3_REM(i)	((i) % (L1_SZ * L2_SZ))
324 #define	L4_INDEX(i)	((i) / (L1_SZ * L2_SZ * L3_SZ))
325 #define	L4_REM(i)	((i) % (L1_SZ * L2_SZ * L3_SZ))
326 #define	L5_INDEX(i)	((i) / (L1_SZ * L2_SZ * L3_SZ * L4_SZ))
327 #define	L5_REM(i)	((i) % (L1_SZ * L2_SZ * L3_SZ * L4_SZ))
328 
329 /*
330  * define for an illegal temperature. This temperature will never be seen
331  * in a real system, so it is used as an illegal value in the various
332  * functions processing the temperature data structure.
333  */
334 #define	NA_TEMP		0x7FFF
335 
336 /*
337  * State variable for board temperature. Each board has its own
338  * temperature state. State transitions from OK -> bad direction
339  * happen instantaneously, but use a counter in the opposite
340  * direction, so that noise in the A/D counters does not cause
341  * a large number of messages to appear.
342  */
343 enum temp_state {	TEMP_OK = 0,		/* normal board temperature */
344 			TEMP_WARN = 1,		/* start warning operator */
345 			TEMP_DANGER = 2 };	/* get ready to shutdown */
346 
347 /*
348  * Number of temperature poll counts to wait before printing that the
349  * system has cooled down.
350  */
351 #define	TEMP_STATE_TIMEOUT_SEC	20
352 #define	TEMP_STATE_COUNT	((TEMP_STATE_TIMEOUT_SEC) / \
353 				(OVERTEMP_TIMEOUT_SEC))
354 
355 /*
356  * Number of poll counts that a system temperature must be at or above danger
357  * temperature before system is halted and powers down.
358  */
359 #define	SHUTDOWN_TIMEOUT_SEC	20
360 #define	SHUTDOWN_COUNT		((SHUTDOWN_TIMEOUT_SEC) / \
361 				(OVERTEMP_TIMEOUT_SEC))
362 
363 /*
364  * State variable for temperature trend.  Each state represents the
365  * current temperature trend for a given device.
366  */
367 enum temp_trend {	TREND_UNKNOWN = 0,	/* Unknown temperature trend */
368 			TREND_RAPID_FALL = 1,	/* Rapidly falling temp. */
369 			TREND_FALL = 2,		/* Falling temperature */
370 			TREND_STABLE = 3,	/* Stable temperature */
371 			TREND_RISE = 4,		/* Rising temperature */
372 			TREND_RAPID_RISE = 5,   /* Rapidly rising temperature */
373 			TREND_NOISY = 6 };	/* Unknown trend (noisy) */
374 
375 /* Thresholds for temperature trend */
376 #define	NOISE_THRESH		2
377 #define	RAPID_RISE_THRESH	4
378 #define	RAPID_FALL_THRESH	4
379 
380 /*
381  * Main structure for passing the calibrated and time averaged temperature
382  * values to user processes. This structure is copied out via the kstat
383  * mechanism.
384  */
385 #define	TEMP_KSTAT_VERSION 3	/* version of temp_stats structure */
386 struct temp_stats {
387 	uint_t index;		/* index of current temperature */
388 	short l1[L1_SZ];	/* OVERTEMP_TIMEOUT_SEC samples */
389 	short l2[L2_SZ];	/* level 2 samples */
390 	short l3[L3_SZ];	/* level 3 samples */
391 	short l4[L4_SZ];	/* level 4 samples */
392 	short l5[L5_SZ];	/* level 5 samples */
393 	short max;		/* maximum temperature recorded */
394 	short min;		/* minimum temperature recorded */
395 	enum temp_state state;	/* state of board temperature */
396 	int temp_cnt;		/* counter for state changes */
397 	int shutdown_cnt;	/* counter for overtemp shutdown */
398 	int version;		/* version of this structure */
399 	enum temp_trend trend;	/* temperature trend for board */
400 	short override;		/* override temperature for testing */
401 };
402 
403 /* The variable fhc_cpu_warning_temp_threshold is initialized to this value. */
404 #define	FHC_CPU_WARNING_TEMP_THRESHOLD		45
405 
406 /*
407  * Fault list management.
408  *
409  * The following defines and enum definitions have been created to support
410  * the fault list (struct ft_list). These defines must match with the
411  * fault string table in fhc.c. If any faults are added, they must be
412  * added at the end of this list, and the table must be modified
413  * accordingly.
414  */
415 enum ft_type {
416 	FT_CORE_PS = 0,		/* Core power supply */
417 	FT_OVERTEMP,		/* Temperature */
418 	FT_AC_PWR,		/* AC power Supply */
419 	FT_PPS,			/* Peripheral Power Supply */
420 	FT_CLK_33,		/* System 3.3 Volt Power */
421 	FT_CLK_50,		/* System 5.0 Volt Power */
422 	FT_V5_P,		/* Peripheral 5V Power */
423 	FT_V12_P,		/* Peripheral 12V Power */
424 	FT_V5_AUX,		/* Auxiliary 5V Power */
425 	FT_V5_P_PCH,		/* Peripheral 5V Precharge */
426 	FT_V12_P_PCH,		/* Peripheral 12V Precharge */
427 	FT_V3_PCH,		/* System 3V Precharge */
428 	FT_V5_PCH,		/* System 5V Precharge */
429 	FT_PPS_FAN,		/* Peripheral Power Supply Fan */
430 	FT_RACK_EXH,		/* Rack Exhaust Fan */
431 	FT_DSK_FAN,		/* 4 (or 5) Slot Disk Fan */
432 	FT_AC_FAN,		/* AC Box Fan */
433 	FT_KEYSW_FAN,		/* Key Switch Fan */
434 	FT_INSUFFICIENT_POWER,	/* System has insufficient power */
435 	FT_PROM,		/* fault inherited from PROM */
436 	FT_HOT_PLUG,		/* hot plug unavailable */
437 	FT_TODFAULT		/* tod error detection */
438 };
439 
440 enum ft_class {
441 	FT_BOARD,
442 	FT_SYSTEM
443 };
444 
445 /*
446  * This extern allows other drivers to use the ft_str_table if they
447  * have fhc specified as a depends_on driver.
448  */
449 extern char *ft_str_table[];
450 
451 /* Maximum length of string table entries */
452 #define	MAX_FT_DESC	64
453 
454 #define	FT_LIST_KSTAT_NAME	"fault_list"
455 
456 /*
457  * The fault list structure is a structure for holding information on
458  * kernel detected faults. The fault list structures are linked into
459  * a list and the list is protected by the ftlist_mutex. There are
460  * also several routines for manipulating the fault list.
461  */
462 struct ft_list {
463 	int32_t unit;		/* unit number of faulting device */
464 	enum ft_type type;	/* type of faulting device */
465 	int32_t pad;		/* padding to replace old next pointer */
466 	enum ft_class fclass;	/* System or board class fault */
467 	time32_t create_time;	/* Time stamp at fault detection */
468 	char msg[MAX_FT_DESC];	/* fault string */
469 };
470 
471 /*
472  * Allow binary compatibility between ILP32 and LP64 by
473  * eliminating the next pointer and making ft_list a fixed size.
474  * The structure name "ft_list" remains unchanged for
475  * source compatibility of kstat applications.
476  */
477 struct ft_link_list {
478 	struct ft_list f;
479 	struct ft_link_list *next;
480 };
481 
482 /*
483  * Board list management.
484  *
485  * Enumerated types for defining type of system and clock
486  * boards. It is used by both the kernel and user programs.
487  */
488 enum board_type {
489 	UNINIT_BOARD = 0,		/* Uninitialized board type */
490 	UNKNOWN_BOARD,			/* Unknown board type */
491 	CPU_BOARD,			/* System board CPU(s) */
492 	MEM_BOARD,			/* System board no CPUs */
493 	IO_2SBUS_BOARD,			/* 2 SBus & SOC IO Board */
494 	IO_SBUS_FFB_BOARD,		/* SBus & FFB SOC IO Board */
495 	IO_PCI_BOARD,			/* PCI IO Board */
496 	DISK_BOARD,			/* Disk Drive Board */
497 	CLOCK_BOARD,			/* System Clock board */
498 	IO_2SBUS_SOCPLUS_BOARD,		/* 2 SBus & SOC+ IO board */
499 	IO_SBUS_FFB_SOCPLUS_BOARD	/* SBus&FFB&SOC+ board */
500 };
501 
502 /*
503  * Defined strings for comparing with OBP board-type property. If OBP ever
504  * changes the board-type properties, these string defines must be changed
505  * as well.
506  */
507 #define	CPU_BD_NAME			"cpu"
508 #define	MEM_BD_NAME			"mem"
509 #define	IO_2SBUS_BD_NAME		"dual-sbus"
510 #define	IO_SBUS_FFB_BD_NAME		"upa-sbus"
511 #define	IO_PCI_BD_NAME			"dual-pci"
512 #define	DISK_BD_NAME			"disk"
513 #define	IO_2SBUS_SOCPLUS_BD_NAME	"dual-sbus-soc+"
514 #define	IO_SBUS_FFB_SOCPLUS_BD_NAME	"upa-sbus-soc+"
515 
516 /*
517  * The following structures and union are needed because the bd_info
518  * structure describes all types of system boards.
519  * XXX - We cannot determine Spitfire rev from JTAG scan, so it is
520  * left blank for now. Future implementations might fill in this info.
521  */
522 struct cpu_info {
523 	int cpu_rev;		/* CPU revision */
524 	int cpu_speed;		/* rated speed of CPU in MHz */
525 	int cpu_compid;		/* CPU component ID */
526 	int sdb0_compid;	/* SDB component ID */
527 	int sdb1_compid;	/* SDB component ID */
528 	int ec_compid;		/* Ecache RAM ID, needed for cache size */
529 	int cache_size;		/* Cache size in bytes */
530 	int cpu_sram_mode;	/* module's sram mode */
531 	int cpu_detected;	/* Something on the CPU JTAG ring. */
532 };
533 
534 struct io1_info {
535 	int sio0_compid;	/* Sysio component ID */
536 	int sio1_compid;	/* Sysio component ID */
537 	int hme_compid;		/* several revs in existence */
538 	int soc_compid;		/* SOC */
539 };
540 
541 struct io1plus_info {
542 	int sio0_compid;	/* Sysio component ID */
543 	int sio1_compid;	/* Sysio component ID */
544 	int hme_compid;		/* several revs in existence */
545 	int socplus_compid;	/* SOC+ */
546 };
547 
548 /* Defines for the FFB size field */
549 #define	FFB_FAILED	-1
550 #define	FFB_NOT_FOUND	0
551 #define	FFB_SINGLE	1
552 #define	FFB_DOUBLE	2
553 
554 struct io2_info {
555 	int fbc_compid;		/* FBC component ID */
556 	int ffb_size;		/* not present, single or dbl buffered */
557 	int sio1_compid;	/* Sysio component ID */
558 	int hme_compid;		/* several revs in existence */
559 	int soc_compid;		/* SOC component ID */
560 };
561 
562 struct io2plus_info {
563 	int fbc_compid;		/* FBC component ID */
564 	int ffb_size;		/* not present, single or dbl buffered */
565 	int sio1_compid;	/* Sysio component ID */
566 	int hme_compid;		/* several revs in existence */
567 	int socplus_compid;	/* or SOC+ component ID */
568 };
569 
570 struct io3_info {
571 	int psyo0_compid;	/* Psycho+ component ID */
572 	int psyo1_compid;	/* Psycho+ component ID */
573 	int cheo_compid;	/* Cheerio component ID */
574 };
575 
576 struct dsk_info {
577 	int disk_pres[2];
578 	int disk_id[2];
579 };
580 
581 union bd_un {
582 	struct cpu_info cpu[2];
583 	struct io1_info io1;
584 	struct io2_info io2;
585 	struct io3_info io3;
586 	struct dsk_info dsk;
587 	struct io1plus_info io1plus;
588 	struct io2plus_info io2plus;
589 };
590 
591 /*
592  * board_state and bd_info are maintained for backward
593  * compatibility with prtdiag and others user programs that may rely
594  * on them.
595  */
596 enum board_state {
597 	UNKNOWN_STATE = 0,	/* Unknown board */
598 	ACTIVE_STATE,		/* active and working */
599 	HOTPLUG_STATE,		/* Hot plugged board */
600 	LOWPOWER_STATE, 	/* Powered down board */
601 	DISABLED_STATE,		/* Board disabled by PROM */
602 	FAILED_STATE		/* Board failed by POST */
603 };
604 
605 struct bd_info {
606 	enum board_type type;		/* Type of board */
607 	enum board_state state;		/* current state of this board */
608 	int board;			/* board number */
609 	int fhc_compid;			/* fhc component id */
610 	int ac_compid;			/* ac component id */
611 	char prom_rev[64];		/* best guess as to what is needed */
612 	union bd_un bd;
613 };
614 
615 /*
616  * Config admin interface.
617  *
618  * Receptacle states.
619  */
620 typedef enum {
621 	SYSC_CFGA_RSTATE_EMPTY = 0,		/* Empty state */
622 	SYSC_CFGA_RSTATE_DISCONNECTED,		/* DISCONNECTED state */
623 	SYSC_CFGA_RSTATE_CONNECTED		/* CONNECTED state */
624 } sysc_cfga_rstate_t;
625 
626 /*
627  * Occupant states.
628  */
629 typedef enum {
630 	SYSC_CFGA_OSTATE_UNCONFIGURED = 0,	/* UNCONFIGURED state */
631 	SYSC_CFGA_OSTATE_CONFIGURED		/* CONFIGURED state */
632 } sysc_cfga_ostate_t;
633 
634 /*
635  * Receptacle/Occupant condition.
636  */
637 typedef enum {
638 	SYSC_CFGA_COND_UNKNOWN = 0,	/* Unknown condition */
639 	SYSC_CFGA_COND_OK,		/* Condition OK */
640 	SYSC_CFGA_COND_FAILING,		/* Failing */
641 	SYSC_CFGA_COND_FAILED,		/* Failed */
642 	SYSC_CFGA_COND_UNUSABLE		/* Unusable */
643 } sysc_cfga_cond_t;
644 
645 /*
646  * Error definitions for CFGADM platform library
647  */
648 typedef enum {
649 	SYSC_ERR_DEFAULT = 0,	/* generic errors */
650 	SYSC_ERR_INTRANS,	/* hardware in transition */
651 	SYSC_ERR_UTHREAD,	/* can't stop user thread */
652 	SYSC_ERR_KTHREAD,	/* can't stop kernel thread */
653 	SYSC_ERR_SUSPEND,	/* can't suspend a device */
654 	SYSC_ERR_RESUME,	/* can't resume a device */
655 	SYSC_ERR_POWER,		/* not enough power for slot */
656 	SYSC_ERR_COOLING,	/* not enough cooling for slot */
657 	SYSC_ERR_PRECHARGE,	/* not enough precharge for slot */
658 	SYSC_ERR_HOTPLUG,	/* Hot Plug Unavailable */
659 	SYSC_ERR_HW_COMPAT,	/* incompatible hardware found during dr */
660 	SYSC_ERR_NON_DR_PROM,	/* prom not support Dynamic Reconfiguration */
661 	SYSC_ERR_CORE_RESOURCE,	/* core resource cannot be removed */
662 	SYSC_ERR_PROM,		/* error encountered in OBP/POST */
663 	SYSC_ERR_DR_INIT,	/* error encountered in sysc_dr_init op */
664 	SYSC_ERR_NDI_ATTACH,	/* error encountered in NDI attach operations */
665 	SYSC_ERR_NDI_DETACH,	/* error encountered in NDI detach operations */
666 	SYSC_ERR_RSTATE,	/* wrong receptacle state */
667 	SYSC_ERR_OSTATE,	/* wrong occupant state */
668 	SYSC_ERR_COND		/* invalid condition */
669 } sysc_err_t;
670 
671 /*
672  * Config admin structure.
673  */
674 typedef struct sysc_cfga_stat {
675 	/* generic representation of the attachment point below */
676 	sysc_cfga_rstate_t rstate;	/* current receptacle state */
677 	sysc_cfga_ostate_t ostate;	/* current occupant state */
678 	sysc_cfga_cond_t condition;	/* current board condition */
679 	time32_t last_change;		/* last state/condition change */
680 	uint_t in_transition:1;		/* board is in_transition */
681 
682 	/* platform specific below */
683 	enum board_type type;		/* Type of board */
684 	int board;			/* board number */
685 	int fhc_compid;			/* fhc component id */
686 	int ac_compid;			/* ac component id */
687 	char prom_rev[64];		/* best guess as to what is needed */
688 	union bd_un bd;
689 	uint_t no_detach:1;		/* board is non_detachable */
690 	uint_t plus_board:1;		/* board is 98 MHz capable */
691 } sysc_cfga_stat_t;
692 
693 /*
694  * Config admin command structure for SYSC_CFGA ioctls.
695  */
696 typedef struct sysc_cfga_cmd {
697 	uint_t		force:1;	/* force this state transition */
698 	uint_t		test:1;		/* Need to test hardware */
699 	int		arg;		/* generic data for test */
700 	sysc_err_t	errtype;	/* error code returned */
701 	char		*outputstr;	/* output returned from ioctl */
702 } sysc_cfga_cmd_t;
703 
704 typedef struct sysc_cfga_cmd32 {
705 	uint_t		force:1;	/* force this state transition */
706 	uint_t		test:1;		/* Need to test hardware */
707 	int		arg;		/* generic data for test */
708 	sysc_err_t	errtype;	/* error code returned */
709 	caddr32_t	outputstr;	/* output returned from ioctl */
710 } sysc_cfga_cmd32_t;
711 
712 typedef struct sysc_cfga_pkt {
713 	sysc_cfga_cmd_t	cmd_cfga;
714 	char		*errbuf;	/* internal error buffer */
715 } sysc_cfga_pkt_t;
716 
717 /*
718  * Sysctrl DR sequencer interface.
719  */
720 typedef struct sysc_dr_handle {
721 	dev_info_t **dip_list;		/* list of top dips for board */
722 	int dip_list_len;		/* length devinfo list */
723 	int flags;			/* dr specific flags */
724 	int error;			/* dr operation error */
725 	char *errstr;			/* dr config/unfig error message */
726 } sysc_dr_handle_t;
727 
728 #define	SYSC_DR_MAX_NODE	32
729 #define	SYSC_DR_FHC		0x1	/* connect phase init (fhc) */
730 #define	SYSC_DR_DEVS		0x2	/* config phase init (devices) */
731 #define	SYSC_DR_FORCE		0x4	/* force detach */
732 #define	SYSC_DR_REMOVE		0x8	/* remove dev_info */
733 
734 #define	SYSC_DR_HANDLE_FHC	0x0
735 #define	SYSC_DR_HANDLE_DEVS	0x1
736 
737 /*
738  * Sysctrl event interface.
739  */
740 typedef enum sysc_evt {
741 	SYSC_EVT_BD_EMPTY = 0,
742 	SYSC_EVT_BD_PRESENT,
743 	SYSC_EVT_BD_DISABLED,
744 	SYSC_EVT_BD_FAILED,
745 	SYSC_EVT_BD_OVERTEMP,
746 	SYSC_EVT_BD_TEMP_OK,
747 	SYSC_EVT_BD_PS_CHANGE,
748 	SYSC_EVT_BD_INS_FAILED,
749 	SYSC_EVT_BD_INSERTED,
750 	SYSC_EVT_BD_REMOVED,
751 	SYSC_EVT_BD_HP_DISABLED,
752 	SYSC_EVT_BD_CORE_RESOURCE_DISCONNECT
753 } sysc_evt_t;
754 
755 /*
756  * sysctrl audit message events
757  */
758 typedef enum sysc_audit_evt {
759 	SYSC_AUDIT_RSTATE_EMPTY = 0,
760 	SYSC_AUDIT_RSTATE_CONNECT,
761 	SYSC_AUDIT_RSTATE_DISCONNECT,
762 	SYSC_AUDIT_RSTATE_SUCCEEDED,
763 	SYSC_AUDIT_RSTATE_EMPTY_FAILED,
764 	SYSC_AUDIT_RSTATE_CONNECT_FAILED,
765 	SYSC_AUDIT_RSTATE_DISCONNECT_FAILED,
766 	SYSC_AUDIT_OSTATE_CONFIGURE,
767 	SYSC_AUDIT_OSTATE_UNCONFIGURE,
768 	SYSC_AUDIT_OSTATE_SUCCEEDED,
769 	SYSC_AUDIT_OSTATE_CONFIGURE_FAILED,
770 	SYSC_AUDIT_OSTATE_UNCONFIGURE_FAILED
771 } sysc_audit_evt_t;
772 
773 typedef struct {
774 	void (*update)(void *, sysc_cfga_stat_t *, sysc_evt_t);
775 	void *soft;
776 } sysc_evt_handle_t;
777 
778 void fhc_bd_sc_register(void f(void *, sysc_cfga_stat_t *, sysc_evt_t), void *);
779 
780 /*
781  * The board list structure is the central storage for the kernel's
782  * knowledge of normally booted and hotplugged boards.
783  */
784 typedef struct bd_list {
785 	struct fhc_soft_state *softsp;	/* handle for DDI soft state */
786 	sysc_cfga_stat_t sc;		/* board info */
787 	sysc_dr_handle_t sh[2];		/* sysctrl dr interface */
788 	void *dev_softsp;		/* opaque pointer to device state */
789 	void *ac_softsp;		/* opaque pointer to our AC */
790 	struct kstat *ksp;		/* pointer used in kstat destroy */
791 	int fault;			/* failure on this board? */
792 	int flags;			/* board state flags */
793 } fhc_bd_t;
794 
795 /*
796  * Fhc_bd.c holds 2 resizable arrays of boards. First for clock
797  * boards under central and second for normally booted and
798  * hotplugged boards.
799  */
800 typedef struct resizable_bd_list {
801 	fhc_bd_t **boards;
802 	int size;
803 	int last;
804 	int sorted;
805 } fhc_bd_resizable_t;
806 
807 #define	BDF_VALID		0x1			/* board entry valid */
808 #define	BDF_DETACH		0x2			/* board detachable */
809 #define	BDF_DISABLED		0x4			/* board disabled */
810 
811 #define	SYSC_OUTPUT_LEN		MAXPATHLEN		/* output str len */
812 
813 /*
814  * Board list management interface.
815  */
816 int			fhc_max_boards(void);
817 void		fhc_bdlist_init(void);
818 void		fhc_bdlist_fini(void);
819 void		fhc_bdlist_prime(int, int, int);
820 fhc_bd_t	*fhc_bdlist_lock(int);
821 void		fhc_bdlist_unlock(void);
822 
823 void		fhc_bd_init(struct fhc_soft_state *, int, enum board_type);
824 fhc_bd_t 	*fhc_bd(int);
825 fhc_bd_t	*fhc_bd_clock(void);
826 fhc_bd_t 	*fhc_bd_first(void);
827 fhc_bd_t 	*fhc_bd_next(fhc_bd_t *);
828 enum board_type	fhc_bd_type(int);
829 char 		*fhc_bd_typestr(enum board_type);
830 int		fhc_bd_valid(int);
831 int		fhc_bd_detachable(int);
832 
833 int		fhc_bd_insert_scan(void);
834 int		fhc_bd_remove_scan(void);
835 int		fhc_bd_test(int, sysc_cfga_pkt_t *);
836 int		fhc_bd_test_set_cond(int, sysc_cfga_pkt_t *);
837 void		fhc_bd_update(int, sysc_evt_t);
838 void		fhc_bd_env_set(int, void *);
839 
840 int		fhc_bdlist_locked(void);
841 int		fhc_bd_busy(int);
842 int		fhc_bd_is_jtag_master(int);
843 int		fhc_bd_is_plus(int);
844 
845 #if defined(_KERNEL)
846 
847 /*
848  * In order to indicate that we are in an environmental chamber, or
849  * oven, the test people will set the 'mfg-mode' property in the
850  * options node to 'chamber'. Therefore we have the following define.
851  */
852 #define	CHAMBER_VALUE	"chamber"
853 
854 /*
855  * zs design for fhc has two zs' interrupting on same interrupt mondo
856  * This requires us to poll for zs and zs alone. The poll list has been
857  * defined as a fixed size for simplicity.
858  */
859 #define	MAX_ZS_CNT	2
860 
861 /* FHC Interrupt routine wrapper structure */
862 struct fhc_wrapper_arg {
863 	struct fhc_soft_state *softsp;
864 	volatile uint_t *clear_reg;
865 	volatile uint_t *mapping_reg;
866 	dev_info_t *child;
867 	uint32_t inum;
868 	uint_t (*funcp)(caddr_t, caddr_t);
869 	caddr_t arg1;
870 	caddr_t arg2;
871 };
872 
873 /*
874  * The JTAG master command structure. It contains the address of the
875  * the JTAG controller on this system board. The controller can only
876  * be used if this FHC holds the JTAG master signal. This is checked
877  * by reading the JTAG control register on this FHC.
878  */
879 struct jt_mstr {
880 	volatile uint_t *jtag_cmd;
881 	int is_master;
882 	kmutex_t lock;
883 };
884 
885 /* Functions exported to manage the fault list */
886 void reg_fault(int, enum ft_type, enum ft_class);
887 void clear_fault(int, enum ft_type, enum ft_class);
888 int process_fault_list(void);
889 void create_ft_kstats(int);
890 
891 /* memloc's are protected under the bdlist lock */
892 struct fhc_memloc {
893 	struct fhc_memloc *next;
894 	int		board;		/* reference our board element */
895 	uint_t		pa;		/* base PA of this segment (in MB) */
896 	uint_t		size;		/* size of this segment (in MB) */
897 };
898 
899 /* Functions used to manage memory 'segments' */
900 #define	FHC_MEMLOC_SHIFT	20
901 #define	FHC_MEMLOC_MAX		(0x10000000000ull >> FHC_MEMLOC_SHIFT)
902 void fhc_add_memloc(int board, uint64_t pa, uint_t size);
903 void fhc_del_memloc(int board);
904 uint64_t fhc_find_memloc_gap(uint_t size);
905 void fhc_program_memory(int board, uint64_t base);
906 
907 /* Structures used in the driver to manage the hardware */
908 struct fhc_soft_state {
909 	dev_info_t *dip;		/* dev info of myself */
910 	struct bd_list *list;		/* pointer to board list entry */
911 	int is_central;			/* A central space instance of FHC */
912 	volatile uint_t *id;		/* FHC ID register */
913 	volatile uint_t *rctrl;		/* FHC Reset Control and Status */
914 	volatile uint_t *bsr;		/* FHC Board Status register */
915 	volatile uint_t *jtag_ctrl;	/* JTAG Control register */
916 	volatile uint_t *igr;		/* Interrupt Group Number */
917 	struct intr_regs intr_regs[FHC_MAX_INO];
918 	struct fhc_wrapper_arg poll_list[MAX_ZS_CNT];
919 	struct fhc_wrapper_arg *intr_list[FHC_MAX_INO];
920 	kmutex_t poll_list_lock;
921 	uchar_t spurious_zs_cntr;	/* Spurious counter for zs devices */
922 	kmutex_t pokefault_mutex;
923 	int pokefault;
924 
925 	/* this lock protects the following data */
926 	/* ! non interrupt use only ! */
927 	kmutex_t ctrl_lock;		/* lock for access to FHC CSR */
928 	volatile uint_t *ctrl;		/* FHC Control and Status */
929 
930 	/* The JTAG master structure has internal locking */
931 	struct jt_mstr jt_master;
932 
933 	/* the pointer to the kstat is stored for deletion upon detach */
934 	kstat_t *fhc_ksp;
935 };
936 
937 /*
938  * Function shared with child drivers which require fhc
939  * support. They gain access to this function through the use of the
940  * _depends_on variable.
941  */
942 enum board_type get_board_type(int board);
943 void update_temp(dev_info_t *pdip, struct temp_stats *envstat, uchar_t value);
944 enum temp_trend temp_trend(struct temp_stats *);
945 void fhc_reboot(void);
946 int overtemp_kstat_update(kstat_t *ksp, int rw);
947 int temp_override_kstat_update(kstat_t *ksp, int rw);
948 void init_temp_arrays(struct temp_stats *envstat);
949 void update_board_leds(fhc_bd_t *, uint_t, uint_t);
950 struct jt_mstr *jtag_master_lock(void);
951 void jtag_master_unlock(struct jt_mstr *);
952 extern int fhc_board_poweroffcpus(int board, char *errbuf, int cpu_flags);
953 
954 
955 /* FHC interrupt specification */
956 struct fhcintrspec {
957 	uint_t mondo;
958 	uint_t pil;
959 	dev_info_t *child;
960 	struct fhc_wrapper_arg *handler_arg;
961 };
962 
963 /* kstat structure used by fhc to pass data to user programs. */
964 struct fhc_kstat {
965 	struct kstat_named csr;	/* FHC Control and Status Register */
966 	struct kstat_named bsr;	/* FHC Board Status Register */
967 };
968 
969 #endif	/* _KERNEL */
970 
971 #endif /* _ASM */
972 
973 #ifdef	__cplusplus
974 }
975 #endif
976 
977 #endif	/* _SYS_FHC_H */
978