125cf1a30Sjl139090 /*
225cf1a30Sjl139090 * CDDL HEADER START
325cf1a30Sjl139090 *
425cf1a30Sjl139090 * The contents of this file are subject to the terms of the
525cf1a30Sjl139090 * Common Development and Distribution License (the "License").
625cf1a30Sjl139090 * You may not use this file except in compliance with the License.
725cf1a30Sjl139090 *
825cf1a30Sjl139090 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
925cf1a30Sjl139090 * or http://www.opensolaris.org/os/licensing.
1025cf1a30Sjl139090 * See the License for the specific language governing permissions
1125cf1a30Sjl139090 * and limitations under the License.
1225cf1a30Sjl139090 *
1325cf1a30Sjl139090 * When distributing Covered Code, include this CDDL HEADER in each
1425cf1a30Sjl139090 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1525cf1a30Sjl139090 * If applicable, add the following below this CDDL HEADER, with the
1625cf1a30Sjl139090 * fields enclosed by brackets "[]" replaced with your own identifying
1725cf1a30Sjl139090 * information: Portions Copyright [yyyy] [name of copyright owner]
1825cf1a30Sjl139090 *
1925cf1a30Sjl139090 * CDDL HEADER END
2025cf1a30Sjl139090 */
2125cf1a30Sjl139090 /*
22*4cca9c84SDave Plauger * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
2325cf1a30Sjl139090 */
2425cf1a30Sjl139090
2525cf1a30Sjl139090 #include <sys/cpuvar.h>
2625cf1a30Sjl139090 #include <sys/systm.h>
2725cf1a30Sjl139090 #include <sys/sysmacros.h>
2825cf1a30Sjl139090 #include <sys/promif.h>
2925cf1a30Sjl139090 #include <sys/platform_module.h>
3025cf1a30Sjl139090 #include <sys/cmn_err.h>
3125cf1a30Sjl139090 #include <sys/errno.h>
3225cf1a30Sjl139090 #include <sys/machsystm.h>
3325cf1a30Sjl139090 #include <sys/bootconf.h>
3425cf1a30Sjl139090 #include <sys/nvpair.h>
3525cf1a30Sjl139090 #include <sys/kobj.h>
3625cf1a30Sjl139090 #include <sys/mem_cage.h>
3725cf1a30Sjl139090 #include <sys/opl.h>
3825cf1a30Sjl139090 #include <sys/scfd/scfostoescf.h>
3925cf1a30Sjl139090 #include <sys/cpu_sgnblk_defs.h>
4025cf1a30Sjl139090 #include <sys/utsname.h>
4125cf1a30Sjl139090 #include <sys/ddi.h>
4225cf1a30Sjl139090 #include <sys/sunndi.h>
4325cf1a30Sjl139090 #include <sys/lgrp.h>
4425cf1a30Sjl139090 #include <sys/memnode.h>
4525cf1a30Sjl139090 #include <sys/sysmacros.h>
46e603b7d4Spm145316 #include <sys/time.h>
47e603b7d4Spm145316 #include <sys/cpu.h>
48ca3e8d88SDave Plauger #include <sys/dumphdr.h>
4925cf1a30Sjl139090 #include <vm/vm_dep.h>
5025cf1a30Sjl139090
5125cf1a30Sjl139090 int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *);
520cc8ae86Sav145390 int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp);
530cc8ae86Sav145390 int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp);
540cc8ae86Sav145390 int (*opl_get_mem_addr)(char *unum, char *sid,
550cc8ae86Sav145390 uint64_t offset, uint64_t *paddr);
5625cf1a30Sjl139090
5725cf1a30Sjl139090 /* Memory for fcode claims. 16k times # maximum possible IO units */
5825cf1a30Sjl139090 #define EFCODE_SIZE (OPL_MAX_BOARDS * OPL_MAX_IO_UNITS_PER_BOARD * 0x4000)
5925cf1a30Sjl139090 int efcode_size = EFCODE_SIZE;
6025cf1a30Sjl139090
6125cf1a30Sjl139090 #define OPL_MC_MEMBOARD_SHIFT 38 /* Boards on 256BG boundary */
6225cf1a30Sjl139090
6325cf1a30Sjl139090 /* Set the maximum number of boards for DR */
6425cf1a30Sjl139090 int opl_boards = OPL_MAX_BOARDS;
6525cf1a30Sjl139090
6625cf1a30Sjl139090 void sgn_update_all_cpus(ushort_t, uchar_t, uchar_t);
6725cf1a30Sjl139090
6825cf1a30Sjl139090 extern int tsb_lgrp_affinity;
6925cf1a30Sjl139090
7025cf1a30Sjl139090 int opl_tsb_spares = (OPL_MAX_BOARDS) * (OPL_MAX_PCICH_UNITS_PER_BOARD) *
7125cf1a30Sjl139090 (OPL_MAX_TSBS_PER_PCICH);
7225cf1a30Sjl139090
7325cf1a30Sjl139090 pgcnt_t opl_startup_cage_size = 0;
7425cf1a30Sjl139090
753f1fa9a7Sjfrank /*
763f1fa9a7Sjfrank * The length of the delay in seconds in communication with XSCF after
773f1fa9a7Sjfrank * which the warning message will be logged.
783f1fa9a7Sjfrank */
793f1fa9a7Sjfrank uint_t xscf_connect_delay = 60 * 15;
803f1fa9a7Sjfrank
811e2e7a75Shuah static opl_model_info_t opl_models[] = {
82195196c6Ssubhan { "FF1", OPL_MAX_BOARDS_FF1, FF1, STD_DISPATCH_TABLE },
83195196c6Ssubhan { "FF2", OPL_MAX_BOARDS_FF2, FF2, STD_DISPATCH_TABLE },
84195196c6Ssubhan { "DC1", OPL_MAX_BOARDS_DC1, DC1, STD_DISPATCH_TABLE },
85195196c6Ssubhan { "DC2", OPL_MAX_BOARDS_DC2, DC2, EXT_DISPATCH_TABLE },
86195196c6Ssubhan { "DC3", OPL_MAX_BOARDS_DC3, DC3, EXT_DISPATCH_TABLE },
8778ed97a7Sjl139090 { "IKKAKU", OPL_MAX_BOARDS_IKKAKU, IKKAKU, STD_DISPATCH_TABLE },
881e2e7a75Shuah };
891e2e7a75Shuah static int opl_num_models = sizeof (opl_models)/sizeof (opl_model_info_t);
901e2e7a75Shuah
91195196c6Ssubhan /*
9272b9fce9Ssubhan * opl_cur_model
93195196c6Ssubhan */
9472b9fce9Ssubhan static opl_model_info_t *opl_cur_model = NULL;
951e2e7a75Shuah
9625cf1a30Sjl139090 static struct memlist *opl_memlist_per_board(struct memlist *ml);
973f1fa9a7Sjfrank static void post_xscf_msg(char *, int);
983f1fa9a7Sjfrank static void pass2xscf_thread();
9925cf1a30Sjl139090
100e603b7d4Spm145316 /*
101e603b7d4Spm145316 * Note FF/DC out-of-order instruction engine takes only a
102e603b7d4Spm145316 * single cycle to execute each spin loop
103e603b7d4Spm145316 * for comparison, Panther takes 6 cycles for same loop
104575a7426Spt157919 * OPL_BOFF_SPIN = base spin loop, roughly one memory reference time
105575a7426Spt157919 * OPL_BOFF_TM = approx nsec for OPL sleep instruction (1600 for OPL-C)
106575a7426Spt157919 * OPL_BOFF_SLEEP = approx number of SPIN iterations to equal one sleep
107575a7426Spt157919 * OPL_BOFF_MAX_SCALE - scaling factor for max backoff based on active cpus
108575a7426Spt157919 * Listed values tuned for 2.15GHz to 2.64GHz systems
109e603b7d4Spm145316 * Value may change for future systems
110e603b7d4Spm145316 */
111575a7426Spt157919 #define OPL_BOFF_SPIN 7
112575a7426Spt157919 #define OPL_BOFF_SLEEP 4
113575a7426Spt157919 #define OPL_BOFF_TM 1600
114575a7426Spt157919 #define OPL_BOFF_MAX_SCALE 8
115e603b7d4Spm145316
1162850d85bSmv143129 #define OPL_CLOCK_TICK_THRESHOLD 128
1172850d85bSmv143129 #define OPL_CLOCK_TICK_NCPUS 64
1182850d85bSmv143129
1192850d85bSmv143129 extern int clock_tick_threshold;
1202850d85bSmv143129 extern int clock_tick_ncpus;
1212850d85bSmv143129
12225cf1a30Sjl139090 int
set_platform_max_ncpus(void)12325cf1a30Sjl139090 set_platform_max_ncpus(void)
12425cf1a30Sjl139090 {
12525cf1a30Sjl139090 return (OPL_MAX_CPU_PER_BOARD * OPL_MAX_BOARDS);
12625cf1a30Sjl139090 }
12725cf1a30Sjl139090
12825cf1a30Sjl139090 int
set_platform_tsb_spares(void)12925cf1a30Sjl139090 set_platform_tsb_spares(void)
13025cf1a30Sjl139090 {
13125cf1a30Sjl139090 return (MIN(opl_tsb_spares, MAX_UPA));
13225cf1a30Sjl139090 }
13325cf1a30Sjl139090
1341e2e7a75Shuah static void
set_model_info()1351e2e7a75Shuah set_model_info()
1361e2e7a75Shuah {
137195196c6Ssubhan extern int ts_dispatch_extended;
1381e2e7a75Shuah char name[MAXSYSNAME];
1391e2e7a75Shuah int i;
1401e2e7a75Shuah
1411e2e7a75Shuah /*
1421e2e7a75Shuah * Get model name from the root node.
1431e2e7a75Shuah *
1441e2e7a75Shuah * We are using the prom device tree since, at this point,
1451e2e7a75Shuah * the Solaris device tree is not yet setup.
1461e2e7a75Shuah */
1471e2e7a75Shuah (void) prom_getprop(prom_rootnode(), "model", (caddr_t)name);
1481e2e7a75Shuah
1491e2e7a75Shuah for (i = 0; i < opl_num_models; i++) {
1501e2e7a75Shuah if (strncmp(name, opl_models[i].model_name, MAXSYSNAME) == 0) {
1511e2e7a75Shuah opl_cur_model = &opl_models[i];
1521e2e7a75Shuah break;
1531e2e7a75Shuah }
1541e2e7a75Shuah }
155195196c6Ssubhan
1569b71d8e9Swh31274 /*
1579b71d8e9Swh31274 * If model not matched, it's an unknown model.
15878ed97a7Sjl139090 * Just return. It will default to standard dispatch tables.
1599b71d8e9Swh31274 */
1601e2e7a75Shuah if (i == opl_num_models)
1619b71d8e9Swh31274 return;
162195196c6Ssubhan
163195196c6Ssubhan if ((opl_cur_model->model_cmds & EXT_DISPATCH_TABLE) &&
164195196c6Ssubhan (ts_dispatch_extended == -1)) {
165195196c6Ssubhan /*
166195196c6Ssubhan * Based on a platform model, select a dispatch table.
167195196c6Ssubhan * Only DC2 and DC3 systems uses the alternate/extended
168195196c6Ssubhan * TS dispatch table.
16978ed97a7Sjl139090 * IKKAKU, FF1, FF2 and DC1 systems use standard dispatch
17078ed97a7Sjl139090 * tables.
171195196c6Ssubhan */
172195196c6Ssubhan ts_dispatch_extended = 1;
173195196c6Ssubhan }
174195196c6Ssubhan
1751e2e7a75Shuah }
1761e2e7a75Shuah
1771e2e7a75Shuah static void
set_max_mmu_ctxdoms()1781e2e7a75Shuah set_max_mmu_ctxdoms()
1791e2e7a75Shuah {
1801e2e7a75Shuah extern uint_t max_mmu_ctxdoms;
1811e2e7a75Shuah int max_boards;
1821e2e7a75Shuah
1831e2e7a75Shuah /*
1841e2e7a75Shuah * From the model, get the maximum number of boards
1851e2e7a75Shuah * supported and set the value accordingly. If the model
1861e2e7a75Shuah * could not be determined or recognized, we assume the max value.
1871e2e7a75Shuah */
1881e2e7a75Shuah if (opl_cur_model == NULL)
1891e2e7a75Shuah max_boards = OPL_MAX_BOARDS;
1901e2e7a75Shuah else
1911e2e7a75Shuah max_boards = opl_cur_model->model_max_boards;
1921e2e7a75Shuah
1931e2e7a75Shuah /*
1941e2e7a75Shuah * On OPL, cores and MMUs are one-to-one.
1951e2e7a75Shuah */
1961e2e7a75Shuah max_mmu_ctxdoms = OPL_MAX_CORE_UNITS_PER_BOARD * max_boards;
1971e2e7a75Shuah }
1981e2e7a75Shuah
19925cf1a30Sjl139090 #pragma weak mmu_init_large_pages
20025cf1a30Sjl139090
20125cf1a30Sjl139090 void
set_platform_defaults(void)20225cf1a30Sjl139090 set_platform_defaults(void)
20325cf1a30Sjl139090 {
20425cf1a30Sjl139090 extern char *tod_module_name;
20525cf1a30Sjl139090 extern void cpu_sgn_update(ushort_t, uchar_t, uchar_t, int);
20625cf1a30Sjl139090 extern void mmu_init_large_pages(size_t);
20725cf1a30Sjl139090
20825cf1a30Sjl139090 /* Set the CPU signature function pointer */
20925cf1a30Sjl139090 cpu_sgn_func = cpu_sgn_update;
21025cf1a30Sjl139090
21125cf1a30Sjl139090 /* Set appropriate tod module for OPL platform */
21225cf1a30Sjl139090 ASSERT(tod_module_name == NULL);
21325cf1a30Sjl139090 tod_module_name = "todopl";
21425cf1a30Sjl139090
21525cf1a30Sjl139090 if ((mmu_page_sizes == max_mmu_page_sizes) &&
216e12a8a13Ssusans (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) {
21725cf1a30Sjl139090 if (&mmu_init_large_pages)
21825cf1a30Sjl139090 mmu_init_large_pages(mmu_ism_pagesize);
21925cf1a30Sjl139090 }
22025cf1a30Sjl139090
22125cf1a30Sjl139090 tsb_lgrp_affinity = 1;
2221e2e7a75Shuah
2231e2e7a75Shuah set_max_mmu_ctxdoms();
224ca3e8d88SDave Plauger
225ca3e8d88SDave Plauger /* set OPL threshold for compressed dumps */
226*4cca9c84SDave Plauger dump_plat_mincpu_default = DUMP_PLAT_SUN4U_OPL_MINCPU;
22725cf1a30Sjl139090 }
22825cf1a30Sjl139090
22925cf1a30Sjl139090 /*
23025cf1a30Sjl139090 * Convert logical a board number to a physical one.
23125cf1a30Sjl139090 */
23225cf1a30Sjl139090
23325cf1a30Sjl139090 #define LSBPROP "board#"
23425cf1a30Sjl139090 #define PSBPROP "physical-board#"
23525cf1a30Sjl139090
23625cf1a30Sjl139090 int
opl_get_physical_board(int id)23725cf1a30Sjl139090 opl_get_physical_board(int id)
23825cf1a30Sjl139090 {
23925cf1a30Sjl139090 dev_info_t *root_dip, *dip = NULL;
24025cf1a30Sjl139090 char *dname = NULL;
24125cf1a30Sjl139090 int circ;
24225cf1a30Sjl139090
24325cf1a30Sjl139090 pnode_t pnode;
24425cf1a30Sjl139090 char pname[MAXSYSNAME] = {0};
24525cf1a30Sjl139090
24625cf1a30Sjl139090 int lsb_id; /* Logical System Board ID */
24725cf1a30Sjl139090 int psb_id; /* Physical System Board ID */
24825cf1a30Sjl139090
24925cf1a30Sjl139090
25025cf1a30Sjl139090 /*
25125cf1a30Sjl139090 * This function is called on early stage of bootup when the
25225cf1a30Sjl139090 * kernel device tree is not initialized yet, and also
25325cf1a30Sjl139090 * later on when the device tree is up. We want to try
25425cf1a30Sjl139090 * the fast track first.
25525cf1a30Sjl139090 */
25625cf1a30Sjl139090 root_dip = ddi_root_node();
25725cf1a30Sjl139090 if (root_dip) {
25825cf1a30Sjl139090 /* Get from devinfo node */
25925cf1a30Sjl139090 ndi_devi_enter(root_dip, &circ);
26025cf1a30Sjl139090 for (dip = ddi_get_child(root_dip); dip;
26125cf1a30Sjl139090 dip = ddi_get_next_sibling(dip)) {
26225cf1a30Sjl139090
26325cf1a30Sjl139090 dname = ddi_node_name(dip);
26425cf1a30Sjl139090 if (strncmp(dname, "pseudo-mc", 9) != 0)
26525cf1a30Sjl139090 continue;
26625cf1a30Sjl139090
26725cf1a30Sjl139090 if ((lsb_id = (int)ddi_getprop(DDI_DEV_T_ANY, dip,
26825cf1a30Sjl139090 DDI_PROP_DONTPASS, LSBPROP, -1)) == -1)
26925cf1a30Sjl139090 continue;
27025cf1a30Sjl139090
27125cf1a30Sjl139090 if (id == lsb_id) {
27225cf1a30Sjl139090 if ((psb_id = (int)ddi_getprop(DDI_DEV_T_ANY,
27325cf1a30Sjl139090 dip, DDI_PROP_DONTPASS, PSBPROP, -1))
27425cf1a30Sjl139090 == -1) {
27525cf1a30Sjl139090 ndi_devi_exit(root_dip, circ);
27625cf1a30Sjl139090 return (-1);
27725cf1a30Sjl139090 } else {
27825cf1a30Sjl139090 ndi_devi_exit(root_dip, circ);
27925cf1a30Sjl139090 return (psb_id);
28025cf1a30Sjl139090 }
28125cf1a30Sjl139090 }
28225cf1a30Sjl139090 }
28325cf1a30Sjl139090 ndi_devi_exit(root_dip, circ);
28425cf1a30Sjl139090 }
28525cf1a30Sjl139090
28625cf1a30Sjl139090 /*
28725cf1a30Sjl139090 * We do not have the kernel device tree, or we did not
28825cf1a30Sjl139090 * find the node for some reason (let's say the kernel
28925cf1a30Sjl139090 * device tree was modified), let's try the OBP tree.
29025cf1a30Sjl139090 */
29125cf1a30Sjl139090 pnode = prom_rootnode();
29225cf1a30Sjl139090 for (pnode = prom_childnode(pnode); pnode;
29325cf1a30Sjl139090 pnode = prom_nextnode(pnode)) {
29425cf1a30Sjl139090
29525cf1a30Sjl139090 if ((prom_getprop(pnode, "name", (caddr_t)pname) == -1) ||
29625cf1a30Sjl139090 (strncmp(pname, "pseudo-mc", 9) != 0))
29725cf1a30Sjl139090 continue;
29825cf1a30Sjl139090
29925cf1a30Sjl139090 if (prom_getprop(pnode, LSBPROP, (caddr_t)&lsb_id) == -1)
30025cf1a30Sjl139090 continue;
30125cf1a30Sjl139090
30225cf1a30Sjl139090 if (id == lsb_id) {
30325cf1a30Sjl139090 if (prom_getprop(pnode, PSBPROP,
30425cf1a30Sjl139090 (caddr_t)&psb_id) == -1) {
30525cf1a30Sjl139090 return (-1);
30625cf1a30Sjl139090 } else {
30725cf1a30Sjl139090 return (psb_id);
30825cf1a30Sjl139090 }
30925cf1a30Sjl139090 }
31025cf1a30Sjl139090 }
31125cf1a30Sjl139090
31225cf1a30Sjl139090 return (-1);
31325cf1a30Sjl139090 }
31425cf1a30Sjl139090
31525cf1a30Sjl139090 /*
31625cf1a30Sjl139090 * For OPL it's possible that memory from two or more successive boards
31725cf1a30Sjl139090 * will be contiguous across the boards, and therefore represented as a
31825cf1a30Sjl139090 * single chunk.
31925cf1a30Sjl139090 * This function splits such chunks down the board boundaries.
32025cf1a30Sjl139090 */
32125cf1a30Sjl139090 static struct memlist *
opl_memlist_per_board(struct memlist * ml)32225cf1a30Sjl139090 opl_memlist_per_board(struct memlist *ml)
32325cf1a30Sjl139090 {
32425cf1a30Sjl139090 uint64_t ssize, low, high, boundary;
32525cf1a30Sjl139090 struct memlist *head, *tail, *new;
32625cf1a30Sjl139090
32725cf1a30Sjl139090 ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
32825cf1a30Sjl139090
32925cf1a30Sjl139090 head = tail = NULL;
33025cf1a30Sjl139090
33156f33205SJonathan Adams for (; ml; ml = ml->ml_next) {
33256f33205SJonathan Adams low = (uint64_t)ml->ml_address;
33356f33205SJonathan Adams high = low+(uint64_t)(ml->ml_size);
33425cf1a30Sjl139090 while (low < high) {
33525cf1a30Sjl139090 boundary = roundup(low+1, ssize);
33625cf1a30Sjl139090 boundary = MIN(high, boundary);
33725cf1a30Sjl139090 new = kmem_zalloc(sizeof (struct memlist), KM_SLEEP);
33856f33205SJonathan Adams new->ml_address = low;
33956f33205SJonathan Adams new->ml_size = boundary - low;
34025cf1a30Sjl139090 if (head == NULL)
34125cf1a30Sjl139090 head = new;
34225cf1a30Sjl139090 if (tail) {
34356f33205SJonathan Adams tail->ml_next = new;
34456f33205SJonathan Adams new->ml_prev = tail;
34525cf1a30Sjl139090 }
34625cf1a30Sjl139090 tail = new;
34725cf1a30Sjl139090 low = boundary;
34825cf1a30Sjl139090 }
34925cf1a30Sjl139090 }
35025cf1a30Sjl139090 return (head);
35125cf1a30Sjl139090 }
35225cf1a30Sjl139090
35325cf1a30Sjl139090 void
set_platform_cage_params(void)35425cf1a30Sjl139090 set_platform_cage_params(void)
35525cf1a30Sjl139090 {
35625cf1a30Sjl139090 extern pgcnt_t total_pages;
35725cf1a30Sjl139090 extern struct memlist *phys_avail;
35825cf1a30Sjl139090 struct memlist *ml, *tml;
35925cf1a30Sjl139090
36025cf1a30Sjl139090 if (kernel_cage_enable) {
36125cf1a30Sjl139090 pgcnt_t preferred_cage_size;
36225cf1a30Sjl139090
363e98fafb9Sjl139090 preferred_cage_size = MAX(opl_startup_cage_size,
364e98fafb9Sjl139090 total_pages / 256);
36525cf1a30Sjl139090
36625cf1a30Sjl139090 ml = opl_memlist_per_board(phys_avail);
36725cf1a30Sjl139090
36825cf1a30Sjl139090 /*
36925cf1a30Sjl139090 * Note: we are assuming that post has load the
37025cf1a30Sjl139090 * whole show in to the high end of memory. Having
37125cf1a30Sjl139090 * taken this leap, we copy the whole of phys_avail
37225cf1a30Sjl139090 * the glist and arrange for the cage to grow
37325cf1a30Sjl139090 * downward (descending pfns).
37425cf1a30Sjl139090 */
37585f58038Sdp78419 kcage_range_init(ml, KCAGE_DOWN, preferred_cage_size);
37625cf1a30Sjl139090
37725cf1a30Sjl139090 /* free the memlist */
37825cf1a30Sjl139090 do {
37956f33205SJonathan Adams tml = ml->ml_next;
38025cf1a30Sjl139090 kmem_free(ml, sizeof (struct memlist));
38125cf1a30Sjl139090 ml = tml;
38225cf1a30Sjl139090 } while (ml != NULL);
38325cf1a30Sjl139090 }
38425cf1a30Sjl139090
38525cf1a30Sjl139090 if (kcage_on)
38625cf1a30Sjl139090 cmn_err(CE_NOTE, "!DR Kernel Cage is ENABLED");
38725cf1a30Sjl139090 else
38825cf1a30Sjl139090 cmn_err(CE_NOTE, "!DR Kernel Cage is DISABLED");
38925cf1a30Sjl139090 }
39025cf1a30Sjl139090
39125cf1a30Sjl139090 /*ARGSUSED*/
39225cf1a30Sjl139090 int
plat_cpu_poweron(struct cpu * cp)39325cf1a30Sjl139090 plat_cpu_poweron(struct cpu *cp)
39425cf1a30Sjl139090 {
39525cf1a30Sjl139090 int (*opl_cpu_poweron)(struct cpu *) = NULL;
39625cf1a30Sjl139090
39725cf1a30Sjl139090 opl_cpu_poweron =
39825cf1a30Sjl139090 (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweron", 0);
39925cf1a30Sjl139090
40025cf1a30Sjl139090 if (opl_cpu_poweron == NULL)
40125cf1a30Sjl139090 return (ENOTSUP);
40225cf1a30Sjl139090 else
40325cf1a30Sjl139090 return ((opl_cpu_poweron)(cp));
40425cf1a30Sjl139090
40525cf1a30Sjl139090 }
40625cf1a30Sjl139090
40725cf1a30Sjl139090 /*ARGSUSED*/
40825cf1a30Sjl139090 int
plat_cpu_poweroff(struct cpu * cp)40925cf1a30Sjl139090 plat_cpu_poweroff(struct cpu *cp)
41025cf1a30Sjl139090 {
41125cf1a30Sjl139090 int (*opl_cpu_poweroff)(struct cpu *) = NULL;
41225cf1a30Sjl139090
41325cf1a30Sjl139090 opl_cpu_poweroff =
41425cf1a30Sjl139090 (int (*)(struct cpu *))kobj_getsymvalue("drmach_cpu_poweroff", 0);
41525cf1a30Sjl139090
41625cf1a30Sjl139090 if (opl_cpu_poweroff == NULL)
41725cf1a30Sjl139090 return (ENOTSUP);
41825cf1a30Sjl139090 else
41925cf1a30Sjl139090 return ((opl_cpu_poweroff)(cp));
42025cf1a30Sjl139090
42125cf1a30Sjl139090 }
42225cf1a30Sjl139090
42325cf1a30Sjl139090 int
plat_max_boards(void)42425cf1a30Sjl139090 plat_max_boards(void)
42525cf1a30Sjl139090 {
4264af09fceSwh31274 /*
4274af09fceSwh31274 * If the model cannot be determined, default to the max value.
4284af09fceSwh31274 * Otherwise, Ikkaku model only supports 1 system board.
4294af09fceSwh31274 */
4304af09fceSwh31274 if ((opl_cur_model != NULL) && (opl_cur_model->model_type == IKKAKU))
4314af09fceSwh31274 return (OPL_MAX_BOARDS_IKKAKU);
4324af09fceSwh31274 else
43325cf1a30Sjl139090 return (OPL_MAX_BOARDS);
43425cf1a30Sjl139090 }
43525cf1a30Sjl139090
43625cf1a30Sjl139090 int
plat_max_cpu_units_per_board(void)43725cf1a30Sjl139090 plat_max_cpu_units_per_board(void)
43825cf1a30Sjl139090 {
43925cf1a30Sjl139090 return (OPL_MAX_CPU_PER_BOARD);
44025cf1a30Sjl139090 }
44125cf1a30Sjl139090
44225cf1a30Sjl139090 int
plat_max_mem_units_per_board(void)44325cf1a30Sjl139090 plat_max_mem_units_per_board(void)
44425cf1a30Sjl139090 {
44525cf1a30Sjl139090 return (OPL_MAX_MEM_UNITS_PER_BOARD);
44625cf1a30Sjl139090 }
44725cf1a30Sjl139090
44825cf1a30Sjl139090 int
plat_max_io_units_per_board(void)44925cf1a30Sjl139090 plat_max_io_units_per_board(void)
45025cf1a30Sjl139090 {
45125cf1a30Sjl139090 return (OPL_MAX_IO_UNITS_PER_BOARD);
45225cf1a30Sjl139090 }
45325cf1a30Sjl139090
45425cf1a30Sjl139090 int
plat_max_cmp_units_per_board(void)45525cf1a30Sjl139090 plat_max_cmp_units_per_board(void)
45625cf1a30Sjl139090 {
45725cf1a30Sjl139090 return (OPL_MAX_CMP_UNITS_PER_BOARD);
45825cf1a30Sjl139090 }
45925cf1a30Sjl139090
46025cf1a30Sjl139090 int
plat_max_core_units_per_board(void)46125cf1a30Sjl139090 plat_max_core_units_per_board(void)
46225cf1a30Sjl139090 {
46325cf1a30Sjl139090 return (OPL_MAX_CORE_UNITS_PER_BOARD);
46425cf1a30Sjl139090 }
46525cf1a30Sjl139090
46625cf1a30Sjl139090 int
plat_pfn_to_mem_node(pfn_t pfn)46725cf1a30Sjl139090 plat_pfn_to_mem_node(pfn_t pfn)
46825cf1a30Sjl139090 {
46925cf1a30Sjl139090 return (pfn >> mem_node_pfn_shift);
47025cf1a30Sjl139090 }
47125cf1a30Sjl139090
47225cf1a30Sjl139090 /* ARGSUSED */
47325cf1a30Sjl139090 void
plat_build_mem_nodes(prom_memlist_t * list,size_t nelems)474986fd29aSsetje plat_build_mem_nodes(prom_memlist_t *list, size_t nelems)
47525cf1a30Sjl139090 {
47625cf1a30Sjl139090 size_t elem;
47725cf1a30Sjl139090 pfn_t basepfn;
47825cf1a30Sjl139090 pgcnt_t npgs;
47925cf1a30Sjl139090 uint64_t boundary, ssize;
48025cf1a30Sjl139090 uint64_t low, high;
48125cf1a30Sjl139090
48225cf1a30Sjl139090 /*
48325cf1a30Sjl139090 * OPL mem slices are always aligned on a 256GB boundary.
48425cf1a30Sjl139090 */
48525cf1a30Sjl139090 mem_node_pfn_shift = OPL_MC_MEMBOARD_SHIFT - MMU_PAGESHIFT;
48625cf1a30Sjl139090 mem_node_physalign = 0;
48725cf1a30Sjl139090
48825cf1a30Sjl139090 /*
48925cf1a30Sjl139090 * Boot install lists are arranged <addr, len>, <addr, len>, ...
49025cf1a30Sjl139090 */
49125cf1a30Sjl139090 ssize = (1ull << OPL_MC_MEMBOARD_SHIFT);
492986fd29aSsetje for (elem = 0; elem < nelems; list++, elem++) {
493986fd29aSsetje low = list->addr;
494986fd29aSsetje high = low + list->size;
49525cf1a30Sjl139090 while (low < high) {
49625cf1a30Sjl139090 boundary = roundup(low+1, ssize);
49725cf1a30Sjl139090 boundary = MIN(high, boundary);
49825cf1a30Sjl139090 basepfn = btop(low);
49925cf1a30Sjl139090 npgs = btop(boundary - low);
50025cf1a30Sjl139090 mem_node_add_slice(basepfn, basepfn + npgs - 1);
50125cf1a30Sjl139090 low = boundary;
50225cf1a30Sjl139090 }
50325cf1a30Sjl139090 }
50425cf1a30Sjl139090 }
50525cf1a30Sjl139090
50625cf1a30Sjl139090 /*
50725cf1a30Sjl139090 * Find the CPU associated with a slice at boot-time.
50825cf1a30Sjl139090 */
50925cf1a30Sjl139090 void
plat_fill_mc(pnode_t nodeid)51025cf1a30Sjl139090 plat_fill_mc(pnode_t nodeid)
51125cf1a30Sjl139090 {
51225cf1a30Sjl139090 int board;
51325cf1a30Sjl139090 int memnode;
51425cf1a30Sjl139090 struct {
51525cf1a30Sjl139090 uint64_t addr;
51625cf1a30Sjl139090 uint64_t size;
51725cf1a30Sjl139090 } mem_range;
51825cf1a30Sjl139090
51925cf1a30Sjl139090 if (prom_getprop(nodeid, "board#", (caddr_t)&board) < 0) {
52025cf1a30Sjl139090 panic("Can not find board# property in mc node %x", nodeid);
52125cf1a30Sjl139090 }
52225cf1a30Sjl139090 if (prom_getprop(nodeid, "sb-mem-ranges", (caddr_t)&mem_range) < 0) {
52325cf1a30Sjl139090 panic("Can not find sb-mem-ranges property in mc node %x",
52425cf1a30Sjl139090 nodeid);
52525cf1a30Sjl139090 }
52625cf1a30Sjl139090 memnode = mem_range.addr >> OPL_MC_MEMBOARD_SHIFT;
52725cf1a30Sjl139090 plat_assign_lgrphand_to_mem_node(board, memnode);
52825cf1a30Sjl139090 }
52925cf1a30Sjl139090
53025cf1a30Sjl139090 /*
53125cf1a30Sjl139090 * Return the platform handle for the lgroup containing the given CPU
53225cf1a30Sjl139090 *
53325cf1a30Sjl139090 * For OPL, lgroup platform handle == board #.
53425cf1a30Sjl139090 */
53525cf1a30Sjl139090
53625cf1a30Sjl139090 extern int mpo_disabled;
53725cf1a30Sjl139090 extern lgrp_handle_t lgrp_default_handle;
53825cf1a30Sjl139090
53925cf1a30Sjl139090 lgrp_handle_t
plat_lgrp_cpu_to_hand(processorid_t id)54025cf1a30Sjl139090 plat_lgrp_cpu_to_hand(processorid_t id)
54125cf1a30Sjl139090 {
54225cf1a30Sjl139090 lgrp_handle_t plathand;
54325cf1a30Sjl139090
54425cf1a30Sjl139090 /*
54525cf1a30Sjl139090 * Return the real platform handle for the CPU until
54625cf1a30Sjl139090 * such time as we know that MPO should be disabled.
54725cf1a30Sjl139090 * At that point, we set the "mpo_disabled" flag to true,
54825cf1a30Sjl139090 * and from that point on, return the default handle.
54925cf1a30Sjl139090 *
55025cf1a30Sjl139090 * By the time we know that MPO should be disabled, the
55125cf1a30Sjl139090 * first CPU will have already been added to a leaf
55225cf1a30Sjl139090 * lgroup, but that's ok. The common lgroup code will
55325cf1a30Sjl139090 * double check that the boot CPU is in the correct place,
55425cf1a30Sjl139090 * and in the case where mpo should be disabled, will move
55525cf1a30Sjl139090 * it to the root if necessary.
55625cf1a30Sjl139090 */
55725cf1a30Sjl139090 if (mpo_disabled) {
55825cf1a30Sjl139090 /* If MPO is disabled, return the default (UMA) handle */
55925cf1a30Sjl139090 plathand = lgrp_default_handle;
56025cf1a30Sjl139090 } else
56125cf1a30Sjl139090 plathand = (lgrp_handle_t)LSB_ID(id);
56225cf1a30Sjl139090 return (plathand);
56325cf1a30Sjl139090 }
56425cf1a30Sjl139090
56525cf1a30Sjl139090 /*
56625cf1a30Sjl139090 * Platform specific lgroup initialization
56725cf1a30Sjl139090 */
56825cf1a30Sjl139090 void
plat_lgrp_init(void)56925cf1a30Sjl139090 plat_lgrp_init(void)
57025cf1a30Sjl139090 {
57125cf1a30Sjl139090 extern uint32_t lgrp_expand_proc_thresh;
57225cf1a30Sjl139090 extern uint32_t lgrp_expand_proc_diff;
573cc85acdaSpm145316 const uint_t m = LGRP_LOADAVG_THREAD_MAX;
57425cf1a30Sjl139090
57525cf1a30Sjl139090 /*
57625cf1a30Sjl139090 * Set tuneables for the OPL architecture
57725cf1a30Sjl139090 *
578cc85acdaSpm145316 * lgrp_expand_proc_thresh is the threshold load on the set of
579cc85acdaSpm145316 * lgroups a process is currently using on before considering
580cc85acdaSpm145316 * adding another lgroup to the set. For Oly-C and Jupiter
581cc85acdaSpm145316 * systems, there are four sockets per lgroup. Setting
582cc85acdaSpm145316 * lgrp_expand_proc_thresh to add lgroups when the load reaches
583cc85acdaSpm145316 * four threads will spread the load when it exceeds one thread
584cc85acdaSpm145316 * per socket, optimizing memory bandwidth and L2 cache space.
58525cf1a30Sjl139090 *
586cc85acdaSpm145316 * lgrp_expand_proc_diff determines how much less another lgroup
587cc85acdaSpm145316 * must be loaded before shifting the start location of a thread
588cc85acdaSpm145316 * to it.
58925cf1a30Sjl139090 *
590cc85acdaSpm145316 * lgrp_loadavg_tolerance is the threshold where two lgroups are
591cc85acdaSpm145316 * considered to have different loads. It is set to be less than
592cc85acdaSpm145316 * 1% so that even a small residual load will be considered different
593cc85acdaSpm145316 * from no residual load.
594cc85acdaSpm145316 *
595cc85acdaSpm145316 * We note loadavg values are not precise.
596cc85acdaSpm145316 * Every 1/10 of a second loadavg values are reduced by 5%.
597cc85acdaSpm145316 * This adjustment can come in the middle of the lgroup selection
598cc85acdaSpm145316 * process, and for larger parallel apps with many threads can
599cc85acdaSpm145316 * frequently occur between the start of the second thread
600cc85acdaSpm145316 * placement and the finish of the last thread placement.
601cc85acdaSpm145316 * We also must be careful to not use too small of a threshold
602cc85acdaSpm145316 * since the cumulative decay for 1 second idle time is 40%.
603cc85acdaSpm145316 * That is, the residual load from completed threads will still
604cc85acdaSpm145316 * be 60% one second after the proc goes idle or 8% after 5 seconds.
605cc85acdaSpm145316 *
606cc85acdaSpm145316 * To allow for lag time in loadavg calculations
607cc85acdaSpm145316 * remote thresh = 3.75 * LGRP_LOADAVG_THREAD_MAX
608cc85acdaSpm145316 * local thresh = 0.75 * LGRP_LOADAVG_THREAD_MAX
609cc85acdaSpm145316 * tolerance = 0.0078 * LGRP_LOADAVG_THREAD_MAX
610cc85acdaSpm145316 *
611cc85acdaSpm145316 * The load placement algorithms consider LGRP_LOADAVG_THREAD_MAX
612cc85acdaSpm145316 * as the equivalent of a load of 1. To make the code more compact,
613cc85acdaSpm145316 * we set m = LGRP_LOADAVG_THREAD_MAX.
61425cf1a30Sjl139090 */
615cc85acdaSpm145316 lgrp_expand_proc_thresh = (m * 3) + (m >> 1) + (m >> 2);
616cc85acdaSpm145316 lgrp_expand_proc_diff = (m >> 1) + (m >> 2);
617cc85acdaSpm145316 lgrp_loadavg_tolerance = (m >> 7);
61825cf1a30Sjl139090 }
61925cf1a30Sjl139090
62025cf1a30Sjl139090 /*
62125cf1a30Sjl139090 * Platform notification of lgroup (re)configuration changes
62225cf1a30Sjl139090 */
62325cf1a30Sjl139090 /*ARGSUSED*/
62425cf1a30Sjl139090 void
plat_lgrp_config(lgrp_config_flag_t evt,uintptr_t arg)62525cf1a30Sjl139090 plat_lgrp_config(lgrp_config_flag_t evt, uintptr_t arg)
62625cf1a30Sjl139090 {
62725cf1a30Sjl139090 update_membounds_t *umb;
62825cf1a30Sjl139090 lgrp_config_mem_rename_t lmr;
62925cf1a30Sjl139090 int sbd, tbd;
63025cf1a30Sjl139090 lgrp_handle_t hand, shand, thand;
63125cf1a30Sjl139090 int mnode, snode, tnode;
63225cf1a30Sjl139090 pfn_t start, end;
63325cf1a30Sjl139090
63425cf1a30Sjl139090 if (mpo_disabled)
63525cf1a30Sjl139090 return;
63625cf1a30Sjl139090
63725cf1a30Sjl139090 switch (evt) {
63825cf1a30Sjl139090
63925cf1a30Sjl139090 case LGRP_CONFIG_MEM_ADD:
64025cf1a30Sjl139090 /*
64125cf1a30Sjl139090 * Establish the lgroup handle to memnode translation.
64225cf1a30Sjl139090 */
64325cf1a30Sjl139090 umb = (update_membounds_t *)arg;
64425cf1a30Sjl139090
64525cf1a30Sjl139090 hand = umb->u_board;
64625cf1a30Sjl139090 mnode = plat_pfn_to_mem_node(umb->u_base >> MMU_PAGESHIFT);
64725cf1a30Sjl139090 plat_assign_lgrphand_to_mem_node(hand, mnode);
64825cf1a30Sjl139090
64925cf1a30Sjl139090 break;
65025cf1a30Sjl139090
65125cf1a30Sjl139090 case LGRP_CONFIG_MEM_DEL:
65225cf1a30Sjl139090 /*
65325cf1a30Sjl139090 * Special handling for possible memory holes.
65425cf1a30Sjl139090 */
65525cf1a30Sjl139090 umb = (update_membounds_t *)arg;
65625cf1a30Sjl139090 hand = umb->u_board;
65725cf1a30Sjl139090 if ((mnode = plat_lgrphand_to_mem_node(hand)) != -1) {
65825cf1a30Sjl139090 if (mem_node_config[mnode].exists) {
65925cf1a30Sjl139090 start = mem_node_config[mnode].physbase;
66025cf1a30Sjl139090 end = mem_node_config[mnode].physmax;
6619853d9e8SJason Beloro mem_node_del_slice(start, end);
66225cf1a30Sjl139090 }
66325cf1a30Sjl139090 }
66425cf1a30Sjl139090
66525cf1a30Sjl139090 break;
66625cf1a30Sjl139090
66725cf1a30Sjl139090 case LGRP_CONFIG_MEM_RENAME:
66825cf1a30Sjl139090 /*
66925cf1a30Sjl139090 * During a DR copy-rename operation, all of the memory
67025cf1a30Sjl139090 * on one board is moved to another board -- but the
67125cf1a30Sjl139090 * addresses/pfns and memnodes don't change. This means
67225cf1a30Sjl139090 * the memory has changed locations without changing identity.
67325cf1a30Sjl139090 *
67425cf1a30Sjl139090 * Source is where we are copying from and target is where we
67525cf1a30Sjl139090 * are copying to. After source memnode is copied to target
67625cf1a30Sjl139090 * memnode, the physical addresses of the target memnode are
67725cf1a30Sjl139090 * renamed to match what the source memnode had. Then target
67825cf1a30Sjl139090 * memnode can be removed and source memnode can take its
67925cf1a30Sjl139090 * place.
68025cf1a30Sjl139090 *
68125cf1a30Sjl139090 * To do this, swap the lgroup handle to memnode mappings for
68225cf1a30Sjl139090 * the boards, so target lgroup will have source memnode and
68325cf1a30Sjl139090 * source lgroup will have empty target memnode which is where
68425cf1a30Sjl139090 * its memory will go (if any is added to it later).
68525cf1a30Sjl139090 *
68625cf1a30Sjl139090 * Then source memnode needs to be removed from its lgroup
68725cf1a30Sjl139090 * and added to the target lgroup where the memory was living
68825cf1a30Sjl139090 * but under a different name/memnode. The memory was in the
68925cf1a30Sjl139090 * target memnode and now lives in the source memnode with
69025cf1a30Sjl139090 * different physical addresses even though it is the same
69125cf1a30Sjl139090 * memory.
69225cf1a30Sjl139090 */
69325cf1a30Sjl139090 sbd = arg & 0xffff;
69425cf1a30Sjl139090 tbd = (arg & 0xffff0000) >> 16;
69525cf1a30Sjl139090 shand = sbd;
69625cf1a30Sjl139090 thand = tbd;
69725cf1a30Sjl139090 snode = plat_lgrphand_to_mem_node(shand);
69825cf1a30Sjl139090 tnode = plat_lgrphand_to_mem_node(thand);
69925cf1a30Sjl139090
70025cf1a30Sjl139090 /*
70125cf1a30Sjl139090 * Special handling for possible memory holes.
70225cf1a30Sjl139090 */
70325cf1a30Sjl139090 if (tnode != -1 && mem_node_config[tnode].exists) {
70468ac2337Sjl139090 start = mem_node_config[tnode].physbase;
70568ac2337Sjl139090 end = mem_node_config[tnode].physmax;
7069853d9e8SJason Beloro mem_node_del_slice(start, end);
70725cf1a30Sjl139090 }
70825cf1a30Sjl139090
70925cf1a30Sjl139090 plat_assign_lgrphand_to_mem_node(thand, snode);
71025cf1a30Sjl139090 plat_assign_lgrphand_to_mem_node(shand, tnode);
71125cf1a30Sjl139090
71225cf1a30Sjl139090 lmr.lmem_rename_from = shand;
71325cf1a30Sjl139090 lmr.lmem_rename_to = thand;
71425cf1a30Sjl139090
71525cf1a30Sjl139090 /*
71625cf1a30Sjl139090 * Remove source memnode of copy rename from its lgroup
71725cf1a30Sjl139090 * and add it to its new target lgroup
71825cf1a30Sjl139090 */
71925cf1a30Sjl139090 lgrp_config(LGRP_CONFIG_MEM_RENAME, (uintptr_t)snode,
72025cf1a30Sjl139090 (uintptr_t)&lmr);
72125cf1a30Sjl139090
72225cf1a30Sjl139090 break;
72325cf1a30Sjl139090
72425cf1a30Sjl139090 default:
72525cf1a30Sjl139090 break;
72625cf1a30Sjl139090 }
72725cf1a30Sjl139090 }
72825cf1a30Sjl139090
72925cf1a30Sjl139090 /*
73025cf1a30Sjl139090 * Return latency between "from" and "to" lgroups
73125cf1a30Sjl139090 *
73225cf1a30Sjl139090 * This latency number can only be used for relative comparison
73325cf1a30Sjl139090 * between lgroups on the running system, cannot be used across platforms,
73425cf1a30Sjl139090 * and may not reflect the actual latency. It is platform and implementation
73525cf1a30Sjl139090 * specific, so platform gets to decide its value. It would be nice if the
73625cf1a30Sjl139090 * number was at least proportional to make comparisons more meaningful though.
73725cf1a30Sjl139090 * NOTE: The numbers below are supposed to be load latencies for uncached
73825cf1a30Sjl139090 * memory divided by 10.
73925cf1a30Sjl139090 *
74025cf1a30Sjl139090 */
74125cf1a30Sjl139090 int
plat_lgrp_latency(lgrp_handle_t from,lgrp_handle_t to)74225cf1a30Sjl139090 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to)
74325cf1a30Sjl139090 {
74425cf1a30Sjl139090 /*
74525cf1a30Sjl139090 * Return min remote latency when there are more than two lgroups
74625cf1a30Sjl139090 * (root and child) and getting latency between two different lgroups
74725cf1a30Sjl139090 * or root is involved
74825cf1a30Sjl139090 */
74925cf1a30Sjl139090 if (lgrp_optimizations() && (from != to ||
75025cf1a30Sjl139090 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE))
75171b3c2ffShyw return (42);
75225cf1a30Sjl139090 else
75371b3c2ffShyw return (35);
75425cf1a30Sjl139090 }
75525cf1a30Sjl139090
75625cf1a30Sjl139090 /*
75725cf1a30Sjl139090 * Return platform handle for root lgroup
75825cf1a30Sjl139090 */
75925cf1a30Sjl139090 lgrp_handle_t
plat_lgrp_root_hand(void)76025cf1a30Sjl139090 plat_lgrp_root_hand(void)
76125cf1a30Sjl139090 {
76225cf1a30Sjl139090 if (mpo_disabled)
76325cf1a30Sjl139090 return (lgrp_default_handle);
76425cf1a30Sjl139090
76525cf1a30Sjl139090 return (LGRP_DEFAULT_HANDLE);
76625cf1a30Sjl139090 }
76725cf1a30Sjl139090
76825cf1a30Sjl139090 /*ARGSUSED*/
76925cf1a30Sjl139090 void
plat_freelist_process(int mnode)77025cf1a30Sjl139090 plat_freelist_process(int mnode)
77125cf1a30Sjl139090 {
77225cf1a30Sjl139090 }
77325cf1a30Sjl139090
77425cf1a30Sjl139090 void
load_platform_drivers(void)77525cf1a30Sjl139090 load_platform_drivers(void)
77625cf1a30Sjl139090 {
77725cf1a30Sjl139090 (void) i_ddi_attach_pseudo_node("dr");
77825cf1a30Sjl139090 }
77925cf1a30Sjl139090
78025cf1a30Sjl139090 /*
78125cf1a30Sjl139090 * No platform drivers on this platform
78225cf1a30Sjl139090 */
78325cf1a30Sjl139090 char *platform_module_list[] = {
78425cf1a30Sjl139090 (char *)0
78525cf1a30Sjl139090 };
78625cf1a30Sjl139090
78725cf1a30Sjl139090 /*ARGSUSED*/
78825cf1a30Sjl139090 void
plat_tod_fault(enum tod_fault_type tod_bad)78925cf1a30Sjl139090 plat_tod_fault(enum tod_fault_type tod_bad)
79025cf1a30Sjl139090 {
79125cf1a30Sjl139090 }
79225cf1a30Sjl139090
79325cf1a30Sjl139090 /*ARGSUSED*/
79425cf1a30Sjl139090 void
cpu_sgn_update(ushort_t sgn,uchar_t state,uchar_t sub_state,int cpuid)79525cf1a30Sjl139090 cpu_sgn_update(ushort_t sgn, uchar_t state, uchar_t sub_state, int cpuid)
79625cf1a30Sjl139090 {
79725cf1a30Sjl139090 static void (*scf_panic_callback)(int);
79825cf1a30Sjl139090 static void (*scf_shutdown_callback)(int);
79925cf1a30Sjl139090
80025cf1a30Sjl139090 /*
80125cf1a30Sjl139090 * This is for notifing system panic/shutdown to SCF.
80225cf1a30Sjl139090 * In case of shutdown and panic, SCF call back
80325cf1a30Sjl139090 * function should be called.
80425cf1a30Sjl139090 * <SCF call back functions>
80525cf1a30Sjl139090 * scf_panic_callb() : panicsys()->panic_quiesce_hw()
80625cf1a30Sjl139090 * scf_shutdown_callb(): halt() or power_down() or reboot_machine()
80725cf1a30Sjl139090 * cpuid should be -1 and state should be SIGST_EXIT.
80825cf1a30Sjl139090 */
80925cf1a30Sjl139090 if (state == SIGST_EXIT && cpuid == -1) {
81025cf1a30Sjl139090
81125cf1a30Sjl139090 /*
81225cf1a30Sjl139090 * find the symbol for the SCF panic callback routine in driver
81325cf1a30Sjl139090 */
81425cf1a30Sjl139090 if (scf_panic_callback == NULL)
81525cf1a30Sjl139090 scf_panic_callback = (void (*)(int))
81625cf1a30Sjl139090 modgetsymvalue("scf_panic_callb", 0);
81725cf1a30Sjl139090 if (scf_shutdown_callback == NULL)
81825cf1a30Sjl139090 scf_shutdown_callback = (void (*)(int))
81925cf1a30Sjl139090 modgetsymvalue("scf_shutdown_callb", 0);
82025cf1a30Sjl139090
82125cf1a30Sjl139090 switch (sub_state) {
82225cf1a30Sjl139090 case SIGSUBST_PANIC:
82325cf1a30Sjl139090 if (scf_panic_callback == NULL) {
82425cf1a30Sjl139090 cmn_err(CE_NOTE, "!cpu_sgn_update: "
82525cf1a30Sjl139090 "scf_panic_callb not found\n");
82625cf1a30Sjl139090 return;
82725cf1a30Sjl139090 }
82825cf1a30Sjl139090 scf_panic_callback(SIGSUBST_PANIC);
82925cf1a30Sjl139090 break;
83025cf1a30Sjl139090
83125cf1a30Sjl139090 case SIGSUBST_HALT:
83225cf1a30Sjl139090 if (scf_shutdown_callback == NULL) {
83325cf1a30Sjl139090 cmn_err(CE_NOTE, "!cpu_sgn_update: "
83425cf1a30Sjl139090 "scf_shutdown_callb not found\n");
83525cf1a30Sjl139090 return;
83625cf1a30Sjl139090 }
83725cf1a30Sjl139090 scf_shutdown_callback(SIGSUBST_HALT);
83825cf1a30Sjl139090 break;
83925cf1a30Sjl139090
84025cf1a30Sjl139090 case SIGSUBST_ENVIRON:
84125cf1a30Sjl139090 if (scf_shutdown_callback == NULL) {
84225cf1a30Sjl139090 cmn_err(CE_NOTE, "!cpu_sgn_update: "
84325cf1a30Sjl139090 "scf_shutdown_callb not found\n");
84425cf1a30Sjl139090 return;
84525cf1a30Sjl139090 }
84625cf1a30Sjl139090 scf_shutdown_callback(SIGSUBST_ENVIRON);
84725cf1a30Sjl139090 break;
84825cf1a30Sjl139090
84925cf1a30Sjl139090 case SIGSUBST_REBOOT:
85025cf1a30Sjl139090 if (scf_shutdown_callback == NULL) {
85125cf1a30Sjl139090 cmn_err(CE_NOTE, "!cpu_sgn_update: "
85225cf1a30Sjl139090 "scf_shutdown_callb not found\n");
85325cf1a30Sjl139090 return;
85425cf1a30Sjl139090 }
85525cf1a30Sjl139090 scf_shutdown_callback(SIGSUBST_REBOOT);
85625cf1a30Sjl139090 break;
85725cf1a30Sjl139090 }
85825cf1a30Sjl139090 }
85925cf1a30Sjl139090 }
86025cf1a30Sjl139090
86125cf1a30Sjl139090 /*ARGSUSED*/
86225cf1a30Sjl139090 int
plat_get_mem_unum(int synd_code,uint64_t flt_addr,int flt_bus_id,int flt_in_memory,ushort_t flt_status,char * buf,int buflen,int * lenp)86325cf1a30Sjl139090 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
86425cf1a30Sjl139090 int flt_in_memory, ushort_t flt_status,
86525cf1a30Sjl139090 char *buf, int buflen, int *lenp)
86625cf1a30Sjl139090 {
86725cf1a30Sjl139090 /*
86825cf1a30Sjl139090 * check if it's a Memory error.
86925cf1a30Sjl139090 */
87025cf1a30Sjl139090 if (flt_in_memory) {
87125cf1a30Sjl139090 if (opl_get_mem_unum != NULL) {
872e98fafb9Sjl139090 return (opl_get_mem_unum(synd_code, flt_addr, buf,
873e98fafb9Sjl139090 buflen, lenp));
87425cf1a30Sjl139090 } else {
87525cf1a30Sjl139090 return (ENOTSUP);
87625cf1a30Sjl139090 }
87725cf1a30Sjl139090 } else {
87825cf1a30Sjl139090 return (ENOTSUP);
87925cf1a30Sjl139090 }
88025cf1a30Sjl139090 }
88125cf1a30Sjl139090
88225cf1a30Sjl139090 /*ARGSUSED*/
88325cf1a30Sjl139090 int
plat_get_cpu_unum(int cpuid,char * buf,int buflen,int * lenp)88425cf1a30Sjl139090 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
88525cf1a30Sjl139090 {
8860cc8ae86Sav145390 int ret = 0;
8873f1fa9a7Sjfrank int sb;
888195196c6Ssubhan int plen;
88925cf1a30Sjl139090
89025cf1a30Sjl139090 sb = opl_get_physical_board(LSB_ID(cpuid));
89125cf1a30Sjl139090 if (sb == -1) {
89225cf1a30Sjl139090 return (ENXIO);
89325cf1a30Sjl139090 }
89425cf1a30Sjl139090
89572b9fce9Ssubhan /*
89672b9fce9Ssubhan * opl_cur_model is assigned here
89772b9fce9Ssubhan */
89872b9fce9Ssubhan if (opl_cur_model == NULL) {
89972b9fce9Ssubhan set_model_info();
9009b71d8e9Swh31274
9019b71d8e9Swh31274 /*
9029b71d8e9Swh31274 * if not matched, return
9039b71d8e9Swh31274 */
9049b71d8e9Swh31274 if (opl_cur_model == NULL)
9059b71d8e9Swh31274 return (ENODEV);
90672b9fce9Ssubhan }
90772b9fce9Ssubhan
908195196c6Ssubhan ASSERT((opl_cur_model - opl_models) == (opl_cur_model->model_type));
909195196c6Ssubhan
910195196c6Ssubhan switch (opl_cur_model->model_type) {
911195196c6Ssubhan case FF1:
9120cc8ae86Sav145390 plen = snprintf(buf, buflen, "/%s/CPUM%d", "MBU_A",
9130cc8ae86Sav145390 CHIP_ID(cpuid) / 2);
9140cc8ae86Sav145390 break;
9150cc8ae86Sav145390
916195196c6Ssubhan case FF2:
9170cc8ae86Sav145390 plen = snprintf(buf, buflen, "/%s/CPUM%d", "MBU_B",
91811114147Sav145390 (CHIP_ID(cpuid) / 2) + (sb * 2));
9190cc8ae86Sav145390 break;
9200cc8ae86Sav145390
921195196c6Ssubhan case DC1:
922195196c6Ssubhan case DC2:
923195196c6Ssubhan case DC3:
9240cc8ae86Sav145390 plen = snprintf(buf, buflen, "/%s%02d/CPUM%d", "CMU", sb,
9250cc8ae86Sav145390 CHIP_ID(cpuid));
9260cc8ae86Sav145390 break;
9270cc8ae86Sav145390
92878ed97a7Sjl139090 case IKKAKU:
92978ed97a7Sjl139090 plen = snprintf(buf, buflen, "/%s", "MBU_A");
93078ed97a7Sjl139090 break;
93178ed97a7Sjl139090
9320cc8ae86Sav145390 default:
9330cc8ae86Sav145390 /* This should never happen */
9340cc8ae86Sav145390 return (ENODEV);
9350cc8ae86Sav145390 }
9360cc8ae86Sav145390
9370cc8ae86Sav145390 if (plen >= buflen) {
9380cc8ae86Sav145390 ret = ENOSPC;
93925cf1a30Sjl139090 } else {
94025cf1a30Sjl139090 if (lenp)
94125cf1a30Sjl139090 *lenp = strlen(buf);
94225cf1a30Sjl139090 }
9430cc8ae86Sav145390 return (ret);
94425cf1a30Sjl139090 }
94525cf1a30Sjl139090
94625cf1a30Sjl139090 void
plat_nodename_set(void)94725cf1a30Sjl139090 plat_nodename_set(void)
94825cf1a30Sjl139090 {
9493f1fa9a7Sjfrank post_xscf_msg((char *)&utsname, sizeof (struct utsname));
95025cf1a30Sjl139090 }
95125cf1a30Sjl139090
95225cf1a30Sjl139090 caddr_t efcode_vaddr = NULL;
95325cf1a30Sjl139090
95425cf1a30Sjl139090 /*
95525cf1a30Sjl139090 * Preallocate enough memory for fcode claims.
95625cf1a30Sjl139090 */
95725cf1a30Sjl139090
95825cf1a30Sjl139090 caddr_t
efcode_alloc(caddr_t alloc_base)95925cf1a30Sjl139090 efcode_alloc(caddr_t alloc_base)
96025cf1a30Sjl139090 {
96125cf1a30Sjl139090 caddr_t efcode_alloc_base = (caddr_t)roundup((uintptr_t)alloc_base,
96225cf1a30Sjl139090 MMU_PAGESIZE);
96325cf1a30Sjl139090 caddr_t vaddr;
96425cf1a30Sjl139090
96525cf1a30Sjl139090 /*
96625cf1a30Sjl139090 * allocate the physical memory for the Oberon fcode.
96725cf1a30Sjl139090 */
96825cf1a30Sjl139090 if ((vaddr = (caddr_t)BOP_ALLOC(bootops, efcode_alloc_base,
96925cf1a30Sjl139090 efcode_size, MMU_PAGESIZE)) == NULL)
97025cf1a30Sjl139090 cmn_err(CE_PANIC, "Cannot allocate Efcode Memory");
97125cf1a30Sjl139090
97225cf1a30Sjl139090 efcode_vaddr = vaddr;
97325cf1a30Sjl139090
97425cf1a30Sjl139090 return (efcode_alloc_base + efcode_size);
97525cf1a30Sjl139090 }
97625cf1a30Sjl139090
97725cf1a30Sjl139090 caddr_t
plat_startup_memlist(caddr_t alloc_base)97825cf1a30Sjl139090 plat_startup_memlist(caddr_t alloc_base)
97925cf1a30Sjl139090 {
98025cf1a30Sjl139090 caddr_t tmp_alloc_base;
98125cf1a30Sjl139090
98225cf1a30Sjl139090 tmp_alloc_base = efcode_alloc(alloc_base);
98325cf1a30Sjl139090 tmp_alloc_base =
98425cf1a30Sjl139090 (caddr_t)roundup((uintptr_t)tmp_alloc_base, ecache_alignsize);
98525cf1a30Sjl139090 return (tmp_alloc_base);
98625cf1a30Sjl139090 }
98725cf1a30Sjl139090
988575a7426Spt157919 /* need to forward declare these */
989575a7426Spt157919 static void plat_lock_delay(uint_t);
990575a7426Spt157919
99125cf1a30Sjl139090 void
startup_platform(void)99225cf1a30Sjl139090 startup_platform(void)
99325cf1a30Sjl139090 {
9942850d85bSmv143129 if (clock_tick_threshold == 0)
9952850d85bSmv143129 clock_tick_threshold = OPL_CLOCK_TICK_THRESHOLD;
9962850d85bSmv143129 if (clock_tick_ncpus == 0)
9972850d85bSmv143129 clock_tick_ncpus = OPL_CLOCK_TICK_NCPUS;
998575a7426Spt157919 mutex_lock_delay = plat_lock_delay;
999575a7426Spt157919 mutex_cap_factor = OPL_BOFF_MAX_SCALE;
100025cf1a30Sjl139090 }
10010cc8ae86Sav145390
100204938e8bSjfrank static uint_t
get_mmu_id(processorid_t cpuid)100304938e8bSjfrank get_mmu_id(processorid_t cpuid)
100404938e8bSjfrank {
100504938e8bSjfrank int pb = opl_get_physical_board(LSB_ID(cpuid));
100604938e8bSjfrank
100704938e8bSjfrank if (pb == -1) {
100804938e8bSjfrank cmn_err(CE_PANIC,
100904938e8bSjfrank "opl_get_physical_board failed (cpu %d LSB %u)",
101004938e8bSjfrank cpuid, LSB_ID(cpuid));
101104938e8bSjfrank }
101204938e8bSjfrank return (pb * OPL_MAX_COREID_PER_BOARD) + (CHIP_ID(cpuid) *
101304938e8bSjfrank OPL_MAX_COREID_PER_CMP) + CORE_ID(cpuid);
101404938e8bSjfrank }
101504938e8bSjfrank
10161e2e7a75Shuah void
plat_cpuid_to_mmu_ctx_info(processorid_t cpuid,mmu_ctx_info_t * info)10171e2e7a75Shuah plat_cpuid_to_mmu_ctx_info(processorid_t cpuid, mmu_ctx_info_t *info)
10181e2e7a75Shuah {
10191e2e7a75Shuah int impl;
10201e2e7a75Shuah
10211e2e7a75Shuah impl = cpunodes[cpuid].implementation;
1022e98fafb9Sjl139090 if (IS_OLYMPUS_C(impl) || IS_JUPITER(impl)) {
102304938e8bSjfrank info->mmu_idx = get_mmu_id(cpuid);
10241e2e7a75Shuah info->mmu_nctxs = 8192;
10251e2e7a75Shuah } else {
10261e2e7a75Shuah cmn_err(CE_PANIC, "Unknown processor %d", impl);
10271e2e7a75Shuah }
10281e2e7a75Shuah }
10291e2e7a75Shuah
10300cc8ae86Sav145390 int
plat_get_mem_sid(char * unum,char * buf,int buflen,int * lenp)10310cc8ae86Sav145390 plat_get_mem_sid(char *unum, char *buf, int buflen, int *lenp)
10320cc8ae86Sav145390 {
10330cc8ae86Sav145390 if (opl_get_mem_sid == NULL) {
10340cc8ae86Sav145390 return (ENOTSUP);
10350cc8ae86Sav145390 }
10360cc8ae86Sav145390 return (opl_get_mem_sid(unum, buf, buflen, lenp));
10370cc8ae86Sav145390 }
10380cc8ae86Sav145390
10390cc8ae86Sav145390 int
plat_get_mem_offset(uint64_t paddr,uint64_t * offp)10400cc8ae86Sav145390 plat_get_mem_offset(uint64_t paddr, uint64_t *offp)
10410cc8ae86Sav145390 {
10420cc8ae86Sav145390 if (opl_get_mem_offset == NULL) {
10430cc8ae86Sav145390 return (ENOTSUP);
10440cc8ae86Sav145390 }
10450cc8ae86Sav145390 return (opl_get_mem_offset(paddr, offp));
10460cc8ae86Sav145390 }
10470cc8ae86Sav145390
10480cc8ae86Sav145390 int
plat_get_mem_addr(char * unum,char * sid,uint64_t offset,uint64_t * addrp)10490cc8ae86Sav145390 plat_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp)
10500cc8ae86Sav145390 {
10510cc8ae86Sav145390 if (opl_get_mem_addr == NULL) {
10520cc8ae86Sav145390 return (ENOTSUP);
10530cc8ae86Sav145390 }
10540cc8ae86Sav145390 return (opl_get_mem_addr(unum, sid, offset, addrp));
10550cc8ae86Sav145390 }
1056e603b7d4Spm145316
1057e603b7d4Spm145316 void
plat_lock_delay(uint_t backoff)1058575a7426Spt157919 plat_lock_delay(uint_t backoff)
1059e603b7d4Spm145316 {
1060e603b7d4Spm145316 int i;
1061575a7426Spt157919 uint_t cnt, remcnt;
1062e603b7d4Spm145316 int ctr;
1063575a7426Spt157919 hrtime_t delay_start, rem_delay;
1064e603b7d4Spm145316 /*
1065e603b7d4Spm145316 * Platform specific lock delay code for OPL
1066e603b7d4Spm145316 *
1067e603b7d4Spm145316 * Using staged linear increases in the delay.
1068e603b7d4Spm145316 * The sleep instruction is the preferred method of delay,
1069e603b7d4Spm145316 * but is too large of granularity for the initial backoff.
1070e603b7d4Spm145316 */
1071e603b7d4Spm145316
1072575a7426Spt157919 if (backoff < 100) {
1073e603b7d4Spm145316 /*
1074e603b7d4Spm145316 * If desired backoff is long enough,
1075e603b7d4Spm145316 * use sleep for most of it
1076e603b7d4Spm145316 */
1077575a7426Spt157919 for (cnt = backoff;
1078575a7426Spt157919 cnt >= OPL_BOFF_SLEEP;
1079e603b7d4Spm145316 cnt -= OPL_BOFF_SLEEP) {
1080e603b7d4Spm145316 cpu_smt_pause();
1081e603b7d4Spm145316 }
1082e603b7d4Spm145316 /*
1083e603b7d4Spm145316 * spin for small remainder of backoff
1084e603b7d4Spm145316 */
1085e603b7d4Spm145316 for (ctr = cnt * OPL_BOFF_SPIN; ctr; ctr--) {
1086575a7426Spt157919 mutex_delay_default();
1087e603b7d4Spm145316 }
1088e603b7d4Spm145316 } else {
1089575a7426Spt157919 /* backoff is large. Fill it by sleeping */
1090fb81f553Sck142721 delay_start = gethrtime_waitfree();
1091575a7426Spt157919 cnt = backoff / OPL_BOFF_SLEEP;
1092e603b7d4Spm145316 /*
1093e603b7d4Spm145316 * use sleep instructions for delay
1094e603b7d4Spm145316 */
1095e603b7d4Spm145316 for (i = 0; i < cnt; i++) {
1096e603b7d4Spm145316 cpu_smt_pause();
1097e603b7d4Spm145316 }
1098e603b7d4Spm145316
1099e603b7d4Spm145316 /*
1100e603b7d4Spm145316 * Note: if the other strand executes a sleep instruction,
1101e603b7d4Spm145316 * then the sleep ends immediately with a minimum time of
1102e603b7d4Spm145316 * 42 clocks. We check gethrtime to insure we have
1103e603b7d4Spm145316 * waited long enough. And we include both a short
1104575a7426Spt157919 * spin loop and a sleep for repeated delay times.
1105e603b7d4Spm145316 */
1106e603b7d4Spm145316
1107fb81f553Sck142721 rem_delay = gethrtime_waitfree() - delay_start;
1108575a7426Spt157919 while (rem_delay < cnt * OPL_BOFF_TM) {
1109575a7426Spt157919 remcnt = cnt - (rem_delay / OPL_BOFF_TM);
1110575a7426Spt157919 for (i = 0; i < remcnt; i++) {
1111e603b7d4Spm145316 cpu_smt_pause();
1112e603b7d4Spm145316 for (ctr = OPL_BOFF_SPIN; ctr; ctr--) {
1113575a7426Spt157919 mutex_delay_default();
1114e603b7d4Spm145316 }
1115e603b7d4Spm145316 }
1116fb81f553Sck142721 rem_delay = gethrtime_waitfree() - delay_start;
1117e603b7d4Spm145316 }
1118e603b7d4Spm145316 }
1119e603b7d4Spm145316 }
11203f1fa9a7Sjfrank
11213f1fa9a7Sjfrank /*
11223f1fa9a7Sjfrank * The following code implements asynchronous call to XSCF to setup the
11233f1fa9a7Sjfrank * domain node name.
11243f1fa9a7Sjfrank */
11253f1fa9a7Sjfrank
11263f1fa9a7Sjfrank #define FREE_MSG(m) kmem_free((m), NM_LEN((m)->len))
11273f1fa9a7Sjfrank
11283f1fa9a7Sjfrank /*
11293f1fa9a7Sjfrank * The following three macros define the all operations on the request
11303f1fa9a7Sjfrank * list we are using here, and hide the details of the list
11313f1fa9a7Sjfrank * implementation from the code.
11323f1fa9a7Sjfrank */
11333f1fa9a7Sjfrank #define PUSH(m) \
11343f1fa9a7Sjfrank { \
11353f1fa9a7Sjfrank (m)->next = ctl_msg.head; \
11363f1fa9a7Sjfrank (m)->prev = NULL; \
11373f1fa9a7Sjfrank if ((m)->next != NULL) \
11383f1fa9a7Sjfrank (m)->next->prev = (m); \
11393f1fa9a7Sjfrank ctl_msg.head = (m); \
11403f1fa9a7Sjfrank }
11413f1fa9a7Sjfrank
11423f1fa9a7Sjfrank #define REMOVE(m) \
11433f1fa9a7Sjfrank { \
11443f1fa9a7Sjfrank if ((m)->prev != NULL) \
11453f1fa9a7Sjfrank (m)->prev->next = (m)->next; \
11463f1fa9a7Sjfrank else \
11473f1fa9a7Sjfrank ctl_msg.head = (m)->next; \
11483f1fa9a7Sjfrank if ((m)->next != NULL) \
11493f1fa9a7Sjfrank (m)->next->prev = (m)->prev; \
11503f1fa9a7Sjfrank }
11513f1fa9a7Sjfrank
11523f1fa9a7Sjfrank #define FREE_THE_TAIL(head) \
11533f1fa9a7Sjfrank { \
11543f1fa9a7Sjfrank nm_msg_t *n_msg, *m; \
11553f1fa9a7Sjfrank m = (head)->next; \
11563f1fa9a7Sjfrank (head)->next = NULL; \
11573f1fa9a7Sjfrank while (m != NULL) { \
11583f1fa9a7Sjfrank n_msg = m->next; \
11593f1fa9a7Sjfrank FREE_MSG(m); \
11603f1fa9a7Sjfrank m = n_msg; \
11613f1fa9a7Sjfrank } \
11623f1fa9a7Sjfrank }
11633f1fa9a7Sjfrank
11643f1fa9a7Sjfrank #define SCF_PUTINFO(f, s, p) \
11653f1fa9a7Sjfrank f(KEY_ESCF, 0x01, 0, s, p)
11663f1fa9a7Sjfrank
11673f1fa9a7Sjfrank #define PASS2XSCF(m, r) ((r = SCF_PUTINFO(ctl_msg.scf_service_function, \
11683f1fa9a7Sjfrank (m)->len, (m)->data)) == 0)
11693f1fa9a7Sjfrank
11703f1fa9a7Sjfrank /*
11713f1fa9a7Sjfrank * The value of the following macro loosely depends on the
11723f1fa9a7Sjfrank * value of the "device busy" timeout used in the SCF driver.
11733f1fa9a7Sjfrank * (See pass2xscf_thread()).
11743f1fa9a7Sjfrank */
11753f1fa9a7Sjfrank #define SCF_DEVBUSY_DELAY 10
11763f1fa9a7Sjfrank
11773f1fa9a7Sjfrank /*
11783f1fa9a7Sjfrank * The default number of attempts to contact the scf driver
11793f1fa9a7Sjfrank * if we cannot fetch any information about the timeout value
11803f1fa9a7Sjfrank * it uses.
11813f1fa9a7Sjfrank */
11823f1fa9a7Sjfrank
11833f1fa9a7Sjfrank #define REPEATS 4
11843f1fa9a7Sjfrank
11853f1fa9a7Sjfrank typedef struct nm_msg {
11863f1fa9a7Sjfrank struct nm_msg *next;
11873f1fa9a7Sjfrank struct nm_msg *prev;
11883f1fa9a7Sjfrank int len;
11893f1fa9a7Sjfrank char data[1];
11903f1fa9a7Sjfrank } nm_msg_t;
11913f1fa9a7Sjfrank
11923f1fa9a7Sjfrank #define NM_LEN(len) (sizeof (nm_msg_t) + (len) - 1)
11933f1fa9a7Sjfrank
11943f1fa9a7Sjfrank static struct ctlmsg {
11953f1fa9a7Sjfrank nm_msg_t *head;
11963f1fa9a7Sjfrank nm_msg_t *now_serving;
11973f1fa9a7Sjfrank kmutex_t nm_lock;
11983f1fa9a7Sjfrank kthread_t *nmt;
11993f1fa9a7Sjfrank int cnt;
12003f1fa9a7Sjfrank int (*scf_service_function)(uint32_t, uint8_t,
12013f1fa9a7Sjfrank uint32_t, uint32_t, void *);
12023f1fa9a7Sjfrank } ctl_msg;
12033f1fa9a7Sjfrank
12043f1fa9a7Sjfrank static void
post_xscf_msg(char * dp,int len)12053f1fa9a7Sjfrank post_xscf_msg(char *dp, int len)
12063f1fa9a7Sjfrank {
12073f1fa9a7Sjfrank nm_msg_t *msg;
12083f1fa9a7Sjfrank
12093f1fa9a7Sjfrank msg = (nm_msg_t *)kmem_zalloc(NM_LEN(len), KM_SLEEP);
12103f1fa9a7Sjfrank
12113f1fa9a7Sjfrank bcopy(dp, msg->data, len);
12123f1fa9a7Sjfrank msg->len = len;
12133f1fa9a7Sjfrank
12143f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
12153f1fa9a7Sjfrank if (ctl_msg.nmt == NULL) {
12163f1fa9a7Sjfrank ctl_msg.nmt = thread_create(NULL, 0, pass2xscf_thread,
12173f1fa9a7Sjfrank NULL, 0, &p0, TS_RUN, minclsyspri);
12183f1fa9a7Sjfrank }
12193f1fa9a7Sjfrank
12203f1fa9a7Sjfrank PUSH(msg);
12213f1fa9a7Sjfrank ctl_msg.cnt++;
12223f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
12233f1fa9a7Sjfrank }
12243f1fa9a7Sjfrank
12253f1fa9a7Sjfrank static void
pass2xscf_thread()12263f1fa9a7Sjfrank pass2xscf_thread()
12273f1fa9a7Sjfrank {
12283f1fa9a7Sjfrank nm_msg_t *msg;
12293f1fa9a7Sjfrank int ret;
12303f1fa9a7Sjfrank uint_t i, msg_sent, xscf_driver_delay;
12313f1fa9a7Sjfrank static uint_t repeat_cnt;
12323f1fa9a7Sjfrank uint_t *scf_wait_cnt;
12333f1fa9a7Sjfrank
12343f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
12353f1fa9a7Sjfrank
12363f1fa9a7Sjfrank /*
12373f1fa9a7Sjfrank * Find the address of the SCF put routine if it's not done yet.
12383f1fa9a7Sjfrank */
12393f1fa9a7Sjfrank if (ctl_msg.scf_service_function == NULL) {
12403f1fa9a7Sjfrank if ((ctl_msg.scf_service_function =
12413f1fa9a7Sjfrank (int (*)(uint32_t, uint8_t, uint32_t, uint32_t, void *))
12423f1fa9a7Sjfrank modgetsymvalue("scf_service_putinfo", 0)) == NULL) {
12433f1fa9a7Sjfrank cmn_err(CE_NOTE, "pass2xscf_thread: "
12443f1fa9a7Sjfrank "scf_service_putinfo not found\n");
12453f1fa9a7Sjfrank ctl_msg.nmt = NULL;
12463f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
12473f1fa9a7Sjfrank return;
12483f1fa9a7Sjfrank }
12493f1fa9a7Sjfrank }
12503f1fa9a7Sjfrank
12513f1fa9a7Sjfrank /*
12523f1fa9a7Sjfrank * Calculate the number of attempts to connect XSCF based on the
12533f1fa9a7Sjfrank * scf driver delay (which is
12543f1fa9a7Sjfrank * SCF_DEVBUSY_DELAY*scf_online_wait_rcnt seconds) and the value
12553f1fa9a7Sjfrank * of xscf_connect_delay (the total number of seconds to wait
12563f1fa9a7Sjfrank * till xscf get ready.)
12573f1fa9a7Sjfrank */
12583f1fa9a7Sjfrank if (repeat_cnt == 0) {
12593f1fa9a7Sjfrank if ((scf_wait_cnt =
12603f1fa9a7Sjfrank (uint_t *)
12613f1fa9a7Sjfrank modgetsymvalue("scf_online_wait_rcnt", 0)) == NULL) {
12623f1fa9a7Sjfrank repeat_cnt = REPEATS;
12633f1fa9a7Sjfrank } else {
12643f1fa9a7Sjfrank
12653f1fa9a7Sjfrank xscf_driver_delay = *scf_wait_cnt *
12663f1fa9a7Sjfrank SCF_DEVBUSY_DELAY;
12673f1fa9a7Sjfrank repeat_cnt = (xscf_connect_delay/xscf_driver_delay) + 1;
12683f1fa9a7Sjfrank }
12693f1fa9a7Sjfrank }
12703f1fa9a7Sjfrank
12713f1fa9a7Sjfrank while (ctl_msg.cnt != 0) {
12723f1fa9a7Sjfrank
12733f1fa9a7Sjfrank /*
12743f1fa9a7Sjfrank * Take the very last request from the queue,
12753f1fa9a7Sjfrank */
12763f1fa9a7Sjfrank ctl_msg.now_serving = ctl_msg.head;
12773f1fa9a7Sjfrank ASSERT(ctl_msg.now_serving != NULL);
12783f1fa9a7Sjfrank
12793f1fa9a7Sjfrank /*
12803f1fa9a7Sjfrank * and discard all the others if any.
12813f1fa9a7Sjfrank */
12823f1fa9a7Sjfrank FREE_THE_TAIL(ctl_msg.now_serving);
12833f1fa9a7Sjfrank ctl_msg.cnt = 1;
12843f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
12853f1fa9a7Sjfrank
12863f1fa9a7Sjfrank /*
12873f1fa9a7Sjfrank * Pass the name to XSCF. Note please, we do not hold the
12883f1fa9a7Sjfrank * mutex while we are doing this.
12893f1fa9a7Sjfrank */
12903f1fa9a7Sjfrank msg_sent = 0;
12913f1fa9a7Sjfrank for (i = 0; i < repeat_cnt; i++) {
12923f1fa9a7Sjfrank if (PASS2XSCF(ctl_msg.now_serving, ret)) {
12933f1fa9a7Sjfrank msg_sent = 1;
12943f1fa9a7Sjfrank break;
12953f1fa9a7Sjfrank } else {
12963f1fa9a7Sjfrank if (ret != EBUSY) {
12973f1fa9a7Sjfrank cmn_err(CE_NOTE, "pass2xscf_thread:"
12983f1fa9a7Sjfrank " unexpected return code"
12993f1fa9a7Sjfrank " from scf_service_putinfo():"
13003f1fa9a7Sjfrank " %d\n", ret);
13013f1fa9a7Sjfrank }
13023f1fa9a7Sjfrank }
13033f1fa9a7Sjfrank }
13043f1fa9a7Sjfrank
13053f1fa9a7Sjfrank if (msg_sent) {
13063f1fa9a7Sjfrank
13073f1fa9a7Sjfrank /*
13083f1fa9a7Sjfrank * Remove the request from the list
13093f1fa9a7Sjfrank */
13103f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
13113f1fa9a7Sjfrank msg = ctl_msg.now_serving;
13123f1fa9a7Sjfrank ctl_msg.now_serving = NULL;
13133f1fa9a7Sjfrank REMOVE(msg);
13143f1fa9a7Sjfrank ctl_msg.cnt--;
13153f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
13163f1fa9a7Sjfrank FREE_MSG(msg);
13173f1fa9a7Sjfrank } else {
13183f1fa9a7Sjfrank
13193f1fa9a7Sjfrank /*
13203f1fa9a7Sjfrank * If while we have tried to communicate with
13213f1fa9a7Sjfrank * XSCF there were any other requests we are
13223f1fa9a7Sjfrank * going to drop this one and take the latest
13233f1fa9a7Sjfrank * one. Otherwise we will try to pass this one
13243f1fa9a7Sjfrank * again.
13253f1fa9a7Sjfrank */
13263f1fa9a7Sjfrank cmn_err(CE_NOTE,
13273f1fa9a7Sjfrank "pass2xscf_thread: "
13283f1fa9a7Sjfrank "scf_service_putinfo "
13293f1fa9a7Sjfrank "not responding\n");
13303f1fa9a7Sjfrank }
13313f1fa9a7Sjfrank mutex_enter(&ctl_msg.nm_lock);
13323f1fa9a7Sjfrank }
13333f1fa9a7Sjfrank
13343f1fa9a7Sjfrank /*
13353f1fa9a7Sjfrank * The request queue is empty, exit.
13363f1fa9a7Sjfrank */
13373f1fa9a7Sjfrank ctl_msg.nmt = NULL;
13383f1fa9a7Sjfrank mutex_exit(&ctl_msg.nm_lock);
13393f1fa9a7Sjfrank }
1340