1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/kmem.h> 30 #include <sys/conf.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/sunndi.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/fm/util.h> 36 #include <sys/modctl.h> 37 #include <sys/disp.h> 38 #include <sys/stat.h> 39 #include <sys/ddi_impldefs.h> 40 #include <sys/vmem.h> 41 #include <sys/iommutsb.h> 42 #include <sys/cpuvar.h> 43 #include <sys/ivintr.h> 44 #include <sys/byteorder.h> 45 #include <sys/hotplug/pci/pciehpc.h> 46 #include <sys/spl.h> 47 #include <px_obj.h> 48 #include <pcie_pwr.h> 49 #include "px_tools_var.h" 50 #include <px_regs.h> 51 #include <px_csr.h> 52 #include <sys/machsystm.h> 53 #include "px_lib4u.h" 54 #include "px_err.h" 55 #include "oberon_regs.h" 56 57 #pragma weak jbus_stst_order 58 59 extern void jbus_stst_order(); 60 61 ulong_t px_mmu_dvma_end = 0xfffffffful; 62 uint_t px_ranges_phi_mask = 0xfffffffful; 63 uint64_t *px_oberon_ubc_scratch_regs; 64 uint64_t px_paddr_mask; 65 66 static int px_goto_l23ready(px_t *px_p); 67 static int px_goto_l0(px_t *px_p); 68 static int px_pre_pwron_check(px_t *px_p); 69 static uint32_t px_identity_init(px_t *px_p); 70 static boolean_t px_cpr_callb(void *arg, int code); 71 static uint_t px_cb_intr(caddr_t arg); 72 73 /* 74 * px_lib_map_registers 75 * 76 * This function is called from the attach routine to map the registers 77 * accessed by this driver. 78 * 79 * used by: px_attach() 80 * 81 * return value: DDI_FAILURE on failure 82 */ 83 int 84 px_lib_map_regs(pxu_t *pxu_p, dev_info_t *dip) 85 { 86 ddi_device_acc_attr_t attr; 87 px_reg_bank_t reg_bank = PX_REG_CSR; 88 89 DBG(DBG_ATTACH, dip, "px_lib_map_regs: pxu_p:0x%p, dip 0x%p\n", 90 pxu_p, dip); 91 92 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 93 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 94 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 95 96 /* 97 * PCI CSR Base 98 */ 99 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 100 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 101 goto fail; 102 } 103 104 reg_bank++; 105 106 /* 107 * XBUS CSR Base 108 */ 109 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 110 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 111 goto fail; 112 } 113 114 pxu_p->px_address[reg_bank] -= FIRE_CONTROL_STATUS; 115 116 done: 117 for (; reg_bank >= PX_REG_CSR; reg_bank--) { 118 DBG(DBG_ATTACH, dip, "reg_bank 0x%x address 0x%p\n", 119 reg_bank, pxu_p->px_address[reg_bank]); 120 } 121 122 return (DDI_SUCCESS); 123 124 fail: 125 cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 126 ddi_driver_name(dip), ddi_get_instance(dip), reg_bank); 127 128 for (reg_bank--; reg_bank >= PX_REG_CSR; reg_bank--) { 129 pxu_p->px_address[reg_bank] = NULL; 130 ddi_regs_map_free(&pxu_p->px_ac[reg_bank]); 131 } 132 133 return (DDI_FAILURE); 134 } 135 136 /* 137 * px_lib_unmap_regs: 138 * 139 * This routine unmaps the registers mapped by map_px_registers. 140 * 141 * used by: px_detach(), and error conditions in px_attach() 142 * 143 * return value: none 144 */ 145 void 146 px_lib_unmap_regs(pxu_t *pxu_p) 147 { 148 int i; 149 150 for (i = 0; i < PX_REG_MAX; i++) { 151 if (pxu_p->px_ac[i]) 152 ddi_regs_map_free(&pxu_p->px_ac[i]); 153 } 154 } 155 156 int 157 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 158 { 159 160 caddr_t xbc_csr_base, csr_base; 161 px_dvma_range_prop_t px_dvma_range; 162 pxu_t *pxu_p; 163 uint8_t chip_mask; 164 px_t *px_p = DIP_TO_STATE(dip); 165 px_chip_type_t chip_type = px_identity_init(px_p); 166 167 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p", dip); 168 169 if (chip_type == PX_CHIP_UNIDENTIFIED) { 170 cmn_err(CE_WARN, "%s%d: Unrecognized Hardware Version\n", 171 NAMEINST(dip)); 172 return (DDI_FAILURE); 173 } 174 175 chip_mask = BITMASK(chip_type); 176 px_paddr_mask = (chip_type == PX_CHIP_FIRE) ? MMU_FIRE_PADDR_MASK : 177 MMU_OBERON_PADDR_MASK; 178 179 /* 180 * Allocate platform specific structure and link it to 181 * the px state structure. 182 */ 183 pxu_p = kmem_zalloc(sizeof (pxu_t), KM_SLEEP); 184 pxu_p->chip_type = chip_type; 185 pxu_p->portid = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 186 "portid", -1); 187 188 /* Map in the registers */ 189 if (px_lib_map_regs(pxu_p, dip) == DDI_FAILURE) { 190 kmem_free(pxu_p, sizeof (pxu_t)); 191 192 return (DDI_FAILURE); 193 } 194 195 xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 196 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 197 198 pxu_p->tsb_cookie = iommu_tsb_alloc(pxu_p->portid); 199 pxu_p->tsb_size = iommu_tsb_cookie_to_size(pxu_p->tsb_cookie); 200 pxu_p->tsb_vaddr = iommu_tsb_cookie_to_va(pxu_p->tsb_cookie); 201 202 pxu_p->tsb_paddr = va_to_pa(pxu_p->tsb_vaddr); 203 204 /* 205 * Create "virtual-dma" property to support child devices 206 * needing to know DVMA range. 207 */ 208 px_dvma_range.dvma_base = (uint32_t)px_mmu_dvma_end + 1 209 - ((pxu_p->tsb_size >> 3) << MMU_PAGE_SHIFT); 210 px_dvma_range.dvma_len = (uint32_t) 211 px_mmu_dvma_end - px_dvma_range.dvma_base + 1; 212 213 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 214 "virtual-dma", (int *)&px_dvma_range, 215 sizeof (px_dvma_range_prop_t) / sizeof (int)); 216 /* 217 * Initilize all fire hardware specific blocks. 218 */ 219 hvio_cb_init(xbc_csr_base, pxu_p); 220 hvio_ib_init(csr_base, pxu_p); 221 hvio_pec_init(csr_base, pxu_p); 222 hvio_mmu_init(csr_base, pxu_p); 223 224 px_p->px_plat_p = (void *)pxu_p; 225 226 /* 227 * Initialize all the interrupt handlers 228 */ 229 switch (PX_CHIP_TYPE(pxu_p)) { 230 case PX_CHIP_OBERON: 231 /* 232 * Oberon hotplug uses SPARE3 field in ILU Error Log Enable 233 * register to indicate the status of leaf reset, 234 * we need to preserve the value of this bit, and keep it in 235 * px_ilu_log_mask to reflect the state of the bit 236 */ 237 if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3)) 238 px_ilu_log_mask |= (1ull << 239 ILU_ERROR_LOG_ENABLE_SPARE3); 240 else 241 px_ilu_log_mask &= ~(1ull << 242 ILU_ERROR_LOG_ENABLE_SPARE3); 243 244 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 245 break; 246 247 case PX_CHIP_FIRE: 248 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 249 break; 250 251 default: 252 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 253 ddi_driver_name(dip), ddi_get_instance(dip)); 254 return (DDI_FAILURE); 255 } 256 257 /* Initilize device handle */ 258 *dev_hdl = (devhandle_t)csr_base; 259 260 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 261 262 return (DDI_SUCCESS); 263 } 264 265 int 266 px_lib_dev_fini(dev_info_t *dip) 267 { 268 caddr_t csr_base; 269 uint8_t chip_mask; 270 px_t *px_p = DIP_TO_STATE(dip); 271 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 272 273 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 274 275 /* 276 * Deinitialize all the interrupt handlers 277 */ 278 switch (PX_CHIP_TYPE(pxu_p)) { 279 case PX_CHIP_OBERON: 280 case PX_CHIP_FIRE: 281 chip_mask = BITMASK(PX_CHIP_TYPE(pxu_p)); 282 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 283 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_DISABLE); 284 break; 285 286 default: 287 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 288 ddi_driver_name(dip), ddi_get_instance(dip)); 289 return (DDI_FAILURE); 290 } 291 292 iommu_tsb_free(pxu_p->tsb_cookie); 293 294 px_lib_unmap_regs((pxu_t *)px_p->px_plat_p); 295 kmem_free(px_p->px_plat_p, sizeof (pxu_t)); 296 px_p->px_plat_p = NULL; 297 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "virtual-dma"); 298 299 return (DDI_SUCCESS); 300 } 301 302 /*ARGSUSED*/ 303 int 304 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 305 sysino_t *sysino) 306 { 307 px_t *px_p = DIP_TO_STATE(dip); 308 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 309 uint64_t ret; 310 311 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 312 "devino 0x%x\n", dip, devino); 313 314 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 315 pxu_p, devino, sysino)) != H_EOK) { 316 DBG(DBG_LIB_INT, dip, 317 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 318 return (DDI_FAILURE); 319 } 320 321 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 322 *sysino); 323 324 return (DDI_SUCCESS); 325 } 326 327 /*ARGSUSED*/ 328 int 329 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 330 intr_valid_state_t *intr_valid_state) 331 { 332 uint64_t ret; 333 334 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 335 dip, sysino); 336 337 if ((ret = hvio_intr_getvalid(DIP_TO_HANDLE(dip), 338 sysino, intr_valid_state)) != H_EOK) { 339 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 340 ret); 341 return (DDI_FAILURE); 342 } 343 344 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 345 *intr_valid_state); 346 347 return (DDI_SUCCESS); 348 } 349 350 /*ARGSUSED*/ 351 int 352 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 353 intr_valid_state_t intr_valid_state) 354 { 355 uint64_t ret; 356 357 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 358 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 359 360 if ((ret = hvio_intr_setvalid(DIP_TO_HANDLE(dip), 361 sysino, intr_valid_state)) != H_EOK) { 362 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 363 ret); 364 return (DDI_FAILURE); 365 } 366 367 return (DDI_SUCCESS); 368 } 369 370 /*ARGSUSED*/ 371 int 372 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 373 intr_state_t *intr_state) 374 { 375 uint64_t ret; 376 377 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 378 dip, sysino); 379 380 if ((ret = hvio_intr_getstate(DIP_TO_HANDLE(dip), 381 sysino, intr_state)) != H_EOK) { 382 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 383 ret); 384 return (DDI_FAILURE); 385 } 386 387 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 388 *intr_state); 389 390 return (DDI_SUCCESS); 391 } 392 393 /*ARGSUSED*/ 394 int 395 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 396 intr_state_t intr_state) 397 { 398 uint64_t ret; 399 400 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 401 "intr_state 0x%x\n", dip, sysino, intr_state); 402 403 if ((ret = hvio_intr_setstate(DIP_TO_HANDLE(dip), 404 sysino, intr_state)) != H_EOK) { 405 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 406 ret); 407 return (DDI_FAILURE); 408 } 409 410 return (DDI_SUCCESS); 411 } 412 413 /*ARGSUSED*/ 414 int 415 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 416 { 417 px_t *px_p = DIP_TO_STATE(dip); 418 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 419 uint64_t ret; 420 421 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 422 dip, sysino); 423 424 if ((ret = hvio_intr_gettarget(DIP_TO_HANDLE(dip), pxu_p, 425 sysino, cpuid)) != H_EOK) { 426 DBG(DBG_LIB_INT, dip, "hvio_intr_gettarget failed, ret 0x%lx\n", 427 ret); 428 return (DDI_FAILURE); 429 } 430 431 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 432 433 return (DDI_SUCCESS); 434 } 435 436 /*ARGSUSED*/ 437 int 438 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 439 { 440 px_t *px_p = DIP_TO_STATE(dip); 441 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 442 uint64_t ret; 443 444 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 445 "cpuid 0x%x\n", dip, sysino, cpuid); 446 447 if ((ret = hvio_intr_settarget(DIP_TO_HANDLE(dip), pxu_p, 448 sysino, cpuid)) != H_EOK) { 449 DBG(DBG_LIB_INT, dip, "hvio_intr_settarget failed, ret 0x%lx\n", 450 ret); 451 return (DDI_FAILURE); 452 } 453 454 return (DDI_SUCCESS); 455 } 456 457 /*ARGSUSED*/ 458 int 459 px_lib_intr_reset(dev_info_t *dip) 460 { 461 devino_t ino; 462 sysino_t sysino; 463 464 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 465 466 /* Reset all Interrupts */ 467 for (ino = 0; ino < INTERRUPT_MAPPING_ENTRIES; ino++) { 468 if (px_lib_intr_devino_to_sysino(dip, ino, 469 &sysino) != DDI_SUCCESS) 470 return (BF_FATAL); 471 472 if (px_lib_intr_setstate(dip, sysino, 473 INTR_IDLE_STATE) != DDI_SUCCESS) 474 return (BF_FATAL); 475 } 476 477 return (BF_NONE); 478 } 479 480 /*ARGSUSED*/ 481 int 482 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 483 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 484 { 485 px_t *px_p = DIP_TO_STATE(dip); 486 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 487 uint64_t ret; 488 489 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 490 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 491 dip, tsbid, pages, attr, addr, pfn_index, flags); 492 493 if ((ret = hvio_iommu_map(px_p->px_dev_hdl, pxu_p, tsbid, pages, 494 attr, addr, pfn_index, flags)) != H_EOK) { 495 DBG(DBG_LIB_DMA, dip, 496 "px_lib_iommu_map failed, ret 0x%lx\n", ret); 497 return (DDI_FAILURE); 498 } 499 500 return (DDI_SUCCESS); 501 } 502 503 /*ARGSUSED*/ 504 int 505 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 506 { 507 px_t *px_p = DIP_TO_STATE(dip); 508 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 509 uint64_t ret; 510 511 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 512 "pages 0x%x\n", dip, tsbid, pages); 513 514 if ((ret = hvio_iommu_demap(px_p->px_dev_hdl, pxu_p, tsbid, pages)) 515 != H_EOK) { 516 DBG(DBG_LIB_DMA, dip, 517 "px_lib_iommu_demap failed, ret 0x%lx\n", ret); 518 519 return (DDI_FAILURE); 520 } 521 522 return (DDI_SUCCESS); 523 } 524 525 /*ARGSUSED*/ 526 int 527 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 528 r_addr_t *r_addr_p) 529 { 530 px_t *px_p = DIP_TO_STATE(dip); 531 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 532 uint64_t ret; 533 534 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 535 dip, tsbid); 536 537 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), pxu_p, tsbid, 538 attr_p, r_addr_p)) != H_EOK) { 539 DBG(DBG_LIB_DMA, dip, 540 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 541 542 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 543 } 544 545 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 546 *attr_p, *r_addr_p); 547 548 return (DDI_SUCCESS); 549 } 550 551 552 /* 553 * Checks dma attributes against system bypass ranges 554 * The bypass range is determined by the hardware. Return them so the 555 * common code can do generic checking against them. 556 */ 557 /*ARGSUSED*/ 558 int 559 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 560 uint64_t *lo_p, uint64_t *hi_p) 561 { 562 px_t *px_p = DIP_TO_STATE(dip); 563 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 564 565 *lo_p = hvio_get_bypass_base(pxu_p); 566 *hi_p = hvio_get_bypass_end(pxu_p); 567 568 return (DDI_SUCCESS); 569 } 570 571 572 /*ARGSUSED*/ 573 int 574 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 575 io_addr_t *io_addr_p) 576 { 577 uint64_t ret; 578 px_t *px_p = DIP_TO_STATE(dip); 579 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 580 581 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 582 "attr 0x%x\n", dip, ra, attr); 583 584 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), pxu_p, ra, 585 attr, io_addr_p)) != H_EOK) { 586 DBG(DBG_LIB_DMA, dip, 587 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 588 return (DDI_FAILURE); 589 } 590 591 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 592 *io_addr_p); 593 594 return (DDI_SUCCESS); 595 } 596 597 /* 598 * bus dma sync entry point. 599 */ 600 /*ARGSUSED*/ 601 int 602 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 603 off_t off, size_t len, uint_t cache_flags) 604 { 605 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 606 px_t *px_p = DIP_TO_STATE(dip); 607 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 608 609 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 610 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 611 dip, rdip, handle, off, len, cache_flags); 612 613 /* 614 * No flush needed for Oberon 615 */ 616 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 617 return (DDI_SUCCESS); 618 619 /* 620 * jbus_stst_order is found only in certain cpu modules. 621 * Just return success if not present. 622 */ 623 if (&jbus_stst_order == NULL) 624 return (DDI_SUCCESS); 625 626 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 627 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 628 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 629 630 return (DDI_FAILURE); 631 } 632 633 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 634 return (DDI_SUCCESS); 635 636 /* 637 * No flush needed when sending data from memory to device. 638 * Nothing to do to "sync" memory to what device would already see. 639 */ 640 if (!(mp->dmai_rflags & DDI_DMA_READ) || 641 ((cache_flags & PX_DMA_SYNC_DDI_FLAGS) == DDI_DMA_SYNC_FORDEV)) 642 return (DDI_SUCCESS); 643 644 /* 645 * Perform necessary cpu workaround to ensure jbus ordering. 646 * CPU's internal "invalidate FIFOs" are flushed. 647 */ 648 649 #if !defined(lint) 650 kpreempt_disable(); 651 #endif 652 jbus_stst_order(); 653 #if !defined(lint) 654 kpreempt_enable(); 655 #endif 656 return (DDI_SUCCESS); 657 } 658 659 /* 660 * MSIQ Functions: 661 */ 662 /*ARGSUSED*/ 663 int 664 px_lib_msiq_init(dev_info_t *dip) 665 { 666 px_t *px_p = DIP_TO_STATE(dip); 667 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 668 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 669 px_dvma_addr_t pg_index; 670 size_t size; 671 int ret; 672 673 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 674 675 /* 676 * Map the EQ memory into the Fire MMU (has to be 512KB aligned) 677 * and then initialize the base address register. 678 * 679 * Allocate entries from Fire IOMMU so that the resulting address 680 * is properly aligned. Calculate the index of the first allocated 681 * entry. Note: The size of the mapping is assumed to be a multiple 682 * of the page size. 683 */ 684 size = msiq_state_p->msiq_cnt * 685 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 686 687 pxu_p->msiq_mapped_p = vmem_xalloc(px_p->px_mmu_p->mmu_dvma_map, 688 size, (512 * 1024), 0, 0, NULL, NULL, VM_NOSLEEP | VM_BESTFIT); 689 690 if (pxu_p->msiq_mapped_p == NULL) 691 return (DDI_FAILURE); 692 693 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 694 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 695 696 if ((ret = px_lib_iommu_map(px_p->px_dip, PCI_TSBID(0, pg_index), 697 MMU_BTOP(size), PCI_MAP_ATTR_WRITE, msiq_state_p->msiq_buf_p, 698 0, MMU_MAP_BUF)) != DDI_SUCCESS) { 699 DBG(DBG_LIB_MSIQ, dip, 700 "px_lib_msiq_init: px_lib_iommu_map failed, " 701 "ret 0x%lx\n", ret); 702 703 (void) px_lib_msiq_fini(dip); 704 return (DDI_FAILURE); 705 } 706 707 (void) hvio_msiq_init(DIP_TO_HANDLE(dip), pxu_p); 708 709 return (DDI_SUCCESS); 710 } 711 712 /*ARGSUSED*/ 713 int 714 px_lib_msiq_fini(dev_info_t *dip) 715 { 716 px_t *px_p = DIP_TO_STATE(dip); 717 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 718 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 719 px_dvma_addr_t pg_index; 720 size_t size; 721 722 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 723 724 /* 725 * Unmap and free the EQ memory that had been mapped 726 * into the Fire IOMMU. 727 */ 728 size = msiq_state_p->msiq_cnt * 729 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 730 731 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 732 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 733 734 (void) px_lib_iommu_demap(px_p->px_dip, 735 PCI_TSBID(0, pg_index), MMU_BTOP(size)); 736 737 /* Free the entries from the Fire MMU */ 738 vmem_xfree(px_p->px_mmu_p->mmu_dvma_map, 739 (void *)pxu_p->msiq_mapped_p, size); 740 741 return (DDI_SUCCESS); 742 } 743 744 /*ARGSUSED*/ 745 int 746 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 747 uint_t *msiq_rec_cnt_p) 748 { 749 px_t *px_p = DIP_TO_STATE(dip); 750 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 751 size_t msiq_size; 752 753 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 754 dip, msiq_id); 755 756 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 757 ra_p = (r_addr_t *)((caddr_t)msiq_state_p->msiq_buf_p + 758 (msiq_id * msiq_size)); 759 760 *msiq_rec_cnt_p = msiq_state_p->msiq_rec_cnt; 761 762 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 763 ra_p, *msiq_rec_cnt_p); 764 765 return (DDI_SUCCESS); 766 } 767 768 /*ARGSUSED*/ 769 int 770 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 771 pci_msiq_valid_state_t *msiq_valid_state) 772 { 773 uint64_t ret; 774 775 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 776 dip, msiq_id); 777 778 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 779 msiq_id, msiq_valid_state)) != H_EOK) { 780 DBG(DBG_LIB_MSIQ, dip, 781 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 782 return (DDI_FAILURE); 783 } 784 785 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 786 *msiq_valid_state); 787 788 return (DDI_SUCCESS); 789 } 790 791 /*ARGSUSED*/ 792 int 793 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 794 pci_msiq_valid_state_t msiq_valid_state) 795 { 796 uint64_t ret; 797 798 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 799 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 800 801 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 802 msiq_id, msiq_valid_state)) != H_EOK) { 803 DBG(DBG_LIB_MSIQ, dip, 804 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 805 return (DDI_FAILURE); 806 } 807 808 return (DDI_SUCCESS); 809 } 810 811 /*ARGSUSED*/ 812 int 813 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 814 pci_msiq_state_t *msiq_state) 815 { 816 uint64_t ret; 817 818 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 819 dip, msiq_id); 820 821 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 822 msiq_id, msiq_state)) != H_EOK) { 823 DBG(DBG_LIB_MSIQ, dip, 824 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 825 return (DDI_FAILURE); 826 } 827 828 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 829 *msiq_state); 830 831 return (DDI_SUCCESS); 832 } 833 834 /*ARGSUSED*/ 835 int 836 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 837 pci_msiq_state_t msiq_state) 838 { 839 uint64_t ret; 840 841 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 842 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 843 844 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 845 msiq_id, msiq_state)) != H_EOK) { 846 DBG(DBG_LIB_MSIQ, dip, 847 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 848 return (DDI_FAILURE); 849 } 850 851 return (DDI_SUCCESS); 852 } 853 854 /*ARGSUSED*/ 855 int 856 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 857 msiqhead_t *msiq_head) 858 { 859 uint64_t ret; 860 861 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 862 dip, msiq_id); 863 864 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 865 msiq_id, msiq_head)) != H_EOK) { 866 DBG(DBG_LIB_MSIQ, dip, 867 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 868 return (DDI_FAILURE); 869 } 870 871 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: msiq_head 0x%x\n", 872 *msiq_head); 873 874 return (DDI_SUCCESS); 875 } 876 877 /*ARGSUSED*/ 878 int 879 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 880 msiqhead_t msiq_head) 881 { 882 uint64_t ret; 883 884 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 885 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 886 887 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 888 msiq_id, msiq_head)) != H_EOK) { 889 DBG(DBG_LIB_MSIQ, dip, 890 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 891 return (DDI_FAILURE); 892 } 893 894 return (DDI_SUCCESS); 895 } 896 897 /*ARGSUSED*/ 898 int 899 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 900 msiqtail_t *msiq_tail) 901 { 902 uint64_t ret; 903 904 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 905 dip, msiq_id); 906 907 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 908 msiq_id, msiq_tail)) != H_EOK) { 909 DBG(DBG_LIB_MSIQ, dip, 910 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 911 return (DDI_FAILURE); 912 } 913 914 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 915 *msiq_tail); 916 917 return (DDI_SUCCESS); 918 } 919 920 /*ARGSUSED*/ 921 void 922 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 923 msiq_rec_t *msiq_rec_p) 924 { 925 eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_head_p; 926 927 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 928 dip, eq_rec_p); 929 930 if (!eq_rec_p->eq_rec_fmt_type) { 931 /* Set msiq_rec_type to zero */ 932 msiq_rec_p->msiq_rec_type = 0; 933 934 return; 935 } 936 937 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: EQ RECORD, " 938 "eq_rec_rid 0x%llx eq_rec_fmt_type 0x%llx " 939 "eq_rec_len 0x%llx eq_rec_addr0 0x%llx " 940 "eq_rec_addr1 0x%llx eq_rec_data0 0x%llx " 941 "eq_rec_data1 0x%llx\n", eq_rec_p->eq_rec_rid, 942 eq_rec_p->eq_rec_fmt_type, eq_rec_p->eq_rec_len, 943 eq_rec_p->eq_rec_addr0, eq_rec_p->eq_rec_addr1, 944 eq_rec_p->eq_rec_data0, eq_rec_p->eq_rec_data1); 945 946 /* 947 * Only upper 4 bits of eq_rec_fmt_type is used 948 * to identify the EQ record type. 949 */ 950 switch (eq_rec_p->eq_rec_fmt_type >> 3) { 951 case EQ_REC_MSI32: 952 msiq_rec_p->msiq_rec_type = MSI32_REC; 953 954 msiq_rec_p->msiq_rec_data.msi.msi_data = 955 eq_rec_p->eq_rec_data0; 956 break; 957 case EQ_REC_MSI64: 958 msiq_rec_p->msiq_rec_type = MSI64_REC; 959 960 msiq_rec_p->msiq_rec_data.msi.msi_data = 961 eq_rec_p->eq_rec_data0; 962 break; 963 case EQ_REC_MSG: 964 msiq_rec_p->msiq_rec_type = MSG_REC; 965 966 msiq_rec_p->msiq_rec_data.msg.msg_route = 967 eq_rec_p->eq_rec_fmt_type & 7; 968 msiq_rec_p->msiq_rec_data.msg.msg_targ = eq_rec_p->eq_rec_rid; 969 msiq_rec_p->msiq_rec_data.msg.msg_code = eq_rec_p->eq_rec_data0; 970 break; 971 default: 972 cmn_err(CE_WARN, "%s%d: px_lib_get_msiq_rec: " 973 "0x%x is an unknown EQ record type", 974 ddi_driver_name(dip), ddi_get_instance(dip), 975 (int)eq_rec_p->eq_rec_fmt_type); 976 break; 977 } 978 979 msiq_rec_p->msiq_rec_rid = eq_rec_p->eq_rec_rid; 980 msiq_rec_p->msiq_rec_msi_addr = ((eq_rec_p->eq_rec_addr1 << 16) | 981 (eq_rec_p->eq_rec_addr0 << 2)); 982 } 983 984 /*ARGSUSED*/ 985 void 986 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 987 { 988 eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_head_p; 989 990 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 991 dip, eq_rec_p); 992 993 if (eq_rec_p->eq_rec_fmt_type) { 994 /* Zero out eq_rec_fmt_type field */ 995 eq_rec_p->eq_rec_fmt_type = 0; 996 } 997 } 998 999 /* 1000 * MSI Functions: 1001 */ 1002 /*ARGSUSED*/ 1003 int 1004 px_lib_msi_init(dev_info_t *dip) 1005 { 1006 px_t *px_p = DIP_TO_STATE(dip); 1007 px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 1008 uint64_t ret; 1009 1010 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 1011 1012 if ((ret = hvio_msi_init(DIP_TO_HANDLE(dip), 1013 msi_state_p->msi_addr32, msi_state_p->msi_addr64)) != H_EOK) { 1014 DBG(DBG_LIB_MSIQ, dip, "px_lib_msi_init failed, ret 0x%lx\n", 1015 ret); 1016 return (DDI_FAILURE); 1017 } 1018 1019 return (DDI_SUCCESS); 1020 } 1021 1022 /*ARGSUSED*/ 1023 int 1024 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 1025 msiqid_t *msiq_id) 1026 { 1027 uint64_t ret; 1028 1029 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 1030 dip, msi_num); 1031 1032 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 1033 msi_num, msiq_id)) != H_EOK) { 1034 DBG(DBG_LIB_MSI, dip, 1035 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 1036 return (DDI_FAILURE); 1037 } 1038 1039 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 1040 *msiq_id); 1041 1042 return (DDI_SUCCESS); 1043 } 1044 1045 /*ARGSUSED*/ 1046 int 1047 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 1048 msiqid_t msiq_id, msi_type_t msitype) 1049 { 1050 uint64_t ret; 1051 1052 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 1053 "msq_id 0x%x\n", dip, msi_num, msiq_id); 1054 1055 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 1056 msi_num, msiq_id)) != H_EOK) { 1057 DBG(DBG_LIB_MSI, dip, 1058 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 1059 return (DDI_FAILURE); 1060 } 1061 1062 return (DDI_SUCCESS); 1063 } 1064 1065 /*ARGSUSED*/ 1066 int 1067 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 1068 pci_msi_valid_state_t *msi_valid_state) 1069 { 1070 uint64_t ret; 1071 1072 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 1073 dip, msi_num); 1074 1075 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 1076 msi_num, msi_valid_state)) != H_EOK) { 1077 DBG(DBG_LIB_MSI, dip, 1078 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 1079 return (DDI_FAILURE); 1080 } 1081 1082 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 1083 *msi_valid_state); 1084 1085 return (DDI_SUCCESS); 1086 } 1087 1088 /*ARGSUSED*/ 1089 int 1090 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 1091 pci_msi_valid_state_t msi_valid_state) 1092 { 1093 uint64_t ret; 1094 1095 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 1096 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 1097 1098 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 1099 msi_num, msi_valid_state)) != H_EOK) { 1100 DBG(DBG_LIB_MSI, dip, 1101 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 1102 return (DDI_FAILURE); 1103 } 1104 1105 return (DDI_SUCCESS); 1106 } 1107 1108 /*ARGSUSED*/ 1109 int 1110 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 1111 pci_msi_state_t *msi_state) 1112 { 1113 uint64_t ret; 1114 1115 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 1116 dip, msi_num); 1117 1118 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 1119 msi_num, msi_state)) != H_EOK) { 1120 DBG(DBG_LIB_MSI, dip, 1121 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 1122 return (DDI_FAILURE); 1123 } 1124 1125 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 1126 *msi_state); 1127 1128 return (DDI_SUCCESS); 1129 } 1130 1131 /*ARGSUSED*/ 1132 int 1133 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 1134 pci_msi_state_t msi_state) 1135 { 1136 uint64_t ret; 1137 1138 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 1139 "msi_state 0x%x\n", dip, msi_num, msi_state); 1140 1141 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 1142 msi_num, msi_state)) != H_EOK) { 1143 DBG(DBG_LIB_MSI, dip, 1144 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 1145 return (DDI_FAILURE); 1146 } 1147 1148 return (DDI_SUCCESS); 1149 } 1150 1151 /* 1152 * MSG Functions: 1153 */ 1154 /*ARGSUSED*/ 1155 int 1156 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1157 msiqid_t *msiq_id) 1158 { 1159 uint64_t ret; 1160 1161 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1162 dip, msg_type); 1163 1164 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1165 msg_type, msiq_id)) != H_EOK) { 1166 DBG(DBG_LIB_MSG, dip, 1167 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1168 return (DDI_FAILURE); 1169 } 1170 1171 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1172 *msiq_id); 1173 1174 return (DDI_SUCCESS); 1175 } 1176 1177 /*ARGSUSED*/ 1178 int 1179 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1180 msiqid_t msiq_id) 1181 { 1182 uint64_t ret; 1183 1184 DBG(DBG_LIB_MSG, dip, "px_lib_msi_setstate: dip 0x%p msg_type 0x%x " 1185 "msiq_id 0x%x\n", dip, msg_type, msiq_id); 1186 1187 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1188 msg_type, msiq_id)) != H_EOK) { 1189 DBG(DBG_LIB_MSG, dip, 1190 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1191 return (DDI_FAILURE); 1192 } 1193 1194 return (DDI_SUCCESS); 1195 } 1196 1197 /*ARGSUSED*/ 1198 int 1199 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1200 pcie_msg_valid_state_t *msg_valid_state) 1201 { 1202 uint64_t ret; 1203 1204 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1205 dip, msg_type); 1206 1207 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1208 msg_valid_state)) != H_EOK) { 1209 DBG(DBG_LIB_MSG, dip, 1210 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1211 return (DDI_FAILURE); 1212 } 1213 1214 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1215 *msg_valid_state); 1216 1217 return (DDI_SUCCESS); 1218 } 1219 1220 /*ARGSUSED*/ 1221 int 1222 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1223 pcie_msg_valid_state_t msg_valid_state) 1224 { 1225 uint64_t ret; 1226 1227 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1228 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1229 1230 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1231 msg_valid_state)) != H_EOK) { 1232 DBG(DBG_LIB_MSG, dip, 1233 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1234 return (DDI_FAILURE); 1235 } 1236 1237 return (DDI_SUCCESS); 1238 } 1239 1240 /* 1241 * Suspend/Resume Functions: 1242 * Currently unsupported by hypervisor 1243 */ 1244 int 1245 px_lib_suspend(dev_info_t *dip) 1246 { 1247 px_t *px_p = DIP_TO_STATE(dip); 1248 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1249 px_cb_t *cb_p = PX2CB(px_p); 1250 devhandle_t dev_hdl, xbus_dev_hdl; 1251 uint64_t ret = H_EOK; 1252 1253 DBG(DBG_DETACH, dip, "px_lib_suspend: dip 0x%p\n", dip); 1254 1255 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1256 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1257 1258 if ((ret = hvio_suspend(dev_hdl, pxu_p)) != H_EOK) 1259 goto fail; 1260 1261 if (--cb_p->attachcnt == 0) { 1262 ret = hvio_cb_suspend(xbus_dev_hdl, pxu_p); 1263 if (ret != H_EOK) 1264 cb_p->attachcnt++; 1265 } 1266 pxu_p->cpr_flag = PX_ENTERED_CPR; 1267 1268 fail: 1269 return ((ret != H_EOK) ? DDI_FAILURE: DDI_SUCCESS); 1270 } 1271 1272 void 1273 px_lib_resume(dev_info_t *dip) 1274 { 1275 px_t *px_p = DIP_TO_STATE(dip); 1276 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1277 px_cb_t *cb_p = PX2CB(px_p); 1278 devhandle_t dev_hdl, xbus_dev_hdl; 1279 devino_t pec_ino = px_p->px_inos[PX_INTR_PEC]; 1280 devino_t xbc_ino = px_p->px_inos[PX_INTR_XBC]; 1281 1282 DBG(DBG_ATTACH, dip, "px_lib_resume: dip 0x%p\n", dip); 1283 1284 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1285 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1286 1287 if (++cb_p->attachcnt == 1) 1288 hvio_cb_resume(dev_hdl, xbus_dev_hdl, xbc_ino, pxu_p); 1289 1290 hvio_resume(dev_hdl, pec_ino, pxu_p); 1291 } 1292 1293 /* 1294 * Generate a unique Oberon UBC ID based on the Logicial System Board and 1295 * the IO Channel from the portid property field. 1296 */ 1297 static uint64_t 1298 oberon_get_ubc_id(dev_info_t *dip) 1299 { 1300 px_t *px_p = DIP_TO_STATE(dip); 1301 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1302 uint64_t ubc_id; 1303 1304 /* 1305 * Generate a unique 6 bit UBC ID using the 2 IO_Channel#[1:0] bits and 1306 * the 4 LSB_ID[3:0] bits from the Oberon's portid property. 1307 */ 1308 ubc_id = (((pxu_p->portid >> OBERON_PORT_ID_IOC) & 1309 OBERON_PORT_ID_IOC_MASK) | (((pxu_p->portid >> 1310 OBERON_PORT_ID_LSB) & OBERON_PORT_ID_LSB_MASK) 1311 << OBERON_UBC_ID_LSB)); 1312 1313 return (ubc_id); 1314 } 1315 1316 /* 1317 * Oberon does not have a UBC scratch register, so alloc an array of scratch 1318 * registers when needed and use a unique UBC ID as an index. This code 1319 * can be simplified if we use a pre-allocated array. They are currently 1320 * being dynamically allocated because it's only needed by the Oberon. 1321 */ 1322 static void 1323 oberon_set_cb(dev_info_t *dip, uint64_t val) 1324 { 1325 uint64_t ubc_id; 1326 1327 if (px_oberon_ubc_scratch_regs == NULL) 1328 px_oberon_ubc_scratch_regs = 1329 (uint64_t *)kmem_zalloc(sizeof (uint64_t)* 1330 OBERON_UBC_ID_MAX, KM_SLEEP); 1331 1332 ubc_id = oberon_get_ubc_id(dip); 1333 1334 px_oberon_ubc_scratch_regs[ubc_id] = val; 1335 1336 /* 1337 * Check if any scratch registers are still in use. If all scratch 1338 * registers are currently set to zero, then deallocate the scratch 1339 * register array. 1340 */ 1341 for (ubc_id = 0; ubc_id < OBERON_UBC_ID_MAX; ubc_id++) { 1342 if (px_oberon_ubc_scratch_regs[ubc_id] != NULL) 1343 return; 1344 } 1345 1346 /* 1347 * All scratch registers are set to zero so deallocate the scratch 1348 * register array and set the pointer to NULL. 1349 */ 1350 kmem_free(px_oberon_ubc_scratch_regs, 1351 (sizeof (uint64_t)*OBERON_UBC_ID_MAX)); 1352 1353 px_oberon_ubc_scratch_regs = NULL; 1354 } 1355 1356 /* 1357 * Oberon does not have a UBC scratch register, so use an allocated array of 1358 * scratch registers and use the unique UBC ID as an index into that array. 1359 */ 1360 static uint64_t 1361 oberon_get_cb(dev_info_t *dip) 1362 { 1363 uint64_t ubc_id; 1364 1365 if (px_oberon_ubc_scratch_regs == NULL) 1366 return (0); 1367 1368 ubc_id = oberon_get_ubc_id(dip); 1369 1370 return (px_oberon_ubc_scratch_regs[ubc_id]); 1371 } 1372 1373 /* 1374 * Misc Functions: 1375 * Currently unsupported by hypervisor 1376 */ 1377 static uint64_t 1378 px_get_cb(dev_info_t *dip) 1379 { 1380 px_t *px_p = DIP_TO_STATE(dip); 1381 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1382 1383 /* 1384 * Oberon does not currently have Scratchpad registers. 1385 */ 1386 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 1387 return (oberon_get_cb(dip)); 1388 1389 return (CSR_XR((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1)); 1390 } 1391 1392 static void 1393 px_set_cb(dev_info_t *dip, uint64_t val) 1394 { 1395 px_t *px_p = DIP_TO_STATE(dip); 1396 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1397 1398 /* 1399 * Oberon does not currently have Scratchpad registers. 1400 */ 1401 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1402 oberon_set_cb(dip, val); 1403 return; 1404 } 1405 1406 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1, val); 1407 } 1408 1409 /*ARGSUSED*/ 1410 int 1411 px_lib_map_vconfig(dev_info_t *dip, 1412 ddi_map_req_t *mp, pci_config_offset_t off, 1413 pci_regspec_t *rp, caddr_t *addrp) 1414 { 1415 /* 1416 * No special config space access services in this layer. 1417 */ 1418 return (DDI_FAILURE); 1419 } 1420 1421 void 1422 px_lib_map_attr_check(ddi_map_req_t *mp) 1423 { 1424 ddi_acc_hdl_t *hp = mp->map_handlep; 1425 1426 /* fire does not accept byte masks from PIO store merge */ 1427 if (hp->ah_acc.devacc_attr_dataorder == DDI_STORECACHING_OK_ACC) 1428 hp->ah_acc.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1429 } 1430 1431 /* This function is called only by poke, caut put and pxtool poke. */ 1432 void 1433 px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr) 1434 { 1435 px_pec_t *pec_p = px_p->px_pec_p; 1436 dev_info_t *rpdip = px_p->px_dip; 1437 int rc_err, fab_err, i; 1438 int acctype = pec_p->pec_safeacc_type; 1439 ddi_fm_error_t derr; 1440 px_ranges_t *ranges_p; 1441 int range_len; 1442 uint32_t addr_high, addr_low; 1443 pcie_req_id_t bdf = 0; 1444 1445 /* Create the derr */ 1446 bzero(&derr, sizeof (ddi_fm_error_t)); 1447 derr.fme_version = DDI_FME_VERSION; 1448 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1449 derr.fme_flag = acctype; 1450 1451 if (acctype == DDI_FM_ERR_EXPECTED) { 1452 derr.fme_status = DDI_FM_NONFATAL; 1453 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, &derr); 1454 } 1455 1456 if (px_fm_enter(px_p) != DDI_SUCCESS) 1457 return; 1458 1459 /* send ereport/handle/clear fire registers */ 1460 rc_err = px_err_cmn_intr(px_p, &derr, PX_LIB_CALL, PX_FM_BLOCK_ALL); 1461 1462 /* Figure out if this is a cfg or mem32 access */ 1463 addr_high = (uint32_t)(addr >> 32); 1464 addr_low = (uint32_t)addr; 1465 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 1466 i = 0; 1467 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1468 if (ranges_p->parent_high == addr_high) { 1469 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1470 case PCI_ADDR_CONFIG: 1471 bdf = (pcie_req_id_t)(addr_low >> 12); 1472 addr_low = 0; 1473 break; 1474 case PCI_ADDR_MEM32: 1475 if (rdip) 1476 bdf = PCI_GET_BDF(rdip); 1477 else 1478 bdf = NULL; 1479 break; 1480 } 1481 break; 1482 } 1483 } 1484 1485 px_rp_en_q(px_p, bdf, addr_low, NULL); 1486 1487 /* 1488 * XXX - Current code scans the fabric for all px_tool accesses. 1489 * In future, do not scan fabric for px_tool access to IO Root Nexus 1490 */ 1491 fab_err = px_scan_fabric(px_p, rpdip, &derr); 1492 1493 px_err_panic(rc_err, PX_RC, fab_err, B_TRUE); 1494 px_fm_exit(px_p); 1495 px_err_panic(rc_err, PX_RC, fab_err, B_FALSE); 1496 } 1497 1498 #ifdef DEBUG 1499 int px_peekfault_cnt = 0; 1500 int px_pokefault_cnt = 0; 1501 #endif /* DEBUG */ 1502 1503 /*ARGSUSED*/ 1504 static int 1505 px_lib_do_poke(dev_info_t *dip, dev_info_t *rdip, 1506 peekpoke_ctlops_t *in_args) 1507 { 1508 px_t *px_p = DIP_TO_STATE(dip); 1509 px_pec_t *pec_p = px_p->px_pec_p; 1510 int err = DDI_SUCCESS; 1511 on_trap_data_t otd; 1512 1513 mutex_enter(&pec_p->pec_pokefault_mutex); 1514 pec_p->pec_ontrap_data = &otd; 1515 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1516 1517 /* Set up protected environment. */ 1518 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1519 uintptr_t tramp = otd.ot_trampoline; 1520 1521 otd.ot_trampoline = (uintptr_t)&poke_fault; 1522 err = do_poke(in_args->size, (void *)in_args->dev_addr, 1523 (void *)in_args->host_addr); 1524 otd.ot_trampoline = tramp; 1525 } else 1526 err = DDI_FAILURE; 1527 1528 px_lib_clr_errs(px_p, rdip, in_args->dev_addr); 1529 1530 if (otd.ot_trap & OT_DATA_ACCESS) 1531 err = DDI_FAILURE; 1532 1533 /* Take down protected environment. */ 1534 no_trap(); 1535 1536 pec_p->pec_ontrap_data = NULL; 1537 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1538 mutex_exit(&pec_p->pec_pokefault_mutex); 1539 1540 #ifdef DEBUG 1541 if (err == DDI_FAILURE) 1542 px_pokefault_cnt++; 1543 #endif 1544 return (err); 1545 } 1546 1547 /*ARGSUSED*/ 1548 static int 1549 px_lib_do_caut_put(dev_info_t *dip, dev_info_t *rdip, 1550 peekpoke_ctlops_t *cautacc_ctlops_arg) 1551 { 1552 size_t size = cautacc_ctlops_arg->size; 1553 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1554 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1555 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1556 size_t repcount = cautacc_ctlops_arg->repcount; 1557 uint_t flags = cautacc_ctlops_arg->flags; 1558 1559 px_t *px_p = DIP_TO_STATE(dip); 1560 px_pec_t *pec_p = px_p->px_pec_p; 1561 int err = DDI_SUCCESS; 1562 1563 /* 1564 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1565 * mutex. 1566 */ 1567 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1568 1569 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1570 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1571 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1572 1573 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1574 for (; repcount; repcount--) { 1575 switch (size) { 1576 1577 case sizeof (uint8_t): 1578 i_ddi_put8(hp, (uint8_t *)dev_addr, 1579 *(uint8_t *)host_addr); 1580 break; 1581 1582 case sizeof (uint16_t): 1583 i_ddi_put16(hp, (uint16_t *)dev_addr, 1584 *(uint16_t *)host_addr); 1585 break; 1586 1587 case sizeof (uint32_t): 1588 i_ddi_put32(hp, (uint32_t *)dev_addr, 1589 *(uint32_t *)host_addr); 1590 break; 1591 1592 case sizeof (uint64_t): 1593 i_ddi_put64(hp, (uint64_t *)dev_addr, 1594 *(uint64_t *)host_addr); 1595 break; 1596 } 1597 1598 host_addr += size; 1599 1600 if (flags == DDI_DEV_AUTOINCR) 1601 dev_addr += size; 1602 1603 px_lib_clr_errs(px_p, rdip, dev_addr); 1604 1605 if (pec_p->pec_ontrap_data->ot_trap & OT_DATA_ACCESS) { 1606 err = DDI_FAILURE; 1607 #ifdef DEBUG 1608 px_pokefault_cnt++; 1609 #endif 1610 break; 1611 } 1612 } 1613 } 1614 1615 i_ddi_notrap((ddi_acc_handle_t)hp); 1616 pec_p->pec_ontrap_data = NULL; 1617 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1618 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1619 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1620 1621 return (err); 1622 } 1623 1624 1625 int 1626 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1627 peekpoke_ctlops_t *in_args) 1628 { 1629 return (in_args->handle ? px_lib_do_caut_put(dip, rdip, in_args) : 1630 px_lib_do_poke(dip, rdip, in_args)); 1631 } 1632 1633 1634 /*ARGSUSED*/ 1635 static int 1636 px_lib_do_peek(dev_info_t *dip, peekpoke_ctlops_t *in_args) 1637 { 1638 px_t *px_p = DIP_TO_STATE(dip); 1639 px_pec_t *pec_p = px_p->px_pec_p; 1640 int err = DDI_SUCCESS; 1641 on_trap_data_t otd; 1642 1643 mutex_enter(&pec_p->pec_pokefault_mutex); 1644 if (px_fm_enter(px_p) != DDI_SUCCESS) 1645 return (DDI_FAILURE); 1646 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1647 px_fm_exit(px_p); 1648 1649 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1650 uintptr_t tramp = otd.ot_trampoline; 1651 1652 otd.ot_trampoline = (uintptr_t)&peek_fault; 1653 err = do_peek(in_args->size, (void *)in_args->dev_addr, 1654 (void *)in_args->host_addr); 1655 otd.ot_trampoline = tramp; 1656 } else 1657 err = DDI_FAILURE; 1658 1659 no_trap(); 1660 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1661 mutex_exit(&pec_p->pec_pokefault_mutex); 1662 1663 #ifdef DEBUG 1664 if (err == DDI_FAILURE) 1665 px_peekfault_cnt++; 1666 #endif 1667 return (err); 1668 } 1669 1670 1671 static int 1672 px_lib_do_caut_get(dev_info_t *dip, peekpoke_ctlops_t *cautacc_ctlops_arg) 1673 { 1674 size_t size = cautacc_ctlops_arg->size; 1675 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1676 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1677 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1678 size_t repcount = cautacc_ctlops_arg->repcount; 1679 uint_t flags = cautacc_ctlops_arg->flags; 1680 1681 px_t *px_p = DIP_TO_STATE(dip); 1682 px_pec_t *pec_p = px_p->px_pec_p; 1683 int err = DDI_SUCCESS; 1684 1685 /* 1686 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1687 * mutex. 1688 */ 1689 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1690 1691 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1692 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1693 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1694 1695 if (repcount == 1) { 1696 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1697 i_ddi_caut_get(size, (void *)dev_addr, 1698 (void *)host_addr); 1699 } else { 1700 int i; 1701 uint8_t *ff_addr = (uint8_t *)host_addr; 1702 for (i = 0; i < size; i++) 1703 *ff_addr++ = 0xff; 1704 1705 err = DDI_FAILURE; 1706 #ifdef DEBUG 1707 px_peekfault_cnt++; 1708 #endif 1709 } 1710 } else { 1711 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1712 for (; repcount; repcount--) { 1713 i_ddi_caut_get(size, (void *)dev_addr, 1714 (void *)host_addr); 1715 1716 host_addr += size; 1717 1718 if (flags == DDI_DEV_AUTOINCR) 1719 dev_addr += size; 1720 } 1721 } else { 1722 err = DDI_FAILURE; 1723 #ifdef DEBUG 1724 px_peekfault_cnt++; 1725 #endif 1726 } 1727 } 1728 1729 i_ddi_notrap((ddi_acc_handle_t)hp); 1730 pec_p->pec_ontrap_data = NULL; 1731 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1732 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1733 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1734 1735 return (err); 1736 } 1737 1738 /*ARGSUSED*/ 1739 int 1740 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1741 peekpoke_ctlops_t *in_args, void *result) 1742 { 1743 result = (void *)in_args->host_addr; 1744 return (in_args->handle ? px_lib_do_caut_get(dip, in_args) : 1745 px_lib_do_peek(dip, in_args)); 1746 } 1747 1748 /* 1749 * implements PPM interface 1750 */ 1751 int 1752 px_lib_pmctl(int cmd, px_t *px_p) 1753 { 1754 ASSERT((cmd & ~PPMREQ_MASK) == PPMREQ); 1755 switch (cmd) { 1756 case PPMREQ_PRE_PWR_OFF: 1757 /* 1758 * Currently there is no device power management for 1759 * the root complex (fire). When there is we need to make 1760 * sure that it is at full power before trying to send the 1761 * PME_Turn_Off message. 1762 */ 1763 DBG(DBG_PWR, px_p->px_dip, 1764 "ioctl: request to send PME_Turn_Off\n"); 1765 return (px_goto_l23ready(px_p)); 1766 1767 case PPMREQ_PRE_PWR_ON: 1768 DBG(DBG_PWR, px_p->px_dip, "ioctl: PRE_PWR_ON request\n"); 1769 return (px_pre_pwron_check(px_p)); 1770 1771 case PPMREQ_POST_PWR_ON: 1772 DBG(DBG_PWR, px_p->px_dip, "ioctl: POST_PWR_ON request\n"); 1773 return (px_goto_l0(px_p)); 1774 1775 default: 1776 return (DDI_FAILURE); 1777 } 1778 } 1779 1780 /* 1781 * sends PME_Turn_Off message to put the link in L2/L3 ready state. 1782 * called by px_ioctl. 1783 * returns DDI_SUCCESS or DDI_FAILURE 1784 * 1. Wait for link to be in L1 state (link status reg) 1785 * 2. write to PME_Turn_off reg to boradcast 1786 * 3. set timeout 1787 * 4. If timeout, return failure. 1788 * 5. If PM_TO_Ack, wait till link is in L2/L3 ready 1789 */ 1790 static int 1791 px_goto_l23ready(px_t *px_p) 1792 { 1793 pcie_pwr_t *pwr_p; 1794 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1795 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1796 int ret = DDI_SUCCESS; 1797 clock_t end, timeleft; 1798 int mutex_held = 1; 1799 1800 /* If no PM info, return failure */ 1801 if (!PCIE_PMINFO(px_p->px_dip) || 1802 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1803 return (DDI_FAILURE); 1804 1805 mutex_enter(&pwr_p->pwr_lock); 1806 mutex_enter(&px_p->px_l23ready_lock); 1807 /* Clear the PME_To_ACK receieved flag */ 1808 px_p->px_pm_flags &= ~PX_PMETOACK_RECVD; 1809 /* 1810 * When P25 is the downstream device, after receiving 1811 * PME_To_ACK, fire will go to Detect state, which causes 1812 * the link down event. Inform FMA that this is expected. 1813 * In case of all other cards complaint with the pci express 1814 * spec, this will happen when the power is re-applied. FMA 1815 * code will clear this flag after one instance of LDN. Since 1816 * there will not be a LDN event for the spec compliant cards, 1817 * we need to clear the flag after receiving PME_To_ACK. 1818 */ 1819 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1820 if (px_send_pme_turnoff(csr_base) != DDI_SUCCESS) { 1821 ret = DDI_FAILURE; 1822 goto l23ready_done; 1823 } 1824 px_p->px_pm_flags |= PX_PME_TURNOFF_PENDING; 1825 1826 end = ddi_get_lbolt() + drv_usectohz(px_pme_to_ack_timeout); 1827 while (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1828 timeleft = cv_timedwait(&px_p->px_l23ready_cv, 1829 &px_p->px_l23ready_lock, end); 1830 /* 1831 * if cv_timedwait returns -1, it is either 1832 * 1) timed out or 1833 * 2) there was a pre-mature wakeup but by the time 1834 * cv_timedwait is called again end < lbolt i.e. 1835 * end is in the past. 1836 * 3) By the time we make first cv_timedwait call, 1837 * end < lbolt is true. 1838 */ 1839 if (timeleft == -1) 1840 break; 1841 } 1842 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1843 /* 1844 * Either timedout or interrupt didn't get a 1845 * chance to grab the mutex and set the flag. 1846 * release the mutex and delay for sometime. 1847 * This will 1) give a chance for interrupt to 1848 * set the flag 2) creates a delay between two 1849 * consequetive requests. 1850 */ 1851 mutex_exit(&px_p->px_l23ready_lock); 1852 delay(drv_usectohz(50 * PX_MSEC_TO_USEC)); 1853 mutex_held = 0; 1854 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1855 ret = DDI_FAILURE; 1856 DBG(DBG_PWR, px_p->px_dip, " Timed out while waiting" 1857 " for PME_TO_ACK\n"); 1858 } 1859 } 1860 px_p->px_pm_flags &= 1861 ~(PX_PME_TURNOFF_PENDING | PX_PMETOACK_RECVD | PX_LDN_EXPECTED); 1862 1863 l23ready_done: 1864 if (mutex_held) 1865 mutex_exit(&px_p->px_l23ready_lock); 1866 /* 1867 * Wait till link is in L1 idle, if sending PME_Turn_Off 1868 * was succesful. 1869 */ 1870 if (ret == DDI_SUCCESS) { 1871 if (px_link_wait4l1idle(csr_base) != DDI_SUCCESS) { 1872 DBG(DBG_PWR, px_p->px_dip, " Link is not at L1" 1873 " even though we received PME_To_ACK.\n"); 1874 /* 1875 * Workaround for hardware bug with P25. 1876 * Due to a hardware bug with P25, link state 1877 * will be Detect state rather than L1 after 1878 * link is transitioned to L23Ready state. Since 1879 * we don't know whether link is L23ready state 1880 * without Fire's state being L1_idle, we delay 1881 * here just to make sure that we wait till link 1882 * is transitioned to L23Ready state. 1883 */ 1884 delay(drv_usectohz(100 * PX_MSEC_TO_USEC)); 1885 } 1886 pwr_p->pwr_link_lvl = PM_LEVEL_L3; 1887 1888 } 1889 mutex_exit(&pwr_p->pwr_lock); 1890 return (ret); 1891 } 1892 1893 /* 1894 * Message interrupt handler intended to be shared for both 1895 * PME and PME_TO_ACK msg handling, currently only handles 1896 * PME_To_ACK message. 1897 */ 1898 uint_t 1899 px_pmeq_intr(caddr_t arg) 1900 { 1901 px_t *px_p = (px_t *)arg; 1902 1903 DBG(DBG_PWR, px_p->px_dip, " PME_To_ACK received \n"); 1904 mutex_enter(&px_p->px_l23ready_lock); 1905 cv_broadcast(&px_p->px_l23ready_cv); 1906 if (px_p->px_pm_flags & PX_PME_TURNOFF_PENDING) { 1907 px_p->px_pm_flags |= PX_PMETOACK_RECVD; 1908 } else { 1909 /* 1910 * This maybe the second ack received. If so then, 1911 * we should be receiving it during wait4L1 stage. 1912 */ 1913 px_p->px_pmetoack_ignored++; 1914 } 1915 mutex_exit(&px_p->px_l23ready_lock); 1916 return (DDI_INTR_CLAIMED); 1917 } 1918 1919 static int 1920 px_pre_pwron_check(px_t *px_p) 1921 { 1922 pcie_pwr_t *pwr_p; 1923 1924 /* If no PM info, return failure */ 1925 if (!PCIE_PMINFO(px_p->px_dip) || 1926 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1927 return (DDI_FAILURE); 1928 1929 /* 1930 * For the spec compliant downstream cards link down 1931 * is expected when the device is powered on. 1932 */ 1933 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1934 return (pwr_p->pwr_link_lvl == PM_LEVEL_L3 ? DDI_SUCCESS : DDI_FAILURE); 1935 } 1936 1937 static int 1938 px_goto_l0(px_t *px_p) 1939 { 1940 pcie_pwr_t *pwr_p; 1941 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1942 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1943 int ret = DDI_SUCCESS; 1944 uint64_t time_spent = 0; 1945 1946 /* If no PM info, return failure */ 1947 if (!PCIE_PMINFO(px_p->px_dip) || 1948 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1949 return (DDI_FAILURE); 1950 1951 mutex_enter(&pwr_p->pwr_lock); 1952 /* 1953 * The following link retrain activity will cause LDN and LUP event. 1954 * Receiving LDN prior to receiving LUP is expected, not an error in 1955 * this case. Receiving LUP indicates link is fully up to support 1956 * powering up down stream device, and of course any further LDN and 1957 * LUP outside this context will be error. 1958 */ 1959 px_p->px_lup_pending = 1; 1960 if (px_link_retrain(csr_base) != DDI_SUCCESS) { 1961 ret = DDI_FAILURE; 1962 goto l0_done; 1963 } 1964 1965 /* LUP event takes the order of 15ms amount of time to occur */ 1966 for (; px_p->px_lup_pending && (time_spent < px_lup_poll_to); 1967 time_spent += px_lup_poll_interval) 1968 drv_usecwait(px_lup_poll_interval); 1969 if (px_p->px_lup_pending) 1970 ret = DDI_FAILURE; 1971 l0_done: 1972 px_enable_detect_quiet(csr_base); 1973 if (ret == DDI_SUCCESS) 1974 pwr_p->pwr_link_lvl = PM_LEVEL_L0; 1975 mutex_exit(&pwr_p->pwr_lock); 1976 return (ret); 1977 } 1978 1979 /* 1980 * Extract the drivers binding name to identify which chip we're binding to. 1981 * Whenever a new bus bridge is created, the driver alias entry should be 1982 * added here to identify the device if needed. If a device isn't added, 1983 * the identity defaults to PX_CHIP_UNIDENTIFIED. 1984 */ 1985 static uint32_t 1986 px_identity_init(px_t *px_p) 1987 { 1988 dev_info_t *dip = px_p->px_dip; 1989 char *name = ddi_binding_name(dip); 1990 uint32_t revision = 0; 1991 1992 revision = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1993 "module-revision#", 0); 1994 1995 /* Check for Fire driver binding name */ 1996 if (strcmp(name, "pciex108e,80f0") == 0) { 1997 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 1998 "(FIRE), module-revision %d\n", NAMEINST(dip), 1999 revision); 2000 2001 return ((revision >= FIRE_MOD_REV_20) ? 2002 PX_CHIP_FIRE : PX_CHIP_UNIDENTIFIED); 2003 } 2004 2005 /* Check for Oberon driver binding name */ 2006 if (strcmp(name, "pciex108e,80f8") == 0) { 2007 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 2008 "(OBERON), module-revision %d\n", NAMEINST(dip), 2009 revision); 2010 2011 return (PX_CHIP_OBERON); 2012 } 2013 2014 DBG(DBG_ATTACH, dip, "%s%d: Unknown PCI Express Host bridge %s %x\n", 2015 ddi_driver_name(dip), ddi_get_instance(dip), name, revision); 2016 2017 return (PX_CHIP_UNIDENTIFIED); 2018 } 2019 2020 int 2021 px_err_add_intr(px_fault_t *px_fault_p) 2022 { 2023 dev_info_t *dip = px_fault_p->px_fh_dip; 2024 px_t *px_p = DIP_TO_STATE(dip); 2025 2026 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 2027 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, 2028 NULL, NULL) == 0); 2029 2030 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 2031 2032 return (DDI_SUCCESS); 2033 } 2034 2035 void 2036 px_err_rem_intr(px_fault_t *px_fault_p) 2037 { 2038 dev_info_t *dip = px_fault_p->px_fh_dip; 2039 px_t *px_p = DIP_TO_STATE(dip); 2040 2041 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 2042 IB_INTR_WAIT); 2043 2044 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 2045 } 2046 2047 /* 2048 * px_cb_intr_redist() - sun4u only, CB interrupt redistribution 2049 */ 2050 void 2051 px_cb_intr_redist(void *arg) 2052 { 2053 px_cb_t *cb_p = (px_cb_t *)arg; 2054 px_cb_list_t *pxl; 2055 px_t *pxp = NULL; 2056 px_fault_t *f_p = NULL; 2057 uint32_t new_cpuid; 2058 intr_valid_state_t enabled = 0; 2059 2060 mutex_enter(&cb_p->cb_mutex); 2061 2062 pxl = cb_p->pxl; 2063 if (!pxl) 2064 goto cb_done; 2065 2066 pxp = pxl->pxp; 2067 f_p = &pxp->px_cb_fault; 2068 for (; pxl && (f_p->px_fh_sysino != cb_p->sysino); ) { 2069 pxl = pxl->next; 2070 pxp = pxl->pxp; 2071 f_p = &pxp->px_cb_fault; 2072 } 2073 if (pxl == NULL) 2074 goto cb_done; 2075 2076 new_cpuid = intr_dist_cpuid(); 2077 if (new_cpuid == cb_p->cpuid) 2078 goto cb_done; 2079 2080 if ((px_lib_intr_getvalid(pxp->px_dip, f_p->px_fh_sysino, &enabled) 2081 != DDI_SUCCESS) || !enabled) { 2082 DBG(DBG_IB, pxp->px_dip, "px_cb_intr_redist: CB not enabled, " 2083 "sysino(0x%x)\n", f_p->px_fh_sysino); 2084 goto cb_done; 2085 } 2086 2087 PX_INTR_DISABLE(pxp->px_dip, f_p->px_fh_sysino); 2088 2089 cb_p->cpuid = new_cpuid; 2090 cb_p->sysino = f_p->px_fh_sysino; 2091 PX_INTR_ENABLE(pxp->px_dip, cb_p->sysino, cb_p->cpuid); 2092 2093 cb_done: 2094 mutex_exit(&cb_p->cb_mutex); 2095 } 2096 2097 /* 2098 * px_cb_add_intr() - Called from attach(9E) to create CB if not yet 2099 * created, to add CB interrupt vector always, but enable only once. 2100 */ 2101 int 2102 px_cb_add_intr(px_fault_t *fault_p) 2103 { 2104 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip); 2105 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2106 px_cb_t *cb_p = (px_cb_t *)px_get_cb(fault_p->px_fh_dip); 2107 px_cb_list_t *pxl, *pxl_new; 2108 boolean_t is_proxy = B_FALSE; 2109 2110 /* create cb */ 2111 if (cb_p == NULL) { 2112 cb_p = kmem_zalloc(sizeof (px_cb_t), KM_SLEEP); 2113 2114 mutex_init(&cb_p->cb_mutex, NULL, MUTEX_DRIVER, 2115 (void *) ipltospl(FM_ERR_PIL)); 2116 2117 cb_p->px_cb_func = px_cb_intr; 2118 pxu_p->px_cb_p = cb_p; 2119 px_set_cb(fault_p->px_fh_dip, (uint64_t)cb_p); 2120 2121 /* px_lib_dev_init allows only FIRE and OBERON */ 2122 px_err_reg_enable( 2123 (pxu_p->chip_type == PX_CHIP_FIRE) ? 2124 PX_ERR_JBC : PX_ERR_UBC, 2125 pxu_p->px_address[PX_REG_XBC]); 2126 } else 2127 pxu_p->px_cb_p = cb_p; 2128 2129 /* register cb interrupt */ 2130 VERIFY(add_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL, 2131 (intrfunc)cb_p->px_cb_func, (caddr_t)cb_p, NULL, NULL) == 0); 2132 2133 2134 /* update cb list */ 2135 mutex_enter(&cb_p->cb_mutex); 2136 if (cb_p->pxl == NULL) { 2137 is_proxy = B_TRUE; 2138 pxl = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2139 pxl->pxp = px_p; 2140 cb_p->pxl = pxl; 2141 cb_p->sysino = fault_p->px_fh_sysino; 2142 cb_p->cpuid = intr_dist_cpuid(); 2143 } else { 2144 /* 2145 * Find the last pxl or 2146 * stop short at encountering a redundent entry, or 2147 * both. 2148 */ 2149 pxl = cb_p->pxl; 2150 for (; !(pxl->pxp == px_p) && pxl->next; pxl = pxl->next) {}; 2151 ASSERT(pxl->pxp != px_p); 2152 2153 /* add to linked list */ 2154 pxl_new = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2155 pxl_new->pxp = px_p; 2156 pxl->next = pxl_new; 2157 } 2158 cb_p->attachcnt++; 2159 mutex_exit(&cb_p->cb_mutex); 2160 2161 if (is_proxy) { 2162 /* add to interrupt redistribution list */ 2163 intr_dist_add(px_cb_intr_redist, cb_p); 2164 2165 /* enable cb hw interrupt */ 2166 px_ib_intr_enable(px_p, cb_p->cpuid, fault_p->px_intr_ino); 2167 } 2168 2169 return (DDI_SUCCESS); 2170 } 2171 2172 /* 2173 * px_cb_rem_intr() - Called from detach(9E) to remove its CB 2174 * interrupt vector, to shift proxy to the next available px, 2175 * or disable CB interrupt when itself is the last. 2176 */ 2177 void 2178 px_cb_rem_intr(px_fault_t *fault_p) 2179 { 2180 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip), *pxp; 2181 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2182 px_cb_t *cb_p = PX2CB(px_p); 2183 px_cb_list_t *pxl, *prev; 2184 px_fault_t *f_p; 2185 2186 ASSERT(cb_p->pxl); 2187 2188 /* find and remove this px, and update cb list */ 2189 mutex_enter(&cb_p->cb_mutex); 2190 2191 pxl = cb_p->pxl; 2192 if (pxl->pxp == px_p) { 2193 cb_p->pxl = pxl->next; 2194 } else { 2195 prev = pxl; 2196 pxl = pxl->next; 2197 for (; pxl && (pxl->pxp != px_p); prev = pxl, pxl = pxl->next) { 2198 }; 2199 if (!pxl) { 2200 cmn_err(CE_WARN, "px_cb_rem_intr: can't find px_p 0x%p " 2201 "in registered CB list.", (void *)px_p); 2202 mutex_exit(&cb_p->cb_mutex); 2203 return; 2204 } 2205 prev->next = pxl->next; 2206 } 2207 pxu_p->px_cb_p = NULL; 2208 cb_p->attachcnt--; 2209 kmem_free(pxl, sizeof (px_cb_list_t)); 2210 mutex_exit(&cb_p->cb_mutex); 2211 2212 /* disable cb hw interrupt */ 2213 if (fault_p->px_fh_sysino == cb_p->sysino) 2214 px_ib_intr_disable(px_p->px_ib_p, fault_p->px_intr_ino, 2215 IB_INTR_WAIT); 2216 2217 /* if last px, remove from interrupt redistribution list */ 2218 if (cb_p->pxl == NULL) 2219 intr_dist_rem(px_cb_intr_redist, cb_p); 2220 2221 /* de-register interrupt */ 2222 VERIFY(rem_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 2223 2224 /* if not last px, assign next px to manage cb */ 2225 mutex_enter(&cb_p->cb_mutex); 2226 if (cb_p->pxl) { 2227 if (fault_p->px_fh_sysino == cb_p->sysino) { 2228 pxp = cb_p->pxl->pxp; 2229 f_p = &pxp->px_cb_fault; 2230 cb_p->sysino = f_p->px_fh_sysino; 2231 2232 PX_INTR_ENABLE(pxp->px_dip, cb_p->sysino, cb_p->cpuid); 2233 (void) px_lib_intr_setstate(pxp->px_dip, cb_p->sysino, 2234 INTR_IDLE_STATE); 2235 } 2236 mutex_exit(&cb_p->cb_mutex); 2237 return; 2238 } 2239 2240 /* clean up after the last px */ 2241 mutex_exit(&cb_p->cb_mutex); 2242 2243 /* px_lib_dev_init allows only FIRE and OBERON */ 2244 px_err_reg_disable( 2245 (pxu_p->chip_type == PX_CHIP_FIRE) ? PX_ERR_JBC : PX_ERR_UBC, 2246 pxu_p->px_address[PX_REG_XBC]); 2247 2248 mutex_destroy(&cb_p->cb_mutex); 2249 px_set_cb(fault_p->px_fh_dip, 0ull); 2250 kmem_free(cb_p, sizeof (px_cb_t)); 2251 } 2252 2253 /* 2254 * px_cb_intr() - sun4u only, CB interrupt dispatcher 2255 */ 2256 uint_t 2257 px_cb_intr(caddr_t arg) 2258 { 2259 px_cb_t *cb_p = (px_cb_t *)arg; 2260 px_t *pxp; 2261 px_fault_t *f_p; 2262 int ret; 2263 2264 mutex_enter(&cb_p->cb_mutex); 2265 2266 if (!cb_p->pxl) { 2267 mutex_exit(&cb_p->cb_mutex); 2268 return (DDI_INTR_UNCLAIMED); 2269 } 2270 2271 pxp = cb_p->pxl->pxp; 2272 f_p = &pxp->px_cb_fault; 2273 2274 ret = f_p->px_err_func((caddr_t)f_p); 2275 2276 mutex_exit(&cb_p->cb_mutex); 2277 return (ret); 2278 } 2279 2280 #ifdef FMA 2281 void 2282 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 2283 { 2284 /* populate the rc_status by reading the registers - TBD */ 2285 } 2286 #endif /* FMA */ 2287 2288 /* 2289 * Unprotected raw reads/writes of fabric device's config space. 2290 * Only used for temporary PCI-E Fabric Error Handling. 2291 */ 2292 uint32_t 2293 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) 2294 { 2295 px_ranges_t *rp = px_p->px_ranges_p; 2296 uint64_t range_prop, base_addr; 2297 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2298 uint32_t val; 2299 2300 /* Get Fire's Physical Base Address */ 2301 range_prop = px_get_range_prop(px_p, rp, bank); 2302 2303 /* Get config space first. */ 2304 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2305 2306 val = ldphysio(base_addr); 2307 2308 return (LE_32(val)); 2309 } 2310 2311 void 2312 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 2313 uint32_t val) { 2314 px_ranges_t *rp = px_p->px_ranges_p; 2315 uint64_t range_prop, base_addr; 2316 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2317 2318 /* Get Fire's Physical Base Address */ 2319 range_prop = px_get_range_prop(px_p, rp, bank); 2320 2321 /* Get config space first. */ 2322 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2323 2324 stphysio(base_addr, LE_32(val)); 2325 } 2326 2327 /* 2328 * cpr callback 2329 * 2330 * disable fabric error msg interrupt prior to suspending 2331 * all device drivers; re-enable fabric error msg interrupt 2332 * after all devices are resumed. 2333 */ 2334 static boolean_t 2335 px_cpr_callb(void *arg, int code) 2336 { 2337 px_t *px_p = (px_t *)arg; 2338 px_ib_t *ib_p = px_p->px_ib_p; 2339 px_pec_t *pec_p = px_p->px_pec_p; 2340 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2341 caddr_t csr_base; 2342 devino_t ce_ino, nf_ino, f_ino; 2343 px_ino_t *ce_ino_p, *nf_ino_p, *f_ino_p; 2344 uint64_t imu_log_enable, imu_intr_enable; 2345 uint64_t imu_log_mask, imu_intr_mask; 2346 2347 ce_ino = px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id); 2348 nf_ino = px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id); 2349 f_ino = px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id); 2350 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2351 2352 imu_log_enable = CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE); 2353 imu_intr_enable = CSR_XR(csr_base, IMU_INTERRUPT_ENABLE); 2354 2355 imu_log_mask = BITMASK(IMU_ERROR_LOG_ENABLE_FATAL_MES_NOT_EN_LOG_EN) | 2356 BITMASK(IMU_ERROR_LOG_ENABLE_NONFATAL_MES_NOT_EN_LOG_EN) | 2357 BITMASK(IMU_ERROR_LOG_ENABLE_COR_MES_NOT_EN_LOG_EN); 2358 2359 imu_intr_mask = 2360 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_S_INT_EN) | 2361 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_S_INT_EN) | 2362 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_S_INT_EN) | 2363 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_P_INT_EN) | 2364 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_P_INT_EN) | 2365 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_P_INT_EN); 2366 2367 switch (code) { 2368 case CB_CODE_CPR_CHKPT: 2369 /* disable imu rbne on corr/nonfatal/fatal errors */ 2370 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, 2371 imu_log_enable & (~imu_log_mask)); 2372 2373 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, 2374 imu_intr_enable & (~imu_intr_mask)); 2375 2376 /* disable CORR intr mapping */ 2377 px_ib_intr_disable(ib_p, ce_ino, IB_INTR_NOWAIT); 2378 2379 /* disable NON FATAL intr mapping */ 2380 px_ib_intr_disable(ib_p, nf_ino, IB_INTR_NOWAIT); 2381 2382 /* disable FATAL intr mapping */ 2383 px_ib_intr_disable(ib_p, f_ino, IB_INTR_NOWAIT); 2384 2385 break; 2386 2387 case CB_CODE_CPR_RESUME: 2388 pxu_p->cpr_flag = PX_NOT_CPR; 2389 mutex_enter(&ib_p->ib_ino_lst_mutex); 2390 2391 ce_ino_p = px_ib_locate_ino(ib_p, ce_ino); 2392 nf_ino_p = px_ib_locate_ino(ib_p, nf_ino); 2393 f_ino_p = px_ib_locate_ino(ib_p, f_ino); 2394 2395 /* enable CORR intr mapping */ 2396 if (ce_ino_p) 2397 px_ib_intr_enable(px_p, ce_ino_p->ino_cpuid, ce_ino); 2398 else 2399 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2400 "reenable PCIe Correctable msg intr.\n"); 2401 2402 /* enable NON FATAL intr mapping */ 2403 if (nf_ino_p) 2404 px_ib_intr_enable(px_p, nf_ino_p->ino_cpuid, nf_ino); 2405 else 2406 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2407 "reenable PCIe Non Fatal msg intr.\n"); 2408 2409 /* enable FATAL intr mapping */ 2410 if (f_ino_p) 2411 px_ib_intr_enable(px_p, f_ino_p->ino_cpuid, f_ino); 2412 else 2413 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2414 "reenable PCIe Fatal msg intr.\n"); 2415 2416 mutex_exit(&ib_p->ib_ino_lst_mutex); 2417 2418 /* enable corr/nonfatal/fatal not enable error */ 2419 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, (imu_log_enable | 2420 (imu_log_mask & px_imu_log_mask))); 2421 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, (imu_intr_enable | 2422 (imu_intr_mask & px_imu_intr_mask))); 2423 2424 break; 2425 } 2426 2427 return (B_TRUE); 2428 } 2429 2430 uint64_t 2431 px_get_rng_parent_hi_mask(px_t *px_p) 2432 { 2433 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2434 uint64_t mask; 2435 2436 switch (PX_CHIP_TYPE(pxu_p)) { 2437 case PX_CHIP_OBERON: 2438 mask = OBERON_RANGE_PROP_MASK; 2439 break; 2440 case PX_CHIP_FIRE: 2441 mask = PX_RANGE_PROP_MASK; 2442 break; 2443 default: 2444 mask = PX_RANGE_PROP_MASK; 2445 } 2446 2447 return (mask); 2448 } 2449 2450 /* 2451 * fetch chip's range propery's value 2452 */ 2453 uint64_t 2454 px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank) 2455 { 2456 uint64_t mask, range_prop; 2457 2458 mask = px_get_rng_parent_hi_mask(px_p); 2459 range_prop = (((uint64_t)(rp[bank].parent_high & mask)) << 32) | 2460 rp[bank].parent_low; 2461 2462 return (range_prop); 2463 } 2464 2465 /* 2466 * add cpr callback 2467 */ 2468 void 2469 px_cpr_add_callb(px_t *px_p) 2470 { 2471 px_p->px_cprcb_id = callb_add(px_cpr_callb, (void *)px_p, 2472 CB_CL_CPR_POST_USER, "px_cpr"); 2473 } 2474 2475 /* 2476 * remove cpr callback 2477 */ 2478 void 2479 px_cpr_rem_callb(px_t *px_p) 2480 { 2481 (void) callb_delete(px_p->px_cprcb_id); 2482 } 2483 2484 /*ARGSUSED*/ 2485 static uint_t 2486 px_hp_intr(caddr_t arg1, caddr_t arg2) 2487 { 2488 px_t *px_p = (px_t *)arg1; 2489 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2490 int rval; 2491 2492 rval = pciehpc_intr(px_p->px_dip); 2493 2494 #ifdef DEBUG 2495 if (rval == DDI_INTR_UNCLAIMED) 2496 cmn_err(CE_WARN, "%s%d: UNCLAIMED intr\n", 2497 ddi_driver_name(px_p->px_dip), 2498 ddi_get_instance(px_p->px_dip)); 2499 #endif 2500 2501 /* Set the interrupt state to idle */ 2502 if (px_lib_intr_setstate(px_p->px_dip, 2503 pxu_p->hp_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 2504 return (DDI_INTR_UNCLAIMED); 2505 2506 return (rval); 2507 } 2508 2509 int 2510 px_lib_hotplug_init(dev_info_t *dip, void *arg) 2511 { 2512 px_t *px_p = DIP_TO_STATE(dip); 2513 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2514 uint64_t ret; 2515 2516 if ((ret = hvio_hotplug_init(dip, arg)) == DDI_SUCCESS) { 2517 if (px_lib_intr_devino_to_sysino(px_p->px_dip, 2518 px_p->px_inos[PX_INTR_HOTPLUG], &pxu_p->hp_sysino) != 2519 DDI_SUCCESS) { 2520 #ifdef DEBUG 2521 cmn_err(CE_WARN, "%s%d: devino_to_sysino fails\n", 2522 ddi_driver_name(px_p->px_dip), 2523 ddi_get_instance(px_p->px_dip)); 2524 #endif 2525 return (DDI_FAILURE); 2526 } 2527 2528 VERIFY(add_ivintr(pxu_p->hp_sysino, PX_PCIEHP_PIL, 2529 (intrfunc)px_hp_intr, (caddr_t)px_p, NULL, NULL) == 0); 2530 2531 px_ib_intr_enable(px_p, intr_dist_cpuid(), 2532 px_p->px_inos[PX_INTR_HOTPLUG]); 2533 } 2534 2535 return (ret); 2536 } 2537 2538 void 2539 px_lib_hotplug_uninit(dev_info_t *dip) 2540 { 2541 if (hvio_hotplug_uninit(dip) == DDI_SUCCESS) { 2542 px_t *px_p = DIP_TO_STATE(dip); 2543 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2544 2545 px_ib_intr_disable(px_p->px_ib_p, 2546 px_p->px_inos[PX_INTR_HOTPLUG], IB_INTR_WAIT); 2547 2548 VERIFY(rem_ivintr(pxu_p->hp_sysino, PX_PCIEHP_PIL) == 0); 2549 } 2550 } 2551 2552 /* 2553 * px_hp_intr_redist() - sun4u only, HP interrupt redistribution 2554 */ 2555 void 2556 px_hp_intr_redist(px_t *px_p) 2557 { 2558 if (px_p && (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)) { 2559 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 2560 px_p->px_inos[PX_INTR_HOTPLUG], B_FALSE); 2561 } 2562 } 2563 2564 boolean_t 2565 px_lib_is_in_drain_state(px_t *px_p) 2566 { 2567 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2568 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2569 uint64_t drain_status; 2570 2571 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 2572 drain_status = CSR_BR(csr_base, DRAIN_CONTROL_STATUS, DRAIN); 2573 } else { 2574 drain_status = CSR_BR(csr_base, TLU_STATUS, DRAIN); 2575 } 2576 2577 return (drain_status); 2578 } 2579 2580 pcie_req_id_t 2581 px_lib_get_bdf(px_t *px_p) 2582 { 2583 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2584 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2585 pcie_req_id_t bdf; 2586 2587 bdf = CSR_BR(csr_base, DMC_PCI_EXPRESS_CONFIGURATION, REQ_ID); 2588 2589 return (bdf); 2590 } 2591