1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * sun4u Fire Error Handling 30 */ 31 32 #include <sys/types.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/fm/protocol.h> 36 #include <sys/fm/util.h> 37 #include <sys/pcie.h> 38 #include <sys/pcie_impl.h> 39 #include "px_obj.h" 40 #include <px_regs.h> 41 #include <px_csr.h> 42 #include <sys/membar.h> 43 #include <sys/machcpuvar.h> 44 #include <sys/platform_module.h> 45 #include "pcie_pwr.h" 46 #include "px_lib4u.h" 47 #include "px_err.h" 48 #include "px_err_impl.h" 49 #include "oberon_regs.h" 50 51 uint64_t px_tlu_ue_intr_mask = PX_ERR_EN_ALL; 52 uint64_t px_tlu_ue_log_mask = PX_ERR_EN_ALL; 53 uint64_t px_tlu_ue_count_mask = PX_ERR_EN_ALL; 54 55 uint64_t px_tlu_ce_intr_mask = PX_ERR_MASK_NONE; 56 uint64_t px_tlu_ce_log_mask = PX_ERR_MASK_NONE; 57 uint64_t px_tlu_ce_count_mask = PX_ERR_MASK_NONE; 58 59 /* 60 * Do not enable Link Interrupts 61 */ 62 uint64_t px_tlu_oe_intr_mask = PX_ERR_EN_ALL & ~0x80000000800; 63 uint64_t px_tlu_oe_log_mask = PX_ERR_EN_ALL & ~0x80000000800; 64 uint64_t px_tlu_oe_count_mask = PX_ERR_EN_ALL; 65 66 uint64_t px_mmu_intr_mask = PX_ERR_EN_ALL; 67 uint64_t px_mmu_log_mask = PX_ERR_EN_ALL; 68 uint64_t px_mmu_count_mask = PX_ERR_EN_ALL; 69 70 uint64_t px_imu_intr_mask = PX_ERR_EN_ALL; 71 uint64_t px_imu_log_mask = PX_ERR_EN_ALL; 72 uint64_t px_imu_count_mask = PX_ERR_EN_ALL; 73 74 /* 75 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) | 76 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P); 77 */ 78 uint64_t px_ilu_intr_mask = (((uint64_t)0x10 << 32) | 0x10); 79 uint64_t px_ilu_log_mask = (((uint64_t)0x10 << 32) | 0x10); 80 uint64_t px_ilu_count_mask = PX_ERR_EN_ALL; 81 82 uint64_t px_ubc_intr_mask = PX_ERR_EN_ALL; 83 uint64_t px_ubc_log_mask = PX_ERR_EN_ALL; 84 uint64_t px_ubc_count_mask = PX_ERR_EN_ALL; 85 86 uint64_t px_jbc_intr_mask = PX_ERR_EN_ALL; 87 uint64_t px_jbc_log_mask = PX_ERR_EN_ALL; 88 uint64_t px_jbc_count_mask = PX_ERR_EN_ALL; 89 90 /* 91 * LPU Intr Registers are reverse encoding from the registers above. 92 * 1 = disable 93 * 0 = enable 94 * 95 * Log and Count are however still the same. 96 */ 97 uint64_t px_lpul_intr_mask = LPU_INTR_DISABLE; 98 uint64_t px_lpul_log_mask = PX_ERR_EN_ALL; 99 uint64_t px_lpul_count_mask = PX_ERR_EN_ALL; 100 101 uint64_t px_lpup_intr_mask = LPU_INTR_DISABLE; 102 uint64_t px_lpup_log_mask = PX_ERR_EN_ALL; 103 uint64_t px_lpup_count_mask = PX_ERR_EN_ALL; 104 105 uint64_t px_lpur_intr_mask = LPU_INTR_DISABLE; 106 uint64_t px_lpur_log_mask = PX_ERR_EN_ALL; 107 uint64_t px_lpur_count_mask = PX_ERR_EN_ALL; 108 109 uint64_t px_lpux_intr_mask = LPU_INTR_DISABLE; 110 uint64_t px_lpux_log_mask = PX_ERR_EN_ALL; 111 uint64_t px_lpux_count_mask = PX_ERR_EN_ALL; 112 113 uint64_t px_lpus_intr_mask = LPU_INTR_DISABLE; 114 uint64_t px_lpus_log_mask = PX_ERR_EN_ALL; 115 uint64_t px_lpus_count_mask = PX_ERR_EN_ALL; 116 117 uint64_t px_lpug_intr_mask = LPU_INTR_DISABLE; 118 uint64_t px_lpug_log_mask = PX_ERR_EN_ALL; 119 uint64_t px_lpug_count_mask = PX_ERR_EN_ALL; 120 121 /* 122 * JBC error bit table 123 */ 124 #define JBC_BIT_DESC(bit, hdl, erpt) \ 125 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 126 0, \ 127 PX_ERR_BIT_HANDLE(hdl), \ 128 PX_ERPT_SEND(erpt), \ 129 PX_ERR_JBC_CLASS(bit) }, \ 130 { JBC_INTERRUPT_STATUS_ ## bit ## _S, \ 131 0, \ 132 PX_ERR_BIT_HANDLE(hdl), \ 133 PX_ERPT_SEND(erpt), \ 134 PX_ERR_JBC_CLASS(bit) 135 px_err_bit_desc_t px_err_jbc_tbl[] = { 136 /* JBC FATAL */ 137 { JBC_BIT_DESC(MB_PEA, hw_reset, jbc_fatal) }, 138 { JBC_BIT_DESC(CPE, hw_reset, jbc_fatal) }, 139 { JBC_BIT_DESC(APE, hw_reset, jbc_fatal) }, 140 { JBC_BIT_DESC(PIO_CPE, hw_reset, jbc_fatal) }, 141 { JBC_BIT_DESC(JTCEEW, hw_reset, jbc_fatal) }, 142 { JBC_BIT_DESC(JTCEEI, hw_reset, jbc_fatal) }, 143 { JBC_BIT_DESC(JTCEER, hw_reset, jbc_fatal) }, 144 145 /* JBC MERGE */ 146 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 147 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 148 149 /* JBC Jbusint IN */ 150 { JBC_BIT_DESC(UE_ASYN, panic, jbc_in) }, 151 { JBC_BIT_DESC(CE_ASYN, no_error, jbc_in) }, 152 { JBC_BIT_DESC(JTE, panic, jbc_in) }, 153 { JBC_BIT_DESC(JBE, panic, jbc_in) }, 154 { JBC_BIT_DESC(JUE, panic, jbc_in) }, 155 { JBC_BIT_DESC(ICISE, panic, jbc_in) }, 156 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 157 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 158 { JBC_BIT_DESC(ILL_BMW, panic, jbc_in) }, 159 { JBC_BIT_DESC(ILL_BMR, panic, jbc_in) }, 160 { JBC_BIT_DESC(BJC, panic, jbc_in) }, 161 162 /* JBC Jbusint Out */ 163 { JBC_BIT_DESC(IJP, panic, jbc_out) }, 164 165 /* 166 * JBC Dmcint ODCD 167 * 168 * Error bits which can be set via a bad PCItool access go through 169 * jbc_safe_acc instead. 170 */ 171 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_safe_acc, jbc_odcd) }, 172 { JBC_BIT_DESC(ILL_ACC_RD, jbc_safe_acc, jbc_odcd) }, 173 { JBC_BIT_DESC(PIO_UNMAP, jbc_safe_acc, jbc_odcd) }, 174 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 175 { JBC_BIT_DESC(PIO_CPE, hw_reset, jbc_odcd) }, 176 { JBC_BIT_DESC(ILL_ACC, jbc_safe_acc, jbc_odcd) }, 177 178 /* JBC Dmcint IDC */ 179 { JBC_BIT_DESC(UNSOL_RD, no_panic, jbc_idc) }, 180 { JBC_BIT_DESC(UNSOL_INTR, no_panic, jbc_idc) }, 181 182 /* JBC CSR */ 183 { JBC_BIT_DESC(EBUS_TO, panic, jbc_csr) } 184 }; 185 186 #define px_err_jbc_keys \ 187 (sizeof (px_err_jbc_tbl)) / (sizeof (px_err_bit_desc_t)) 188 189 /* 190 * UBC error bit table 191 */ 192 #define UBC_BIT_DESC(bit, hdl, erpt) \ 193 UBC_INTERRUPT_STATUS_ ## bit ## _P, \ 194 0, \ 195 PX_ERR_BIT_HANDLE(hdl), \ 196 PX_ERPT_SEND(erpt), \ 197 PX_ERR_UBC_CLASS(bit) }, \ 198 { UBC_INTERRUPT_STATUS_ ## bit ## _S, \ 199 0, \ 200 PX_ERR_BIT_HANDLE(hdl), \ 201 PX_ERPT_SEND(erpt), \ 202 PX_ERR_UBC_CLASS(bit) 203 px_err_bit_desc_t px_err_ubc_tbl[] = { 204 /* UBC FATAL */ 205 { UBC_BIT_DESC(DMARDUEA, no_panic, ubc_fatal) }, 206 { UBC_BIT_DESC(DMAWTUEA, panic, ubc_fatal) }, 207 { UBC_BIT_DESC(MEMRDAXA, panic, ubc_fatal) }, 208 { UBC_BIT_DESC(MEMWTAXA, panic, ubc_fatal) }, 209 { UBC_BIT_DESC(DMARDUEB, no_panic, ubc_fatal) }, 210 { UBC_BIT_DESC(DMAWTUEB, panic, ubc_fatal) }, 211 { UBC_BIT_DESC(MEMRDAXB, panic, ubc_fatal) }, 212 { UBC_BIT_DESC(MEMWTAXB, panic, ubc_fatal) }, 213 { UBC_BIT_DESC(PIOWTUE, panic, ubc_fatal) }, 214 { UBC_BIT_DESC(PIOWBEUE, panic, ubc_fatal) }, 215 { UBC_BIT_DESC(PIORBEUE, panic, ubc_fatal) } 216 }; 217 218 #define px_err_ubc_keys \ 219 (sizeof (px_err_ubc_tbl)) / (sizeof (px_err_bit_desc_t)) 220 221 222 char *ubc_class_eid_qualifier[] = { 223 "-mem", 224 "-channel", 225 "-cpu", 226 "-path" 227 }; 228 229 230 /* 231 * DMC error bit tables 232 */ 233 #define IMU_BIT_DESC(bit, hdl, erpt) \ 234 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 235 0, \ 236 PX_ERR_BIT_HANDLE(hdl), \ 237 PX_ERPT_SEND(erpt), \ 238 PX_ERR_DMC_CLASS(bit) }, \ 239 { IMU_INTERRUPT_STATUS_ ## bit ## _S, \ 240 0, \ 241 PX_ERR_BIT_HANDLE(hdl), \ 242 PX_ERPT_SEND(erpt), \ 243 PX_ERR_DMC_CLASS(bit) 244 px_err_bit_desc_t px_err_imu_tbl[] = { 245 /* DMC IMU RDS */ 246 { IMU_BIT_DESC(MSI_MAL_ERR, panic, imu_rds) }, 247 { IMU_BIT_DESC(MSI_PAR_ERR, panic, imu_rds) }, 248 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, panic, imu_rds) }, 249 { IMU_BIT_DESC(PMPME_MES_NOT_EN, panic, imu_rds) }, 250 { IMU_BIT_DESC(FATAL_MES_NOT_EN, panic, imu_rds) }, 251 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, panic, imu_rds) }, 252 { IMU_BIT_DESC(COR_MES_NOT_EN, panic, imu_rds) }, 253 { IMU_BIT_DESC(MSI_NOT_EN, panic, imu_rds) }, 254 255 /* DMC IMU SCS */ 256 { IMU_BIT_DESC(EQ_NOT_EN, panic, imu_scs) }, 257 258 /* DMC IMU */ 259 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 260 }; 261 262 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 263 264 /* mmu errors */ 265 #define MMU_BIT_DESC(bit, hdl, erpt) \ 266 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 267 0, \ 268 PX_ERR_BIT_HANDLE(hdl), \ 269 PX_ERPT_SEND(erpt), \ 270 PX_ERR_DMC_CLASS(bit) }, \ 271 { MMU_INTERRUPT_STATUS_ ## bit ## _S, \ 272 0, \ 273 PX_ERR_BIT_HANDLE(hdl), \ 274 PX_ERPT_SEND(erpt), \ 275 PX_ERR_DMC_CLASS(bit) 276 px_err_bit_desc_t px_err_mmu_tbl[] = { 277 /* DMC MMU TFAR/TFSR */ 278 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 279 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 280 { MMU_BIT_DESC(TRN_ERR, panic, mmu_tfar_tfsr) }, 281 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 282 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 283 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 284 { MMU_BIT_DESC(TTC_DPE, mmu_parity, mmu_tfar_tfsr) }, 285 { MMU_BIT_DESC(TBW_DME, panic, mmu_tfar_tfsr) }, 286 { MMU_BIT_DESC(TBW_UDE, panic, mmu_tfar_tfsr) }, 287 { MMU_BIT_DESC(TBW_ERR, panic, mmu_tfar_tfsr) }, 288 { MMU_BIT_DESC(TBW_DPE, mmu_parity, mmu_tfar_tfsr) }, 289 290 /* DMC MMU */ 291 { MMU_BIT_DESC(TTC_CAE, panic, mmu) } 292 }; 293 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 294 295 296 /* 297 * PEC error bit tables 298 */ 299 #define ILU_BIT_DESC(bit, hdl, erpt) \ 300 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 301 0, \ 302 PX_ERR_BIT_HANDLE(hdl), \ 303 PX_ERPT_SEND(erpt), \ 304 PX_ERR_PEC_CLASS(bit) }, \ 305 { ILU_INTERRUPT_STATUS_ ## bit ## _S, \ 306 0, \ 307 PX_ERR_BIT_HANDLE(hdl), \ 308 PX_ERPT_SEND(erpt), \ 309 PX_ERR_PEC_CLASS(bit) 310 px_err_bit_desc_t px_err_ilu_tbl[] = { 311 /* PEC ILU none */ 312 { ILU_BIT_DESC(IHB_PE, panic, pec_ilu) } 313 }; 314 #define px_err_ilu_keys \ 315 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 316 317 /* 318 * PEC UE errors implementation is incomplete pending PCIE generic 319 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 320 */ 321 /* pec ue errors */ 322 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 323 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 324 0, \ 325 PX_ERR_BIT_HANDLE(hdl), \ 326 PX_ERPT_SEND(erpt), \ 327 PX_ERR_PEC_CLASS(bit) }, \ 328 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 329 0, \ 330 PX_ERR_BIT_HANDLE(hdl), \ 331 PX_ERPT_SEND(erpt), \ 332 PX_ERR_PEC_CLASS(bit) 333 #define TLU_UC_OB_BIT_DESC(bit, hdl, erpt) \ 334 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 335 0, \ 336 PX_ERR_BIT_HANDLE(hdl), \ 337 PX_ERPT_SEND(erpt), \ 338 PX_ERR_PEC_OB_CLASS(bit) }, \ 339 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 340 0, \ 341 PX_ERR_BIT_HANDLE(hdl), \ 342 PX_ERPT_SEND(erpt), \ 343 PX_ERR_PEC_CLASS(bit) 344 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 345 /* PCI-E Receive Uncorrectable Errors */ 346 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 347 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 348 349 /* PCI-E Transmit Uncorrectable Errors */ 350 { TLU_UC_OB_BIT_DESC(ECRC, pciex_ue, pciex_rx_ue) }, 351 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 352 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 353 354 /* PCI-E Rx/Tx Uncorrectable Errors */ 355 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 356 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 357 358 /* Other PCI-E Uncorrectable Errors */ 359 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 360 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 361 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 362 363 /* Not used */ 364 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 365 }; 366 #define px_err_tlu_ue_keys \ 367 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 368 369 370 /* 371 * PEC CE errors implementation is incomplete pending PCIE generic 372 * fabric rules. 373 */ 374 /* pec ce errors */ 375 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 376 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 377 0, \ 378 PX_ERR_BIT_HANDLE(hdl), \ 379 PX_ERPT_SEND(erpt), \ 380 PX_ERR_PEC_CLASS(bit) }, \ 381 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 382 0, \ 383 PX_ERR_BIT_HANDLE(hdl), \ 384 PX_ERPT_SEND(erpt), \ 385 PX_ERR_PEC_CLASS(bit) 386 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 387 /* PCI-E Correctable Errors */ 388 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 389 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 390 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 391 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 392 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 393 }; 394 #define px_err_tlu_ce_keys \ 395 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 396 397 398 /* pec oe errors */ 399 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 400 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 401 0, \ 402 PX_ERR_BIT_HANDLE(hdl), \ 403 PX_ERPT_SEND(erpt), \ 404 PX_ERR_PEC_CLASS(bit) }, \ 405 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 406 0, \ 407 PX_ERR_BIT_HANDLE(hdl), \ 408 PX_ERPT_SEND(erpt), \ 409 PX_ERR_PEC_CLASS(bit) 410 #define TLU_OE_OB_BIT_DESC(bit, hdl, erpt) \ 411 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 412 0, \ 413 PX_ERR_BIT_HANDLE(hdl), \ 414 PX_ERPT_SEND(erpt), \ 415 PX_ERR_PEC_OB_CLASS(bit) }, \ 416 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 417 0, \ 418 PX_ERR_BIT_HANDLE(hdl), \ 419 PX_ERPT_SEND(erpt), \ 420 PX_ERR_PEC_OB_CLASS(bit) 421 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 422 /* TLU Other Event Status (receive only) */ 423 { TLU_OE_BIT_DESC(MRC, hw_reset, pciex_rx_oe) }, 424 425 /* TLU Other Event Status (rx + tx) */ 426 { TLU_OE_BIT_DESC(WUC, wuc_ruc, pciex_rx_tx_oe) }, 427 { TLU_OE_BIT_DESC(RUC, wuc_ruc, pciex_rx_tx_oe) }, 428 { TLU_OE_BIT_DESC(CRS, no_panic, pciex_rx_tx_oe) }, 429 430 /* TLU Other Event */ 431 { TLU_OE_BIT_DESC(IIP, panic, pciex_oe) }, 432 { TLU_OE_BIT_DESC(EDP, panic, pciex_oe) }, 433 { TLU_OE_BIT_DESC(EHP, panic, pciex_oe) }, 434 { TLU_OE_OB_BIT_DESC(TLUEITMO, panic, pciex_oe) }, 435 { TLU_OE_BIT_DESC(LIN, no_panic, pciex_oe) }, 436 { TLU_OE_BIT_DESC(LRS, no_panic, pciex_oe) }, 437 { TLU_OE_BIT_DESC(LDN, tlu_ldn, pciex_oe) }, 438 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_oe) }, 439 { TLU_OE_BIT_DESC(ERU, panic, pciex_oe) }, 440 { TLU_OE_BIT_DESC(ERO, panic, pciex_oe) }, 441 { TLU_OE_BIT_DESC(EMP, panic, pciex_oe) }, 442 { TLU_OE_BIT_DESC(EPE, panic, pciex_oe) }, 443 { TLU_OE_BIT_DESC(ERP, panic, pciex_oe) }, 444 { TLU_OE_BIT_DESC(EIP, panic, pciex_oe) } 445 }; 446 447 #define px_err_tlu_oe_keys \ 448 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 449 450 451 /* 452 * All the following tables below are for LPU Interrupts. These interrupts 453 * are *NOT* error interrupts, but event status interrupts. 454 * 455 * These events are probably of most interest to: 456 * o Hotplug 457 * o Power Management 458 * o etc... 459 * 460 * There are also a few events that would be interresting for FMA. 461 * Again none of the regiseters below state that an error has occured 462 * or that data has been lost. If anything, they give status that an 463 * error is *about* to occur. examples 464 * o INT_SKP_ERR - indicates clock between fire and child is too far 465 * off and is most unlikely able to compensate 466 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 467 * HW recoverable, but will like end up as a future 468 * fabric error as well. 469 * 470 * For now, we don't care about any of these errors and should be ignore, 471 * but cleared. 472 */ 473 474 /* LPU Link Interrupt Table */ 475 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 476 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 477 0, \ 478 NULL, \ 479 NULL, \ 480 "" 481 px_err_bit_desc_t px_err_lpul_tbl[] = { 482 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 483 }; 484 #define px_err_lpul_keys \ 485 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 486 487 /* LPU Physical Interrupt Table */ 488 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 489 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 490 0, \ 491 NULL, \ 492 NULL, \ 493 "" 494 px_err_bit_desc_t px_err_lpup_tbl[] = { 495 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 496 }; 497 #define px_err_lpup_keys \ 498 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 499 500 /* LPU Receive Interrupt Table */ 501 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 502 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 503 0, \ 504 NULL, \ 505 NULL, \ 506 "" 507 px_err_bit_desc_t px_err_lpur_tbl[] = { 508 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 509 }; 510 #define px_err_lpur_keys \ 511 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 512 513 /* LPU Transmit Interrupt Table */ 514 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 515 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 516 0, \ 517 NULL, \ 518 NULL, \ 519 "" 520 px_err_bit_desc_t px_err_lpux_tbl[] = { 521 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 522 }; 523 #define px_err_lpux_keys \ 524 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 525 526 /* LPU LTSSM Interrupt Table */ 527 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 528 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 529 0, \ 530 NULL, \ 531 NULL, \ 532 "" 533 px_err_bit_desc_t px_err_lpus_tbl[] = { 534 { LPUS_BIT_DESC(ANY, NULL, NULL) } 535 }; 536 #define px_err_lpus_keys \ 537 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 538 539 /* LPU Gigablaze Glue Interrupt Table */ 540 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 541 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 542 0, \ 543 NULL, \ 544 NULL, \ 545 "" 546 px_err_bit_desc_t px_err_lpug_tbl[] = { 547 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 548 }; 549 #define px_err_lpug_keys \ 550 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 551 552 553 /* Mask and Tables */ 554 #define MnT6X(pre) \ 555 &px_ ## pre ## _intr_mask, \ 556 &px_ ## pre ## _log_mask, \ 557 &px_ ## pre ## _count_mask, \ 558 px_err_ ## pre ## _tbl, \ 559 px_err_ ## pre ## _keys, \ 560 PX_REG_XBC, \ 561 0 562 563 #define MnT6(pre) \ 564 &px_ ## pre ## _intr_mask, \ 565 &px_ ## pre ## _log_mask, \ 566 &px_ ## pre ## _count_mask, \ 567 px_err_ ## pre ## _tbl, \ 568 px_err_ ## pre ## _keys, \ 569 PX_REG_CSR, \ 570 0 571 572 /* LPU Registers Addresses */ 573 #define LR4(pre) \ 574 NULL, \ 575 LPU_ ## pre ## _INTERRUPT_MASK, \ 576 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 577 LPU_ ## pre ## _INTERRUPT_AND_STATUS 578 579 /* LPU Registers Addresses with Irregularities */ 580 #define LR4_FIXME(pre) \ 581 NULL, \ 582 LPU_ ## pre ## _INTERRUPT_MASK, \ 583 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 584 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 585 586 /* TLU Registers Addresses */ 587 #define TR4(pre) \ 588 TLU_ ## pre ## _LOG_ENABLE, \ 589 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 590 TLU_ ## pre ## _INTERRUPT_STATUS, \ 591 TLU_ ## pre ## _STATUS_CLEAR 592 593 /* Registers Addresses for JBC, UBC, MMU, IMU and ILU */ 594 #define R4(pre) \ 595 pre ## _ERROR_LOG_ENABLE, \ 596 pre ## _INTERRUPT_ENABLE, \ 597 pre ## _INTERRUPT_STATUS, \ 598 pre ## _ERROR_STATUS_CLEAR 599 600 /* Bits in chip_mask, set according to type. */ 601 #define CHP_O BITMASK(PX_CHIP_OBERON) 602 #define CHP_F BITMASK(PX_CHIP_FIRE) 603 #define CHP_FO (CHP_F | CHP_O) 604 605 /* 606 * Register error handling tables. 607 * The ID Field (first field) is identified by an enum px_err_id_t. 608 * It is located in px_err.h 609 */ 610 static const 611 px_err_reg_desc_t px_err_reg_tbl[] = { 612 { CHP_F, MnT6X(jbc), R4(JBC), "JBC Error"}, 613 { CHP_O, MnT6X(ubc), R4(UBC), "UBC Error"}, 614 { CHP_FO, MnT6(mmu), R4(MMU), "MMU Error"}, 615 { CHP_FO, MnT6(imu), R4(IMU), "IMU Error"}, 616 { CHP_FO, MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 617 { CHP_FO, MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 618 { CHP_FO, MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 619 { CHP_FO, MnT6(ilu), R4(ILU), "ILU Error"}, 620 { CHP_F, MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 621 { CHP_F, MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 622 { CHP_F, MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 623 { CHP_F, MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 624 { CHP_F, MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 625 { CHP_F, MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"}, 626 }; 627 628 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 629 630 typedef struct px_err_ss { 631 uint64_t err_status[PX_ERR_REG_KEYS]; 632 } px_err_ss_t; 633 634 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, int block); 635 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 636 px_err_ss_t *ss); 637 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 638 int err, int caller); 639 640 /* 641 * px_err_cb_intr: 642 * Interrupt handler for the JBC/UBC block. 643 * o lock 644 * o create derr 645 * o px_err_cmn_intr 646 * o unlock 647 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 648 */ 649 uint_t 650 px_err_cb_intr(caddr_t arg) 651 { 652 px_fault_t *px_fault_p = (px_fault_t *)arg; 653 dev_info_t *rpdip = px_fault_p->px_fh_dip; 654 px_t *px_p = DIP_TO_STATE(rpdip); 655 int err; 656 ddi_fm_error_t derr; 657 658 /* Create the derr */ 659 bzero(&derr, sizeof (ddi_fm_error_t)); 660 derr.fme_version = DDI_FME_VERSION; 661 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 662 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 663 664 mutex_enter(&px_p->px_fm_mutex); 665 px_p->px_fm_mutex_owner = curthread; 666 667 err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_HOST); 668 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 669 INTR_IDLE_STATE); 670 671 px_p->px_fm_mutex_owner = NULL; 672 mutex_exit(&px_p->px_fm_mutex); 673 674 px_err_panic(err, PX_HB, PX_NO_ERROR); 675 676 return (DDI_INTR_CLAIMED); 677 } 678 679 /* 680 * px_err_dmc_pec_intr: 681 * Interrupt handler for the DMC/PEC block. 682 * o lock 683 * o create derr 684 * o px_err_cmn_intr(leaf, with out cb) 685 * o pcie_scan_fabric (leaf) 686 * o unlock 687 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 688 */ 689 uint_t 690 px_err_dmc_pec_intr(caddr_t arg) 691 { 692 px_fault_t *px_fault_p = (px_fault_t *)arg; 693 dev_info_t *rpdip = px_fault_p->px_fh_dip; 694 px_t *px_p = DIP_TO_STATE(rpdip); 695 int rc_err, fab_err = PF_NO_PANIC; 696 ddi_fm_error_t derr; 697 698 /* Create the derr */ 699 bzero(&derr, sizeof (ddi_fm_error_t)); 700 derr.fme_version = DDI_FME_VERSION; 701 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 702 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 703 704 mutex_enter(&px_p->px_fm_mutex); 705 px_p->px_fm_mutex_owner = curthread; 706 707 /* send ereport/handle/clear fire registers */ 708 rc_err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_PCIE); 709 710 /* Check all child devices for errors */ 711 if (!px_lib_is_in_drain_state(px_p)) { 712 fab_err = pf_scan_fabric(rpdip, &derr, px_p->px_dq_p, 713 &px_p->px_dq_tail); 714 } 715 716 /* Set the interrupt state to idle */ 717 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 718 INTR_IDLE_STATE); 719 720 px_p->px_fm_mutex_owner = NULL; 721 mutex_exit(&px_p->px_fm_mutex); 722 723 px_err_panic(rc_err, PX_RC, fab_err); 724 725 return (DDI_INTR_CLAIMED); 726 } 727 728 /* 729 * Proper csr_base is responsibility of the caller. (Called from px_lib_dev_init 730 * via px_err_reg_setup_all for pcie error registers; called from 731 * px_cb_add_intr for jbc/ubc from px_cb_attach.) 732 * 733 * Note: reg_id is passed in instead of reg_desc since this function is called 734 * from px_lib4u.c, which doesn't know about the structure of the table. 735 */ 736 void 737 px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base) 738 { 739 const px_err_reg_desc_t *reg_desc_p = &px_err_reg_tbl[reg_id]; 740 uint64_t intr_mask = *reg_desc_p->intr_mask_p; 741 uint64_t log_mask = *reg_desc_p->log_mask_p; 742 743 /* Enable logs if it exists */ 744 if (reg_desc_p->log_addr != NULL) 745 CSR_XS(csr_base, reg_desc_p->log_addr, log_mask); 746 747 /* 748 * For readability you in code you set 1 to enable an interrupt. 749 * But in Fire it's backwards. You set 1 to *disable* an intr. 750 * Reverse the user tunable intr mask field. 751 * 752 * Disable All Errors 753 * Clear All Errors 754 * Enable Errors 755 */ 756 CSR_XS(csr_base, reg_desc_p->enable_addr, 0); 757 CSR_XS(csr_base, reg_desc_p->clear_addr, -1); 758 CSR_XS(csr_base, reg_desc_p->enable_addr, intr_mask); 759 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", reg_desc_p->msg, 760 CSR_XR(csr_base, reg_desc_p->enable_addr)); 761 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", reg_desc_p->msg, 762 CSR_XR(csr_base, reg_desc_p->status_addr)); 763 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", reg_desc_p->msg, 764 CSR_XR(csr_base, reg_desc_p->clear_addr)); 765 if (reg_desc_p->log_addr != NULL) { 766 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", reg_desc_p->msg, 767 CSR_XR(csr_base, reg_desc_p->log_addr)); 768 } 769 } 770 771 void 772 px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base) 773 { 774 const px_err_reg_desc_t *reg_desc_p = &px_err_reg_tbl[reg_id]; 775 uint64_t val = (reg_id >= PX_ERR_LPU_LINK) ? -1 : 0; 776 777 if (reg_desc_p->log_addr != NULL) 778 CSR_XS(csr_base, reg_desc_p->log_addr, val); 779 CSR_XS(csr_base, reg_desc_p->enable_addr, val); 780 } 781 782 /* 783 * Set up pcie error registers. 784 */ 785 void 786 px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base, boolean_t enable) 787 { 788 px_err_id_t reg_id; 789 const px_err_reg_desc_t *reg_desc_p; 790 void (*px_err_reg_func)(px_err_id_t, caddr_t); 791 792 /* 793 * JBC or XBC are enabled during adding of common block interrupts, 794 * not done here. 795 */ 796 px_err_reg_func = (enable ? px_err_reg_enable : px_err_reg_disable); 797 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id++) { 798 reg_desc_p = &px_err_reg_tbl[reg_id]; 799 if ((reg_desc_p->chip_mask & chip_mask) && 800 (reg_desc_p->reg_bank == PX_REG_CSR)) 801 px_err_reg_func(reg_id, csr_base); 802 } 803 } 804 805 /* 806 * px_err_cmn_intr: 807 * Common function called by trap, mondo and fabric intr. 808 * o Snap shot current fire registers 809 * o check for safe access 810 * o send ereport and clear snap shot registers 811 * o create and queue RC info for later use in fabric scan. 812 * o RUC/WUC, PTLP, MMU Errors(CA), UR 813 * o check severity of snap shot registers 814 * 815 * @param px_p leaf in which to check access 816 * @param derr fm err data structure to be updated 817 * @param caller PX_TRAP_CALL | PX_INTR_CALL 818 * @param block PX_FM_BLOCK_HOST | PX_FM_BLOCK_PCIE | PX_FM_BLOCK_ALL 819 * @return err PX_NO_PANIC | PX_PANIC | PX_HW_RESET | PX_PROTECTED 820 */ 821 int 822 px_err_cmn_intr(px_t *px_p, ddi_fm_error_t *derr, int caller, int block) 823 { 824 px_err_ss_t ss = {0}; 825 int err; 826 827 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 828 829 /* check for safe access */ 830 px_err_safeacc_check(px_p, derr); 831 832 /* snap shot the current fire registers */ 833 px_err_snapshot(px_p, &ss, block); 834 835 /* send ereports/handle/clear registers */ 836 err = px_err_erpt_and_clr(px_p, derr, &ss); 837 838 /* check for error severity */ 839 err = px_err_check_severity(px_p, derr, err, caller); 840 841 /* Mark the On Trap Handle if an error occured */ 842 if (err != PX_NO_ERROR) { 843 px_pec_t *pec_p = px_p->px_pec_p; 844 on_trap_data_t *otd = pec_p->pec_ontrap_data; 845 846 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 847 otd->ot_trap |= OT_DATA_ACCESS; 848 } 849 850 return (err); 851 } 852 853 /* 854 * Static function 855 */ 856 857 /* 858 * px_err_snapshot: 859 * Take a current snap shot of all the fire error registers. This includes 860 * JBC/UBC, DMC, and PEC depending on the block flag 861 * 862 * @param px_p leaf in which to take the snap shot. 863 * @param ss pre-allocated memory to store the snap shot. 864 * @param chk_cb boolean on whether to store jbc/ubc register. 865 */ 866 static void 867 px_err_snapshot(px_t *px_p, px_err_ss_t *ss_p, int block) 868 { 869 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 870 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 871 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 872 caddr_t csr_base; 873 uint8_t chip_mask = 1 << PX_CHIP_TYPE(pxu_p); 874 const px_err_reg_desc_t *reg_desc_p = px_err_reg_tbl; 875 px_err_id_t reg_id; 876 877 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id++, reg_desc_p++) { 878 if (!(reg_desc_p->chip_mask & chip_mask)) 879 continue; 880 881 if ((block & PX_FM_BLOCK_HOST) && 882 (reg_desc_p->reg_bank == PX_REG_XBC)) 883 csr_base = xbc_csr_base; 884 else if ((block & PX_FM_BLOCK_PCIE) && 885 (reg_desc_p->reg_bank == PX_REG_CSR)) 886 csr_base = pec_csr_base; 887 else { 888 ss_p->err_status[reg_id] = 0; 889 continue; 890 } 891 892 ss_p->err_status[reg_id] = CSR_XR(csr_base, 893 reg_desc_p->status_addr); 894 } 895 } 896 897 /* 898 * px_err_erpt_and_clr: 899 * This function does the following thing to all the fire registers based 900 * on an earlier snap shot. 901 * o Send ereport 902 * o Handle the error 903 * o Clear the error 904 * 905 * @param px_p leaf in which to take the snap shot. 906 * @param derr fm err in which the ereport is to be based on 907 * @param ss_p pre-allocated memory to store the snap shot. 908 */ 909 static int 910 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss_p) 911 { 912 dev_info_t *rpdip = px_p->px_dip; 913 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 914 caddr_t csr_base; 915 const px_err_reg_desc_t *err_reg_tbl; 916 px_err_bit_desc_t *err_bit_tbl; 917 px_err_bit_desc_t *err_bit_desc; 918 919 uint64_t *count_mask; 920 uint64_t clear_addr; 921 uint64_t ss_reg; 922 923 int (*err_handler)(); 924 int (*erpt_handler)(); 925 int reg_id, key; 926 int err = PX_NO_ERROR; 927 int biterr = 0; 928 929 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 930 931 /* send erport/handle/clear JBC errors */ 932 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id++) { 933 /* Get the correct register description table */ 934 err_reg_tbl = &px_err_reg_tbl[reg_id]; 935 936 /* Only look at enabled groups. */ 937 if (!(BIT_TST(err_reg_tbl->chip_mask, PX_CHIP_TYPE(pxu_p)))) 938 continue; 939 940 /* Get the correct CSR BASE */ 941 csr_base = (caddr_t)pxu_p->px_address[err_reg_tbl->reg_bank]; 942 943 /* If there are no errors in this register, continue */ 944 ss_reg = ss_p->err_status[reg_id]; 945 if (!ss_reg) 946 continue; 947 948 /* Get pointers to masks and register addresses */ 949 count_mask = err_reg_tbl->count_mask_p; 950 clear_addr = err_reg_tbl->clear_addr; 951 952 /* Get the register BIT description table */ 953 err_bit_tbl = err_reg_tbl->err_bit_tbl; 954 955 /* For each known bit in the register send erpt and handle */ 956 for (key = 0; key < err_reg_tbl->err_bit_keys; key++) { 957 /* 958 * If the ss_reg is set for this bit, 959 * send ereport and handle 960 */ 961 err_bit_desc = &err_bit_tbl[key]; 962 if (!BIT_TST(ss_reg, err_bit_desc->bit)) 963 continue; 964 965 /* Increment the counter if necessary */ 966 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 967 err_bit_desc->counter++; 968 } 969 970 /* Error Handle for this bit */ 971 err_handler = err_bit_desc->err_handler; 972 if (err_handler) { 973 biterr = err_handler(rpdip, csr_base, derr, 974 err_reg_tbl, err_bit_desc); 975 err |= biterr; 976 } 977 978 /* 979 * Send the ereport if it's an UNEXPECTED err. 980 * This is the only place where PX_EXPECTED is utilized. 981 */ 982 erpt_handler = err_bit_desc->erpt_handler; 983 if ((derr->fme_flag != DDI_FM_ERR_UNEXPECTED) || 984 (biterr == PX_EXPECTED)) 985 continue; 986 987 if (erpt_handler) 988 (void) erpt_handler(rpdip, csr_base, ss_reg, 989 derr, err_bit_desc->bit, 990 err_bit_desc->class_name); 991 } 992 993 /* Clear the register and error */ 994 CSR_XS(csr_base, clear_addr, ss_reg); 995 } 996 997 return (err); 998 } 999 1000 /* 1001 * px_err_check_severity: 1002 * Check the severity of the fire error based on an earlier snapshot 1003 * 1004 * @param px_p leaf in which to take the snap shot. 1005 * @param derr fm err in which the ereport is to be based on 1006 * @param err fire register error status 1007 * @param caller PX_TRAP_CALL | PX_INTR_CALL | PX_LIB_CALL 1008 */ 1009 static int 1010 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 1011 { 1012 px_pec_t *pec_p = px_p->px_pec_p; 1013 boolean_t is_safeacc = B_FALSE; 1014 1015 /* 1016 * Nothing to do if called with no error. 1017 * The err could have already been set to PX_NO_PANIC, which means the 1018 * system doesn't need to panic, but PEEK/POKE still failed. 1019 */ 1020 if (err == PX_NO_ERROR) 1021 return (err); 1022 1023 /* Cautious access error handling */ 1024 switch (derr->fme_flag) { 1025 case DDI_FM_ERR_EXPECTED: 1026 if (caller == PX_TRAP_CALL) { 1027 /* 1028 * for ddi_caut_get treat all events as nonfatal 1029 * The trampoline will set err_ena = 0, 1030 * err_status = NONFATAL. 1031 */ 1032 derr->fme_status = DDI_FM_NONFATAL; 1033 is_safeacc = B_TRUE; 1034 } else { 1035 /* 1036 * For ddi_caut_put treat all events as nonfatal. Here 1037 * we have the handle and can call ndi_fm_acc_err_set(). 1038 */ 1039 derr->fme_status = DDI_FM_NONFATAL; 1040 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 1041 is_safeacc = B_TRUE; 1042 } 1043 break; 1044 case DDI_FM_ERR_PEEK: 1045 case DDI_FM_ERR_POKE: 1046 /* 1047 * For ddi_peek/poke treat all events as nonfatal. 1048 */ 1049 is_safeacc = B_TRUE; 1050 break; 1051 default: 1052 is_safeacc = B_FALSE; 1053 } 1054 1055 /* re-adjust error status from safe access, forgive all errors */ 1056 if (is_safeacc) 1057 return (PX_NO_PANIC); 1058 1059 return (err); 1060 } 1061 1062 /* predefined convenience functions */ 1063 /* ARGSUSED */ 1064 void 1065 px_err_log_handle(dev_info_t *rpdip, px_err_reg_desc_t *err_reg_descr, 1066 px_err_bit_desc_t *err_bit_descr, char *msg) 1067 { 1068 DBG(DBG_ERR_INTR, rpdip, 1069 "Bit %d, %s, at %s(0x%x) has occured %d times with a severity " 1070 "of \"%s\"\n", 1071 err_bit_descr->bit, err_bit_descr->class_name, 1072 err_reg_descr->msg, err_reg_descr->status_addr, 1073 err_bit_descr->counter, msg); 1074 } 1075 1076 /* ARGSUSED */ 1077 int 1078 px_err_hw_reset_handle(dev_info_t *rpdip, caddr_t csr_base, 1079 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1080 px_err_bit_desc_t *err_bit_descr) 1081 { 1082 if (px_log & PX_HW_RESET) { 1083 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1084 "HW RESET"); 1085 } 1086 1087 return (PX_HW_RESET); 1088 } 1089 1090 /* ARGSUSED */ 1091 int 1092 px_err_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 1093 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1094 px_err_bit_desc_t *err_bit_descr) 1095 { 1096 if (px_log & PX_PANIC) { 1097 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, "PANIC"); 1098 } 1099 1100 return (PX_PANIC); 1101 } 1102 1103 /* ARGSUSED */ 1104 int 1105 px_err_protected_handle(dev_info_t *rpdip, caddr_t csr_base, 1106 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1107 px_err_bit_desc_t *err_bit_descr) 1108 { 1109 if (px_log & PX_PROTECTED) { 1110 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1111 "PROTECTED"); 1112 } 1113 1114 return (PX_PROTECTED); 1115 } 1116 1117 /* ARGSUSED */ 1118 int 1119 px_err_no_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 1120 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1121 px_err_bit_desc_t *err_bit_descr) 1122 { 1123 if (px_log & PX_NO_PANIC) { 1124 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1125 "NO PANIC"); 1126 } 1127 1128 return (PX_NO_PANIC); 1129 } 1130 1131 /* ARGSUSED */ 1132 int 1133 px_err_no_error_handle(dev_info_t *rpdip, caddr_t csr_base, 1134 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1135 px_err_bit_desc_t *err_bit_descr) 1136 { 1137 if (px_log & PX_NO_ERROR) { 1138 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1139 "NO ERROR"); 1140 } 1141 1142 return (PX_NO_ERROR); 1143 } 1144 1145 /* ARGSUSED */ 1146 PX_ERPT_SEND_DEC(do_not) 1147 { 1148 return (PX_NO_ERROR); 1149 } 1150 1151 1152 /* UBC FATAL - see io erpt doc, section 1.1 */ 1153 /* ARGSUSED */ 1154 PX_ERPT_SEND_DEC(ubc_fatal) 1155 { 1156 char buf[FM_MAX_CLASS]; 1157 uint64_t memory_ue_log, marked; 1158 char unum[FM_MAX_CLASS]; 1159 int unum_length; 1160 uint64_t device_id = 0; 1161 uint8_t cpu_version = 0; 1162 nvlist_t *resource = NULL; 1163 1164 unum[0] = '\0'; 1165 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1166 1167 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG); 1168 marked = (memory_ue_log >> UBC_MEMORY_UE_LOG_MARKED) & 1169 UBC_MEMORY_UE_LOG_MARKED_MASK; 1170 1171 if ((strstr(class_name, "ubc.piowtue") != NULL) || 1172 (strstr(class_name, "ubc.piowbeue") != NULL) || 1173 (strstr(class_name, "ubc.piorbeue") != NULL) || 1174 (strstr(class_name, "ubc.dmarduea") != NULL) || 1175 (strstr(class_name, "ubc.dmardueb") != NULL)) { 1176 int eid = (memory_ue_log >> UBC_MEMORY_UE_LOG_EID) & 1177 UBC_MEMORY_UE_LOG_EID_MASK; 1178 (void) strncat(buf, ubc_class_eid_qualifier[eid], 1179 FM_MAX_CLASS); 1180 1181 if (eid == UBC_EID_MEM) { 1182 uint64_t phys_addr = memory_ue_log & 1183 MMU_OBERON_PADDR_MASK; 1184 uint64_t offset = (uint64_t)-1; 1185 1186 resource = fm_nvlist_create(NULL); 1187 if (&plat_get_mem_unum) { 1188 if ((plat_get_mem_unum(0, 1189 phys_addr, 0, B_TRUE, 0, unum, 1190 FM_MAX_CLASS, &unum_length)) != 0) 1191 unum[0] = '\0'; 1192 } 1193 fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1194 NULL, unum, NULL, offset); 1195 1196 } else if (eid == UBC_EID_CPU) { 1197 int cpuid = (marked & UBC_MARKED_MAX_CPUID_MASK); 1198 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1199 1200 resource = fm_nvlist_create(NULL); 1201 cpu_version = cpunodes[cpuid].version; 1202 device_id = cpunodes[cpuid].device_id; 1203 (void) snprintf(sbuf, sizeof (sbuf), "%lX", 1204 device_id); 1205 (void) fm_fmri_cpu_set(resource, 1206 FM_CPU_SCHEME_VERSION, NULL, cpuid, 1207 &cpu_version, sbuf); 1208 } 1209 } 1210 1211 if (resource) { 1212 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1213 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1214 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1215 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1216 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1217 OBERON_UBC_IE, DATA_TYPE_UINT64, 1218 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1219 OBERON_UBC_IS, DATA_TYPE_UINT64, 1220 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1221 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1222 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1223 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1224 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1225 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1226 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1227 OBERON_UBC_RESOURCE, DATA_TYPE_NVLIST, resource, 1228 NULL); 1229 fm_nvlist_destroy(resource, FM_NVA_FREE); 1230 } else { 1231 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1232 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1233 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1234 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1235 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1236 OBERON_UBC_IE, DATA_TYPE_UINT64, 1237 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1238 OBERON_UBC_IS, DATA_TYPE_UINT64, 1239 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1240 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1241 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1242 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1243 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1244 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1245 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1246 NULL); 1247 } 1248 1249 return (PX_NO_PANIC); 1250 } 1251 1252 /* JBC FATAL */ 1253 PX_ERPT_SEND_DEC(jbc_fatal) 1254 { 1255 char buf[FM_MAX_CLASS]; 1256 boolean_t pri = PX_ERR_IS_PRI(bit); 1257 1258 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1259 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1260 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1261 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1262 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1263 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1264 FIRE_JBC_IE, DATA_TYPE_UINT64, 1265 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1266 FIRE_JBC_IS, DATA_TYPE_UINT64, 1267 ss_reg, 1268 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1269 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1270 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1271 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1272 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1273 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1274 NULL); 1275 1276 return (PX_NO_PANIC); 1277 } 1278 1279 /* JBC MERGE */ 1280 PX_ERPT_SEND_DEC(jbc_merge) 1281 { 1282 char buf[FM_MAX_CLASS]; 1283 boolean_t pri = PX_ERR_IS_PRI(bit); 1284 1285 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1286 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1287 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1288 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1289 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1290 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1291 FIRE_JBC_IE, DATA_TYPE_UINT64, 1292 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1293 FIRE_JBC_IS, DATA_TYPE_UINT64, 1294 ss_reg, 1295 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1296 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1297 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1298 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1299 NULL); 1300 1301 return (PX_NO_PANIC); 1302 } 1303 1304 /* 1305 * JBC Merge buffer retryable errors: 1306 * Merge buffer parity error (rd_buf): PIO or DMA 1307 * Merge buffer parity error (wr_buf): PIO or DMA 1308 */ 1309 /* ARGSUSED */ 1310 int 1311 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1312 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1313 px_err_bit_desc_t *err_bit_descr) 1314 { 1315 /* 1316 * Holder function to attempt error recovery. When the features 1317 * are in place, look up the address of the transaction in: 1318 * 1319 * paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1320 * paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1321 * 1322 * If the error is a secondary error, there is no log information 1323 * just panic as it is unknown which address has been affected. 1324 * 1325 * Remember the address is pretranslation and might be hard to look 1326 * up the appropriate driver based on the PA. 1327 */ 1328 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1329 err_bit_descr)); 1330 } 1331 1332 /* JBC Jbusint IN */ 1333 PX_ERPT_SEND_DEC(jbc_in) 1334 { 1335 char buf[FM_MAX_CLASS]; 1336 boolean_t pri = PX_ERR_IS_PRI(bit); 1337 1338 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1339 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1340 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1341 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1342 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1343 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1344 FIRE_JBC_IE, DATA_TYPE_UINT64, 1345 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1346 FIRE_JBC_IS, DATA_TYPE_UINT64, 1347 ss_reg, 1348 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1349 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1350 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1351 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1352 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1353 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1354 NULL); 1355 1356 return (PX_NO_PANIC); 1357 } 1358 1359 /* 1360 * JBC Jbusint IN retryable errors 1361 * Log Reg[42:0]. 1362 * Write Data Parity Error: PIO Writes 1363 * Read Data Parity Error: DMA Reads 1364 */ 1365 int 1366 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1367 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1368 px_err_bit_desc_t *err_bit_descr) 1369 { 1370 /* 1371 * Holder function to attempt error recovery. When the features 1372 * are in place, look up the address of the transaction in: 1373 * 1374 * paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1375 * paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1376 * 1377 * If the error is a secondary error, there is no log information 1378 * just panic as it is unknown which address has been affected. 1379 * 1380 * Remember the address is pretranslation and might be hard to look 1381 * up the appropriate driver based on the PA. 1382 */ 1383 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1384 err_bit_descr)); 1385 } 1386 1387 1388 /* JBC Jbusint Out */ 1389 PX_ERPT_SEND_DEC(jbc_out) 1390 { 1391 char buf[FM_MAX_CLASS]; 1392 boolean_t pri = PX_ERR_IS_PRI(bit); 1393 1394 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1395 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1396 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1397 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1398 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1399 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1400 FIRE_JBC_IE, DATA_TYPE_UINT64, 1401 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1402 FIRE_JBC_IS, DATA_TYPE_UINT64, 1403 ss_reg, 1404 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1405 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1406 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1407 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1408 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1409 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1410 NULL); 1411 1412 return (PX_NO_PANIC); 1413 } 1414 1415 /* JBC Dmcint ODCD */ 1416 PX_ERPT_SEND_DEC(jbc_odcd) 1417 { 1418 char buf[FM_MAX_CLASS]; 1419 boolean_t pri = PX_ERR_IS_PRI(bit); 1420 1421 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1422 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1423 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1424 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1425 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1426 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1427 FIRE_JBC_IE, DATA_TYPE_UINT64, 1428 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1429 FIRE_JBC_IS, DATA_TYPE_UINT64, 1430 ss_reg, 1431 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1432 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1433 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1434 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1435 NULL); 1436 1437 return (PX_NO_PANIC); 1438 } 1439 1440 /* 1441 * JBC Dmcint ODCO nonfatal errer handling - 1442 * PIO data parity error: PIO 1443 */ 1444 /* ARGSUSED */ 1445 int 1446 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1447 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1448 px_err_bit_desc_t *err_bit_descr) 1449 { 1450 /* 1451 * Holder function to attempt error recovery. When the features 1452 * are in place, look up the address of the transaction in: 1453 * 1454 * paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1455 * paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1456 * 1457 * If the error is a secondary error, there is no log information 1458 * just panic as it is unknown which address has been affected. 1459 * 1460 * Remember the address is pretranslation and might be hard to look 1461 * up the appropriate driver based on the PA. 1462 */ 1463 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1464 err_bit_descr)); 1465 } 1466 1467 /* Does address in DMCINT error log register match address of pcitool access? */ 1468 static boolean_t 1469 px_jbc_pcitool_addr_match(dev_info_t *rpdip, caddr_t csr_base) 1470 { 1471 px_t *px_p = DIP_TO_STATE(rpdip); 1472 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1473 caddr_t pcitool_addr = pxu_p->pcitool_addr; 1474 caddr_t errlog_addr = 1475 (caddr_t)CSR_FR(csr_base, DMCINT_ODCD_ERROR_LOG, ADDRESS); 1476 1477 return (pcitool_addr == errlog_addr); 1478 } 1479 1480 /* 1481 * JBC Dmcint ODCD errer handling for errors which are forgivable during a safe 1482 * access. (This will be most likely be a PCItool access.) If not a safe 1483 * access context, treat like jbc_dmcint_odcd. 1484 * Unmapped PIO read error: pio:read:M:nonfatal 1485 * Unmapped PIO write error: pio:write:M:nonfatal 1486 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1487 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1488 */ 1489 /* ARGSUSED */ 1490 int 1491 px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base, 1492 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1493 px_err_bit_desc_t *err_bit_descr) 1494 { 1495 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1496 1497 if (!pri) 1498 return (px_err_panic_handle(rpdip, csr_base, derr, 1499 err_reg_descr, err_bit_descr)); 1500 /* 1501 * Got an error which is forgivable during a PCItool access. 1502 * 1503 * Don't do handler check since the error may otherwise be unfairly 1504 * attributed to a device. Just return. 1505 * 1506 * Note: There is a hole here in that a legitimate error can come in 1507 * while a PCItool access is in play and be forgiven. This is possible 1508 * though not likely. 1509 */ 1510 if ((derr->fme_flag != DDI_FM_ERR_UNEXPECTED) && 1511 (px_jbc_pcitool_addr_match(rpdip, csr_base))) 1512 return (px_err_protected_handle(rpdip, csr_base, derr, 1513 err_reg_descr, err_bit_descr)); 1514 1515 return (px_err_jbc_dmcint_odcd_handle(rpdip, csr_base, derr, 1516 err_reg_descr, err_bit_descr)); 1517 } 1518 1519 /* JBC Dmcint IDC */ 1520 PX_ERPT_SEND_DEC(jbc_idc) 1521 { 1522 char buf[FM_MAX_CLASS]; 1523 boolean_t pri = PX_ERR_IS_PRI(bit); 1524 1525 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1526 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1527 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1528 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1529 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1530 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1531 FIRE_JBC_IE, DATA_TYPE_UINT64, 1532 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1533 FIRE_JBC_IS, DATA_TYPE_UINT64, 1534 ss_reg, 1535 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1536 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1537 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1538 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1539 NULL); 1540 1541 return (PX_NO_PANIC); 1542 } 1543 1544 /* JBC CSR */ 1545 PX_ERPT_SEND_DEC(jbc_csr) 1546 { 1547 char buf[FM_MAX_CLASS]; 1548 boolean_t pri = PX_ERR_IS_PRI(bit); 1549 1550 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1551 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1552 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1553 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1554 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1555 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1556 FIRE_JBC_IE, DATA_TYPE_UINT64, 1557 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1558 FIRE_JBC_IS, DATA_TYPE_UINT64, 1559 ss_reg, 1560 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1561 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1562 "jbc-error-reg", DATA_TYPE_UINT64, 1563 CSR_XR(csr_base, CSR_ERROR_LOG), 1564 NULL); 1565 1566 return (PX_NO_PANIC); 1567 } 1568 1569 /* DMC IMU RDS */ 1570 PX_ERPT_SEND_DEC(imu_rds) 1571 { 1572 char buf[FM_MAX_CLASS]; 1573 boolean_t pri = PX_ERR_IS_PRI(bit); 1574 1575 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1576 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1577 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1578 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1579 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1580 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1581 FIRE_IMU_IE, DATA_TYPE_UINT64, 1582 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1583 FIRE_IMU_IS, DATA_TYPE_UINT64, 1584 ss_reg, 1585 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1586 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1587 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1588 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1589 NULL); 1590 1591 return (PX_NO_PANIC); 1592 } 1593 1594 /* handle EQ overflow */ 1595 /* ARGSUSED */ 1596 int 1597 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1598 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1599 px_err_bit_desc_t *err_bit_descr) 1600 { 1601 px_t *px_p = DIP_TO_STATE(rpdip); 1602 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1603 int err = px_err_check_eq(rpdip); 1604 1605 if ((err == PX_PANIC) && (pxu_p->cpr_flag == PX_NOT_CPR)) { 1606 return (px_err_panic_handle(rpdip, csr_base, derr, 1607 err_reg_descr, err_bit_descr)); 1608 } else { 1609 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1610 err_reg_descr, err_bit_descr)); 1611 } 1612 } 1613 1614 /* DMC IMU SCS */ 1615 PX_ERPT_SEND_DEC(imu_scs) 1616 { 1617 char buf[FM_MAX_CLASS]; 1618 boolean_t pri = PX_ERR_IS_PRI(bit); 1619 1620 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1621 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1622 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1623 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1624 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1625 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1626 FIRE_IMU_IE, DATA_TYPE_UINT64, 1627 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1628 FIRE_IMU_IS, DATA_TYPE_UINT64, 1629 ss_reg, 1630 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1631 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1632 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1633 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1634 NULL); 1635 1636 return (PX_NO_PANIC); 1637 } 1638 1639 /* DMC IMU */ 1640 PX_ERPT_SEND_DEC(imu) 1641 { 1642 char buf[FM_MAX_CLASS]; 1643 boolean_t pri = PX_ERR_IS_PRI(bit); 1644 1645 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1646 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1647 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1648 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1649 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1650 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1651 FIRE_IMU_IE, DATA_TYPE_UINT64, 1652 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1653 FIRE_IMU_IS, DATA_TYPE_UINT64, 1654 ss_reg, 1655 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1656 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1657 NULL); 1658 1659 return (PX_NO_PANIC); 1660 } 1661 1662 /* DMC MMU TFAR/TFSR */ 1663 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1664 { 1665 char buf[FM_MAX_CLASS]; 1666 boolean_t pri = PX_ERR_IS_PRI(bit); 1667 px_t *px_p = DIP_TO_STATE(rpdip); 1668 pcie_req_id_t fault_bdf = 0; 1669 uint16_t s_status = 0; 1670 1671 if (pri) { 1672 fault_bdf = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS) 1673 & (MMU_TRANSLATION_FAULT_STATUS_ID_MASK << 1674 MMU_TRANSLATION_FAULT_STATUS_ID); 1675 s_status = PCI_STAT_S_TARG_AB; 1676 1677 /* Only PIO Fault Addresses are valid, this is DMA */ 1678 (void) px_rp_en_q(px_p, fault_bdf, NULL, s_status); 1679 } 1680 1681 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1682 1683 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1684 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1685 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1686 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1687 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1688 FIRE_MMU_IE, DATA_TYPE_UINT64, 1689 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1690 FIRE_MMU_IS, DATA_TYPE_UINT64, 1691 ss_reg, 1692 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1693 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1694 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1695 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1696 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1697 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1698 NULL); 1699 1700 return (PX_NO_PANIC); 1701 } 1702 1703 /* DMC MMU */ 1704 PX_ERPT_SEND_DEC(mmu) 1705 { 1706 char buf[FM_MAX_CLASS]; 1707 boolean_t pri = PX_ERR_IS_PRI(bit); 1708 1709 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1710 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1711 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1712 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1713 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1714 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1715 FIRE_MMU_IE, DATA_TYPE_UINT64, 1716 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1717 FIRE_MMU_IS, DATA_TYPE_UINT64, 1718 ss_reg, 1719 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1720 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1721 NULL); 1722 1723 return (PX_NO_PANIC); 1724 } 1725 1726 /* 1727 * IMU function to handle all Received but Not Enabled errors. 1728 * 1729 * These errors are due to transactions modes in which the PX driver was not 1730 * setup to be able to do. If possible, inform the driver that their DMA has 1731 * failed by marking their DMA handle as failed, but do not panic the system. 1732 * Most likely the address is not valid, as Fire wasn't setup to handle them in 1733 * the first place. 1734 * 1735 * These errors are not retryable, unless the PX mode has changed, otherwise the 1736 * same error will occur again. 1737 */ 1738 int 1739 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1740 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1741 px_err_bit_desc_t *err_bit_descr) 1742 { 1743 pcie_req_id_t bdf; 1744 1745 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1746 goto done; 1747 1748 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); 1749 (void) pf_hdl_lookup(rpdip, derr->fme_ena, PF_DMA_ADDR, NULL, 1750 bdf); 1751 1752 done: 1753 return (px_err_no_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1754 err_bit_descr)); 1755 } 1756 1757 /* 1758 * IMU function to handle all invalid address errors. 1759 * 1760 * These errors are due to transactions in which the address is not recognized. 1761 * If possible, inform the driver that all DMAs have failed by marking their DMA 1762 * handles. Fire should not panic the system, it'll be up to the driver to 1763 * panic. The address logged is invalid. 1764 * 1765 * These errors are not retryable since retrying the same transaction with the 1766 * same invalid address will result in the same error. 1767 */ 1768 /* ARGSUSED */ 1769 int 1770 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1771 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1772 px_err_bit_desc_t *err_bit_descr) 1773 { 1774 pcie_req_id_t bdf; 1775 1776 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1777 goto done; 1778 1779 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); 1780 (void) pf_hdl_lookup(rpdip, derr->fme_ena, PF_DMA_ADDR, NULL, 1781 bdf); 1782 1783 done: 1784 return (px_err_no_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1785 err_bit_descr)); 1786 } 1787 1788 /* 1789 * IMU function to handle normal transactions that encounter a parity error. 1790 * 1791 * These errors are due to transactions that enouter a parity error. If 1792 * possible, inform the driver that their DMA have failed and that they should 1793 * retry. If Fire is unable to contact the leaf driver, panic the system. 1794 * Otherwise, it'll be up to the device to determine is this is a panicable 1795 * error. 1796 */ 1797 /* ARGSUSED */ 1798 int 1799 px_err_mmu_parity_handle(dev_info_t *rpdip, caddr_t csr_base, 1800 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1801 px_err_bit_desc_t *err_bit_descr) 1802 { 1803 uint64_t mmu_tfa; 1804 pcie_req_id_t bdf; 1805 int status = DDI_FM_UNKNOWN; 1806 1807 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1808 goto done; 1809 1810 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1811 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); 1812 status = pf_hdl_lookup(rpdip, derr->fme_ena, PF_DMA_ADDR, 1813 (uint32_t)mmu_tfa, bdf); 1814 1815 done: 1816 if (status == DDI_FM_UNKNOWN) 1817 return (px_err_panic_handle(rpdip, csr_base, derr, 1818 err_reg_descr, err_bit_descr)); 1819 else 1820 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1821 err_reg_descr, err_bit_descr)); 1822 } 1823 1824 /* 1825 * wuc/ruc event - Mark the handle of the failed PIO access. Return "no_panic" 1826 */ 1827 /* ARGSUSED */ 1828 int 1829 px_err_wuc_ruc_handle(dev_info_t *rpdip, caddr_t csr_base, 1830 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1831 px_err_bit_desc_t *err_bit_descr) 1832 { 1833 px_t *px_p = DIP_TO_STATE(rpdip); 1834 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1835 uint64_t data; 1836 uint32_t addr, hdr; 1837 pcie_tlp_hdr_t *tlp; 1838 int sts = PF_HDL_NOTFOUND; 1839 1840 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1841 goto done; 1842 1843 data = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG); 1844 hdr = (uint32_t)(data >> 32); 1845 tlp = (pcie_tlp_hdr_t *)&hdr; 1846 data = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG); 1847 addr = (uint32_t)(data >> 32); 1848 1849 switch (tlp->type) { 1850 case PCIE_TLP_TYPE_IO: 1851 case PCIE_TLP_TYPE_MEM: 1852 case PCIE_TLP_TYPE_MEMLK: 1853 sts = pf_hdl_lookup(rpdip, derr->fme_ena, PF_PIO_ADDR, 1854 addr, NULL); 1855 break; 1856 case PCIE_TLP_TYPE_CFG0: 1857 case PCIE_TLP_TYPE_CFG1: 1858 sts = pf_hdl_lookup(rpdip, derr->fme_ena, PF_CFG_ADDR, 1859 addr, (addr >> 16)); 1860 break; 1861 } 1862 1863 done: 1864 if ((sts == PF_HDL_NOTFOUND) && (pxu_p->cpr_flag == PX_NOT_CPR)) 1865 return (px_err_protected_handle(rpdip, csr_base, derr, 1866 err_reg_descr, err_bit_descr)); 1867 1868 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1869 err_reg_descr, err_bit_descr)); 1870 } 1871 1872 /* 1873 * TLU LUP event - if caused by power management activity, then it is expected. 1874 * In all other cases, it is an error. 1875 */ 1876 /* ARGSUSED */ 1877 int 1878 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1879 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1880 px_err_bit_desc_t *err_bit_descr) 1881 { 1882 px_t *px_p = DIP_TO_STATE(rpdip); 1883 1884 /* 1885 * power management code is currently the only segment that sets 1886 * px_lup_pending to indicate its expectation for a healthy LUP 1887 * event. For all other occasions, LUP event should be flaged as 1888 * error condition. 1889 */ 1890 return ((atomic_cas_32(&px_p->px_lup_pending, 1, 0) == 0) ? 1891 PX_NO_PANIC : PX_EXPECTED); 1892 } 1893 1894 /* 1895 * TLU LDN event - if caused by power management activity, then it is expected. 1896 * In all other cases, it is an error. 1897 */ 1898 /* ARGSUSED */ 1899 int 1900 px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 1901 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1902 px_err_bit_desc_t *err_bit_descr) 1903 { 1904 px_t *px_p = DIP_TO_STATE(rpdip); 1905 return ((px_p->px_pm_flags & PX_LDN_EXPECTED) ? PX_EXPECTED : 1906 PX_NO_PANIC); 1907 } 1908 1909 /* PEC ILU none - see io erpt doc, section 3.1 */ 1910 PX_ERPT_SEND_DEC(pec_ilu) 1911 { 1912 char buf[FM_MAX_CLASS]; 1913 boolean_t pri = PX_ERR_IS_PRI(bit); 1914 1915 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1916 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1917 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1918 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1919 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1920 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1921 FIRE_ILU_IE, DATA_TYPE_UINT64, 1922 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1923 FIRE_ILU_IS, DATA_TYPE_UINT64, 1924 ss_reg, 1925 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1926 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1927 NULL); 1928 1929 return (PX_NO_PANIC); 1930 } 1931 1932 /* PCIEX UE Errors */ 1933 /* ARGSUSED */ 1934 int 1935 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1936 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1937 px_err_bit_desc_t *err_bit_descr) 1938 { 1939 px_err_pcie_t regs = {0}; 1940 uint32_t err_bit; 1941 int err; 1942 uint64_t log; 1943 1944 if (err_bit_descr->bit < 32) { 1945 err_bit = (uint32_t)BITMASK(err_bit_descr->bit); 1946 regs.ue_reg = err_bit; 1947 regs.primary_ue = err_bit; 1948 1949 /* 1950 * Log the Received Log for PTLP and UR. The PTLP most likely 1951 * is a poisoned completion. The original transaction will be 1952 * logged inthe Transmit Log. 1953 */ 1954 if (err_bit & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_UR)) { 1955 log = CSR_XR(csr_base, 1956 TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG); 1957 regs.rx_hdr1 = (uint32_t)(log >> 32); 1958 regs.rx_hdr2 = (uint32_t)(log && 0xFFFFFFFF); 1959 1960 log = CSR_XR(csr_base, 1961 TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG); 1962 regs.rx_hdr3 = (uint32_t)(log >> 32); 1963 regs.rx_hdr4 = (uint32_t)(log && 0xFFFFFFFF); 1964 } 1965 1966 if (err_bit & (PCIE_AER_UCE_PTLP)) { 1967 log = CSR_XR(csr_base, 1968 TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG); 1969 regs.tx_hdr1 = (uint32_t)(log >> 32); 1970 regs.tx_hdr2 = (uint32_t)(log && 0xFFFFFFFF); 1971 1972 log = CSR_XR(csr_base, 1973 TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG); 1974 regs.tx_hdr3 = (uint32_t)(log >> 32); 1975 regs.tx_hdr4 = (uint32_t)(log && 0xFFFFFFFF); 1976 } 1977 } else { 1978 regs.ue_reg = (uint32_t)BITMASK(err_bit_descr->bit - 32); 1979 } 1980 1981 err = px_err_check_pcie(rpdip, derr, ®s); 1982 1983 if (err & PX_PANIC) { 1984 return (px_err_panic_handle(rpdip, csr_base, derr, 1985 err_reg_descr, err_bit_descr)); 1986 } else { 1987 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1988 err_reg_descr, err_bit_descr)); 1989 } 1990 } 1991 1992 /* PCI-E Uncorrectable Errors */ 1993 PX_ERPT_SEND_DEC(pciex_rx_ue) 1994 { 1995 char buf[FM_MAX_CLASS]; 1996 boolean_t pri = PX_ERR_IS_PRI(bit); 1997 1998 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1999 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2000 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2001 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2002 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2003 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2004 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2005 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2006 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2007 ss_reg, 2008 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2009 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2010 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2011 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2012 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2013 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2014 NULL); 2015 2016 return (PX_NO_PANIC); 2017 } 2018 2019 /* PCI-E Uncorrectable Errors */ 2020 PX_ERPT_SEND_DEC(pciex_tx_ue) 2021 { 2022 char buf[FM_MAX_CLASS]; 2023 boolean_t pri = PX_ERR_IS_PRI(bit); 2024 2025 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2026 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2027 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2028 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2029 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2030 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2031 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2032 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2033 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2034 ss_reg, 2035 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2036 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2037 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2038 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2039 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2040 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2041 NULL); 2042 2043 return (PX_NO_PANIC); 2044 } 2045 2046 /* PCI-E Uncorrectable Errors */ 2047 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 2048 { 2049 char buf[FM_MAX_CLASS]; 2050 boolean_t pri = PX_ERR_IS_PRI(bit); 2051 2052 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2053 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2054 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2055 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2056 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2057 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2058 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2059 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2060 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2061 ss_reg, 2062 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2063 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2064 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2065 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2066 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2067 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2068 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2069 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2070 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2071 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2072 NULL); 2073 2074 return (PX_NO_PANIC); 2075 } 2076 2077 /* PCI-E Uncorrectable Errors */ 2078 PX_ERPT_SEND_DEC(pciex_ue) 2079 { 2080 char buf[FM_MAX_CLASS]; 2081 boolean_t pri = PX_ERR_IS_PRI(bit); 2082 2083 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2084 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2085 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2086 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2087 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2088 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2089 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2090 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2091 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2092 ss_reg, 2093 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2094 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2095 NULL); 2096 2097 return (PX_NO_PANIC); 2098 } 2099 2100 /* PCIEX UE Errors */ 2101 /* ARGSUSED */ 2102 int 2103 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 2104 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2105 px_err_bit_desc_t *err_bit_descr) 2106 { 2107 px_err_pcie_t regs = {0}; 2108 int err; 2109 2110 if (err_bit_descr->bit < 32) 2111 regs.ce_reg = (uint32_t)BITMASK(err_bit_descr->bit); 2112 else 2113 regs.ce_reg = (uint32_t)BITMASK(err_bit_descr->bit - 32); 2114 2115 err = px_err_check_pcie(rpdip, derr, ®s); 2116 2117 if (err & PX_PANIC) { 2118 return (px_err_panic_handle(rpdip, csr_base, derr, 2119 err_reg_descr, err_bit_descr)); 2120 } else { 2121 return (px_err_no_panic_handle(rpdip, csr_base, derr, 2122 err_reg_descr, err_bit_descr)); 2123 } 2124 } 2125 2126 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 2127 PX_ERPT_SEND_DEC(pciex_ce) 2128 { 2129 char buf[FM_MAX_CLASS]; 2130 boolean_t pri = PX_ERR_IS_PRI(bit); 2131 2132 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2133 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2134 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2135 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2136 FIRE_TLU_CELE, DATA_TYPE_UINT64, 2137 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 2138 FIRE_TLU_CIE, DATA_TYPE_UINT64, 2139 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 2140 FIRE_TLU_CIS, DATA_TYPE_UINT64, 2141 ss_reg, 2142 FIRE_TLU_CESS, DATA_TYPE_UINT64, 2143 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 2144 NULL); 2145 2146 return (PX_NO_PANIC); 2147 } 2148 2149 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 2150 PX_ERPT_SEND_DEC(pciex_rx_oe) 2151 { 2152 char buf[FM_MAX_CLASS]; 2153 boolean_t pri = PX_ERR_IS_PRI(bit); 2154 2155 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2156 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2157 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2158 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2159 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2160 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2161 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2162 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2163 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2164 ss_reg, 2165 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2166 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2167 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2168 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2169 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2170 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2171 NULL); 2172 2173 return (PX_NO_PANIC); 2174 } 2175 2176 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 2177 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 2178 { 2179 char buf[FM_MAX_CLASS]; 2180 boolean_t pri = PX_ERR_IS_PRI(bit); 2181 px_t *px_p = DIP_TO_STATE(rpdip); 2182 uint32_t trans_type, fault_addr = 0; 2183 uint64_t rx_h1, rx_h2, tx_h1, tx_h2; 2184 uint16_t s_status; 2185 int sts; 2186 pcie_req_id_t fault_bdf = 0; 2187 pcie_cpl_t *cpl; 2188 pf_data_t pf_data = {0}; 2189 2190 rx_h1 = CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG); 2191 rx_h2 = CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG); 2192 tx_h1 = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG); 2193 tx_h2 = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG); 2194 2195 if ((bit == TLU_OTHER_EVENT_STATUS_SET_RUC_P) || 2196 (bit == TLU_OTHER_EVENT_STATUS_SET_WUC_P)) { 2197 pf_data.aer_h0 = (uint32_t)(rx_h1 >> 32); 2198 pf_data.aer_h1 = (uint32_t)rx_h1; 2199 pf_data.aer_h2 = (uint32_t)(rx_h2 >> 32); 2200 pf_data.aer_h3 = (uint32_t)rx_h2; 2201 2202 /* get completer bdf (fault bdf) from rx logs */ 2203 cpl = (pcie_cpl_t *)&pf_data.aer_h1; 2204 fault_bdf = cpl->cid; 2205 2206 /* Figure out if UR/CA from rx logs */ 2207 if (cpl->status == PCIE_CPL_STS_UR) 2208 s_status = PCI_STAT_R_MAST_AB; 2209 else if (cpl->status == PCIE_CPL_STS_CA) 2210 s_status = PCI_STAT_R_TARG_AB; 2211 2212 2213 pf_data.aer_h0 = (uint32_t)(tx_h1 >> 32); 2214 pf_data.aer_h1 = (uint32_t)tx_h1; 2215 pf_data.aer_h2 = (uint32_t)(tx_h2 >> 32); 2216 pf_data.aer_h3 = (uint32_t)tx_h2; 2217 2218 /* get fault addr from tx logs */ 2219 sts = pf_tlp_decode(rpdip, &pf_data, 0, &fault_addr, 2220 &trans_type); 2221 2222 if (sts == DDI_SUCCESS) 2223 (void) px_rp_en_q(px_p, fault_bdf, fault_addr, 2224 s_status); 2225 } 2226 2227 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2228 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2229 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2230 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2231 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2232 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2233 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2234 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2235 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2236 ss_reg, 2237 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2238 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2239 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, rx_h1, 2240 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, rx_h2, 2241 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, tx_h1, 2242 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, tx_h2, 2243 NULL); 2244 2245 return (PX_NO_PANIC); 2246 } 2247 2248 /* TLU Other Event - see io erpt doc, section 3.9 */ 2249 PX_ERPT_SEND_DEC(pciex_oe) 2250 { 2251 char buf[FM_MAX_CLASS]; 2252 boolean_t pri = PX_ERR_IS_PRI(bit); 2253 2254 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2255 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2256 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2257 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2258 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2259 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2260 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2261 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2262 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2263 ss_reg, 2264 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2265 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2266 NULL); 2267 2268 return (PX_NO_PANIC); 2269 } 2270