1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * PCI nexus driver interface 29 */ 30 31 #include <sys/types.h> 32 #include <sys/conf.h> /* nulldev */ 33 #include <sys/stat.h> /* devctl */ 34 #include <sys/kmem.h> 35 #include <sys/async.h> /* ecc_flt for pci_ecc.h */ 36 #include <sys/sunddi.h> 37 #include <sys/sunndi.h> 38 #include <sys/ndifm.h> 39 #include <sys/ontrap.h> 40 #include <sys/ddi_impldefs.h> 41 #include <sys/ddi_subrdefs.h> 42 #include <sys/epm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include <sys/pci/pci_tools_ext.h> 45 #include <sys/spl.h> 46 #include <sys/pci/pci_obj.h> 47 48 /*LINTLIBRARY*/ 49 50 /* 51 * function prototype for hotplug routine: 52 */ 53 static void 54 pci_init_hotplug(struct pci *); 55 56 /* 57 * function prototypes for dev ops routines: 58 */ 59 static int pci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 60 static int pci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 61 static int pci_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 62 void *arg, void **result); 63 static int pci_ctlops_poke(pci_t *pci_p, peekpoke_ctlops_t *in_args); 64 static int pci_ctlops_peek(pci_t *pci_p, peekpoke_ctlops_t *in_args, 65 void *result); 66 static off_t get_reg_set_size(dev_info_t *child, int rnumber); 67 68 /* 69 * bus ops and dev ops structures: 70 */ 71 static struct bus_ops pci_bus_ops = { 72 BUSO_REV, 73 pci_map, 74 0, 75 0, 76 0, 77 i_ddi_map_fault, 78 pci_dma_setup, 79 pci_dma_allochdl, 80 pci_dma_freehdl, 81 pci_dma_bindhdl, 82 pci_dma_unbindhdl, 83 pci_dma_sync, 84 pci_dma_win, 85 pci_dma_ctlops, 86 pci_ctlops, 87 ddi_bus_prop_op, 88 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 89 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 90 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 91 ndi_post_event, /* (*bus_post_event)(); */ 92 NULL, /* (*bus_intr_ctl)(); */ 93 NULL, /* (*bus_config)(); */ 94 NULL, /* (*bus_unconfig)(); */ 95 pci_fm_init_child, /* (*bus_fm_init)(); */ 96 NULL, /* (*bus_fm_fini)(); */ 97 pci_bus_enter, /* (*bus_fm_access_enter)(); */ 98 pci_bus_exit, /* (*bus_fm_access_fini)(); */ 99 NULL, /* (*bus_power)(); */ 100 pci_intr_ops /* (*bus_intr_op)(); */ 101 }; 102 103 extern struct cb_ops pci_cb_ops; 104 105 static struct dev_ops pci_ops = { 106 DEVO_REV, 107 0, 108 pci_info, 109 nulldev, 110 0, 111 pci_attach, 112 pci_detach, 113 nodev, 114 &pci_cb_ops, 115 &pci_bus_ops, 116 0, 117 ddi_quiesce_not_supported, /* devo_quiesce */ 118 }; 119 120 /* 121 * module definitions: 122 */ 123 #include <sys/modctl.h> 124 extern struct mod_ops mod_driverops; 125 126 static struct modldrv modldrv = { 127 &mod_driverops, /* Type of module - driver */ 128 "PCI Bus nexus driver", /* Name of module. */ 129 &pci_ops, /* driver ops */ 130 }; 131 132 static struct modlinkage modlinkage = { 133 MODREV_1, (void *)&modldrv, NULL 134 }; 135 136 /* 137 * driver global data: 138 */ 139 void *per_pci_state; /* per-pbm soft state pointer */ 140 void *per_pci_common_state; /* per-psycho soft state pointer */ 141 kmutex_t pci_global_mutex; /* attach/detach common struct lock */ 142 errorq_t *pci_ecc_queue = NULL; /* per-system ecc handling queue */ 143 extern errorq_t *pci_target_queue; 144 struct cb_ops *pcihp_ops = NULL; /* hotplug module cb ops */ 145 146 extern void pci_child_cfg_save(dev_info_t *dip); 147 extern void pci_child_cfg_restore(dev_info_t *dip); 148 149 int 150 _init(void) 151 { 152 int e; 153 154 /* 155 * Initialize per-pci bus soft state pointer. 156 */ 157 e = ddi_soft_state_init(&per_pci_state, sizeof (pci_t), 1); 158 if (e != 0) 159 return (e); 160 161 /* 162 * Initialize per-psycho soft state pointer. 163 */ 164 e = ddi_soft_state_init(&per_pci_common_state, 165 sizeof (pci_common_t), 1); 166 if (e != 0) { 167 ddi_soft_state_fini(&per_pci_state); 168 return (e); 169 } 170 171 /* 172 * Initialize global mutexes. 173 */ 174 mutex_init(&pci_global_mutex, NULL, MUTEX_DRIVER, NULL); 175 pci_reloc_init(); 176 177 /* 178 * Create the performance kstats. 179 */ 180 pci_kstat_init(); 181 182 /* 183 * Install the module. 184 */ 185 e = mod_install(&modlinkage); 186 if (e != 0) { 187 ddi_soft_state_fini(&per_pci_state); 188 ddi_soft_state_fini(&per_pci_common_state); 189 mutex_destroy(&pci_global_mutex); 190 } 191 return (e); 192 } 193 194 int 195 _fini(void) 196 { 197 int e; 198 199 /* 200 * Remove the module. 201 */ 202 e = mod_remove(&modlinkage); 203 if (e != 0) 204 return (e); 205 206 /* 207 * Destroy pci_ecc_queue, and set it to NULL. 208 */ 209 if (pci_ecc_queue) 210 errorq_destroy(pci_ecc_queue); 211 212 pci_ecc_queue = NULL; 213 214 /* 215 * Destroy pci_target_queue, and set it to NULL. 216 */ 217 if (pci_target_queue) 218 errorq_destroy(pci_target_queue); 219 220 pci_target_queue = NULL; 221 222 /* 223 * Destroy the performance kstats. 224 */ 225 pci_kstat_fini(); 226 227 /* 228 * Free the per-pci and per-psycho soft state info and destroy 229 * mutex for per-psycho soft state. 230 */ 231 ddi_soft_state_fini(&per_pci_state); 232 ddi_soft_state_fini(&per_pci_common_state); 233 mutex_destroy(&pci_global_mutex); 234 pci_reloc_fini(); 235 return (e); 236 } 237 238 int 239 _info(struct modinfo *modinfop) 240 { 241 return (mod_info(&modlinkage, modinfop)); 242 } 243 244 /*ARGSUSED*/ 245 static int 246 pci_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 247 { 248 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor((dev_t)arg)); 249 pci_t *pci_p = get_pci_soft_state(instance); 250 251 /* allow hotplug to deal with ones it manages */ 252 if (pci_p && (pci_p->hotplug_capable == B_TRUE)) 253 return (pcihp_info(dip, infocmd, arg, result)); 254 255 /* non-hotplug or not attached */ 256 switch (infocmd) { 257 case DDI_INFO_DEVT2INSTANCE: 258 *result = (void *)(uintptr_t)instance; 259 return (DDI_SUCCESS); 260 261 case DDI_INFO_DEVT2DEVINFO: 262 if (pci_p == NULL) 263 return (DDI_FAILURE); 264 *result = (void *)pci_p->pci_dip; 265 return (DDI_SUCCESS); 266 267 default: 268 return (DDI_FAILURE); 269 } 270 } 271 272 273 /* device driver entry points */ 274 /* 275 * attach entry point: 276 */ 277 static int 278 pci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 279 { 280 pci_t *pci_p; /* per bus state pointer */ 281 int instance = ddi_get_instance(dip); 282 283 switch (cmd) { 284 case DDI_ATTACH: 285 DEBUG0(DBG_ATTACH, dip, "DDI_ATTACH\n"); 286 287 /* 288 * Allocate and get the per-pci soft state structure. 289 */ 290 if (alloc_pci_soft_state(instance) != DDI_SUCCESS) { 291 cmn_err(CE_WARN, "%s%d: can't allocate pci state", 292 ddi_driver_name(dip), instance); 293 goto err_bad_pci_softstate; 294 } 295 pci_p = get_pci_soft_state(instance); 296 pci_p->pci_dip = dip; 297 mutex_init(&pci_p->pci_mutex, NULL, MUTEX_DRIVER, NULL); 298 pci_p->pci_soft_state = PCI_SOFT_STATE_CLOSED; 299 pci_p->pci_open_count = 0; 300 301 /* 302 * Get key properties of the pci bridge node and 303 * determine it's type (psycho, schizo, etc ...). 304 */ 305 if (get_pci_properties(pci_p, dip) == DDI_FAILURE) 306 goto err_bad_pci_prop; 307 308 /* 309 * Map in the registers. 310 */ 311 if (map_pci_registers(pci_p, dip) == DDI_FAILURE) 312 goto err_bad_reg_prop; 313 314 if (pci_obj_setup(pci_p) != DDI_SUCCESS) 315 goto err_bad_objs; 316 317 /* 318 * If this PCI leaf has hotplug and this platform 319 * loads hotplug modules then initialize the 320 * hotplug framework. 321 */ 322 pci_init_hotplug(pci_p); 323 324 /* 325 * Create the "devctl" node for hotplug support. 326 * For non-hotplug bus, we still need ":devctl" to 327 * support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls. 328 */ 329 if (pci_p->hotplug_capable == B_FALSE) { 330 if (ddi_create_minor_node(dip, "devctl", S_IFCHR, 331 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 332 DDI_NT_NEXUS, 0) != DDI_SUCCESS) 333 goto err_bad_devctl_node; 334 } 335 336 /* 337 * Create pcitool nodes for register access and interrupt 338 * routing. 339 */ 340 if (pcitool_init(dip) != DDI_SUCCESS) { 341 goto err_bad_pcitool_nodes; 342 } 343 344 /* 345 * Due to unresolved hardware issues, disable PCIPM until 346 * the problem is fully understood. 347 * 348 * pci_pwr_setup(pci_p, dip); 349 */ 350 351 ddi_report_dev(dip); 352 353 pci_p->pci_state = PCI_ATTACHED; 354 DEBUG0(DBG_ATTACH, dip, "attach success\n"); 355 break; 356 357 err_bad_pcitool_nodes: 358 if (pci_p->hotplug_capable == B_FALSE) 359 ddi_remove_minor_node(dip, "devctl"); 360 else 361 (void) pcihp_uninit(dip); 362 err_bad_devctl_node: 363 pci_obj_destroy(pci_p); 364 err_bad_objs: 365 unmap_pci_registers(pci_p); 366 err_bad_reg_prop: 367 free_pci_properties(pci_p); 368 err_bad_pci_prop: 369 mutex_destroy(&pci_p->pci_mutex); 370 free_pci_soft_state(instance); 371 err_bad_pci_softstate: 372 return (DDI_FAILURE); 373 374 case DDI_RESUME: 375 DEBUG0(DBG_ATTACH, dip, "DDI_RESUME\n"); 376 377 /* 378 * Make sure the Psycho control registers and IOMMU 379 * are configured properly. 380 */ 381 pci_p = get_pci_soft_state(instance); 382 mutex_enter(&pci_p->pci_mutex); 383 384 /* 385 * Make sure this instance has been suspended. 386 */ 387 if (pci_p->pci_state != PCI_SUSPENDED) { 388 DEBUG0(DBG_ATTACH, dip, "instance NOT suspended\n"); 389 mutex_exit(&pci_p->pci_mutex); 390 return (DDI_FAILURE); 391 } 392 pci_obj_resume(pci_p); 393 pci_p->pci_state = PCI_ATTACHED; 394 395 pci_child_cfg_restore(dip); 396 397 mutex_exit(&pci_p->pci_mutex); 398 break; 399 400 default: 401 DEBUG0(DBG_ATTACH, dip, "unsupported attach op\n"); 402 return (DDI_FAILURE); 403 } 404 405 return (DDI_SUCCESS); 406 } 407 408 /* 409 * detach entry point: 410 */ 411 static int 412 pci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 413 { 414 int instance = ddi_get_instance(dip); 415 pci_t *pci_p = get_pci_soft_state(instance); 416 417 /* 418 * Make sure we are currently attached 419 */ 420 if (pci_p->pci_state != PCI_ATTACHED) { 421 DEBUG0(DBG_ATTACH, dip, "failed - instance not attached\n"); 422 return (DDI_FAILURE); 423 } 424 425 mutex_enter(&pci_p->pci_mutex); 426 427 switch (cmd) { 428 case DDI_DETACH: 429 DEBUG0(DBG_DETACH, dip, "DDI_DETACH\n"); 430 431 if (pci_p->hotplug_capable == B_TRUE) 432 if (pcihp_uninit(dip) == DDI_FAILURE) { 433 mutex_exit(&pci_p->pci_mutex); 434 return (DDI_FAILURE); 435 } 436 437 pcitool_uninit(dip); 438 439 pci_obj_destroy(pci_p); 440 441 /* 442 * Free the pci soft state structure and the rest of the 443 * resources it's using. 444 */ 445 free_pci_properties(pci_p); 446 unmap_pci_registers(pci_p); 447 mutex_exit(&pci_p->pci_mutex); 448 mutex_destroy(&pci_p->pci_mutex); 449 free_pci_soft_state(instance); 450 451 /* Free the interrupt-priorities prop if we created it. */ 452 { 453 int len; 454 455 if (ddi_getproplen(DDI_DEV_T_ANY, dip, 456 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS, 457 "interrupt-priorities", &len) == DDI_PROP_SUCCESS) 458 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 459 "interrupt-priorities"); 460 } 461 return (DDI_SUCCESS); 462 463 case DDI_SUSPEND: 464 pci_child_cfg_save(dip); 465 pci_obj_suspend(pci_p); 466 pci_p->pci_state = PCI_SUSPENDED; 467 468 mutex_exit(&pci_p->pci_mutex); 469 return (DDI_SUCCESS); 470 471 default: 472 DEBUG0(DBG_DETACH, dip, "unsupported detach op\n"); 473 mutex_exit(&pci_p->pci_mutex); 474 return (DDI_FAILURE); 475 } 476 } 477 478 479 /* bus driver entry points */ 480 481 /* 482 * bus map entry point: 483 * 484 * if map request is for an rnumber 485 * get the corresponding regspec from device node 486 * build a new regspec in our parent's format 487 * build a new map_req with the new regspec 488 * call up the tree to complete the mapping 489 */ 490 int 491 pci_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 492 off_t off, off_t len, caddr_t *addrp) 493 { 494 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 495 struct regspec p_regspec; 496 ddi_map_req_t p_mapreq; 497 int reglen, rval, r_no; 498 pci_regspec_t reloc_reg, *rp = &reloc_reg; 499 500 DEBUG2(DBG_MAP, dip, "rdip=%s%d:", 501 ddi_driver_name(rdip), ddi_get_instance(rdip)); 502 503 if (mp->map_flags & DDI_MF_USER_MAPPING) 504 return (DDI_ME_UNIMPLEMENTED); 505 506 switch (mp->map_type) { 507 case DDI_MT_REGSPEC: 508 reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */ 509 break; 510 511 case DDI_MT_RNUMBER: 512 r_no = mp->map_obj.rnumber; 513 DEBUG1(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no); 514 515 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 516 "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) 517 return (DDI_ME_RNUMBER_RANGE); 518 519 if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) { 520 kmem_free(rp, reglen); 521 return (DDI_ME_RNUMBER_RANGE); 522 } 523 rp += r_no; 524 break; 525 526 default: 527 return (DDI_ME_INVAL); 528 } 529 DEBUG0(DBG_MAP | DBG_CONT, dip, "\n"); 530 531 /* use "assigned-addresses" to relocate regspec within pci space */ 532 if (rval = pci_reloc_reg(dip, rdip, pci_p, rp)) 533 goto done; 534 535 if (len) /* adjust regspec according to mapping request */ 536 rp->pci_size_low = len; 537 rp->pci_phys_low += off; 538 539 /* use "ranges" to translate relocated pci regspec into parent space */ 540 if (rval = pci_xlate_reg(pci_p, rp, &p_regspec)) 541 goto done; 542 543 p_mapreq = *mp; /* dup the whole structure */ 544 p_mapreq.map_type = DDI_MT_REGSPEC; 545 p_mapreq.map_obj.rp = &p_regspec; 546 rval = ddi_map(dip, &p_mapreq, 0, 0, addrp); 547 548 if (rval == DDI_SUCCESS) { 549 /* 550 * Set-up access functions for FM access error capable drivers. 551 * The axq workaround prevents fault management support 552 */ 553 if (DDI_FM_ACC_ERR_CAP(pci_p->pci_fm_cap) && 554 DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)) && 555 mp->map_handlep->ah_acc.devacc_attr_access != 556 DDI_DEFAULT_ACC) 557 pci_fm_acc_setup(mp, rdip); 558 pci_axq_setup(mp, pci_p->pci_pbm_p); 559 } 560 561 done: 562 if (mp->map_type == DDI_MT_RNUMBER) 563 kmem_free(rp - r_no, reglen); 564 565 return (rval); 566 } 567 568 /* 569 * bus dma map entry point 570 * return value: 571 * DDI_DMA_PARTIAL_MAP 1 572 * DDI_DMA_MAPOK 0 573 * DDI_DMA_MAPPED 0 574 * DDI_DMA_NORESOURCES -1 575 * DDI_DMA_NOMAPPING -2 576 * DDI_DMA_TOOBIG -3 577 */ 578 int 579 pci_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq, 580 ddi_dma_handle_t *handlep) 581 { 582 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 583 iommu_t *iommu_p = pci_p->pci_iommu_p; 584 ddi_dma_impl_t *mp; 585 int ret; 586 587 DEBUG3(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n", 588 ddi_driver_name(rdip), ddi_get_instance(rdip), 589 handlep ? "alloc" : "advisory"); 590 591 if (!(mp = pci_dma_lmts2hdl(dip, rdip, iommu_p, dmareq))) 592 return (DDI_DMA_NORESOURCES); 593 if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING) 594 return (DDI_DMA_NOMAPPING); 595 if (ret = pci_dma_type(pci_p, dmareq, mp)) 596 goto freehandle; 597 if (ret = pci_dma_pfn(pci_p, dmareq, mp)) 598 goto freehandle; 599 600 switch (PCI_DMA_TYPE(mp)) { 601 case DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 602 if ((ret = pci_dvma_win(pci_p, dmareq, mp)) || !handlep) 603 goto freehandle; 604 if (!PCI_DMA_CANCACHE(mp)) { /* try fast track */ 605 if (PCI_DMA_CANFAST(mp)) { 606 if (!pci_dvma_map_fast(iommu_p, mp)) 607 break; 608 /* LINTED E_NOP_ELSE_STMT */ 609 } else { 610 PCI_DVMA_FASTTRAK_PROF(mp); 611 } 612 } 613 if (ret = pci_dvma_map(mp, dmareq, iommu_p)) 614 goto freehandle; 615 break; 616 case DMAI_FLAGS_PEER_TO_PEER: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 617 if ((ret = pci_dma_physwin(pci_p, dmareq, mp)) || !handlep) 618 goto freehandle; 619 break; 620 case DMAI_FLAGS_BYPASS: 621 default: 622 panic("%s%d: pci_dma_setup: bad dma type 0x%x", 623 ddi_driver_name(rdip), ddi_get_instance(rdip), 624 PCI_DMA_TYPE(mp)); 625 /*NOTREACHED*/ 626 } 627 *handlep = (ddi_dma_handle_t)mp; 628 mp->dmai_flags |= (DMAI_FLAGS_INUSE | DMAI_FLAGS_MAPPED); 629 dump_dma_handle(DBG_DMA_MAP, dip, mp); 630 631 return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 632 freehandle: 633 if (ret == DDI_DMA_NORESOURCES) 634 pci_dma_freemp(mp); /* don't run_callback() */ 635 else 636 (void) pci_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 637 return (ret); 638 } 639 640 641 /* 642 * bus dma alloc handle entry point: 643 */ 644 int 645 pci_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 646 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 647 { 648 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 649 ddi_dma_impl_t *mp; 650 int rval; 651 652 DEBUG2(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", 653 ddi_driver_name(rdip), ddi_get_instance(rdip)); 654 655 if (attrp->dma_attr_version != DMA_ATTR_V0) 656 return (DDI_DMA_BADATTR); 657 658 if (!(mp = pci_dma_allocmp(dip, rdip, waitfp, arg))) 659 return (DDI_DMA_NORESOURCES); 660 661 /* 662 * Save requestor's information 663 */ 664 mp->dmai_attr = *attrp; /* whole object - augmented later */ 665 *DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */ 666 DEBUG1(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 667 668 /* check and convert dma attributes to handle parameters */ 669 if (rval = pci_dma_attr2hdl(pci_p, mp)) { 670 pci_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 671 *handlep = NULL; 672 return (rval); 673 } 674 *handlep = (ddi_dma_handle_t)mp; 675 return (DDI_SUCCESS); 676 } 677 678 679 /* 680 * bus dma free handle entry point: 681 */ 682 /*ARGSUSED*/ 683 int 684 pci_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 685 { 686 DEBUG3(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n", 687 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 688 pci_dma_freemp((ddi_dma_impl_t *)handle); 689 690 if (pci_kmem_clid) { 691 DEBUG0(DBG_DMA_FREEH, dip, "run handle callback\n"); 692 ddi_run_callback(&pci_kmem_clid); 693 } 694 return (DDI_SUCCESS); 695 } 696 697 698 /* 699 * bus dma bind handle entry point: 700 */ 701 int 702 pci_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 703 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 704 ddi_dma_cookie_t *cookiep, uint_t *ccountp) 705 { 706 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 707 iommu_t *iommu_p = pci_p->pci_iommu_p; 708 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 709 int ret; 710 711 DEBUG4(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", 712 ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq); 713 714 if (mp->dmai_flags & DMAI_FLAGS_INUSE) 715 return (DDI_DMA_INUSE); 716 717 ASSERT((mp->dmai_flags & ~DMAI_FLAGS_PRESERVE) == 0); 718 mp->dmai_flags |= DMAI_FLAGS_INUSE; 719 720 if (ret = pci_dma_type(pci_p, dmareq, mp)) 721 goto err; 722 if (ret = pci_dma_pfn(pci_p, dmareq, mp)) 723 goto err; 724 725 switch (PCI_DMA_TYPE(mp)) { 726 case DMAI_FLAGS_DVMA: 727 if (ret = pci_dvma_win(pci_p, dmareq, mp)) 728 goto map_err; 729 if (!PCI_DMA_CANCACHE(mp)) { /* try fast track */ 730 if (PCI_DMA_CANFAST(mp)) { 731 if (!pci_dvma_map_fast(iommu_p, mp)) 732 goto mapped; /*LINTED E_NOP_ELSE_STMT*/ 733 } else { 734 PCI_DVMA_FASTTRAK_PROF(mp); 735 } 736 } 737 if (ret = pci_dvma_map(mp, dmareq, iommu_p)) 738 goto map_err; 739 mapped: 740 *ccountp = 1; 741 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size); 742 break; 743 case DMAI_FLAGS_BYPASS: 744 case DMAI_FLAGS_PEER_TO_PEER: 745 if (ret = pci_dma_physwin(pci_p, dmareq, mp)) 746 goto map_err; 747 *ccountp = WINLST(mp)->win_ncookies; 748 *cookiep = *(ddi_dma_cookie_t *)(WINLST(mp) + 1); /* wholeobj */ 749 break; 750 default: 751 panic("%s%d: pci_dma_bindhdl(%p): bad dma type", 752 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 753 /*NOTREACHED*/ 754 } 755 DEBUG2(DBG_DMA_BINDH, dip, "cookie %x+%x\n", cookiep->dmac_address, 756 cookiep->dmac_size); 757 dump_dma_handle(DBG_DMA_MAP, dip, mp); 758 759 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 760 (void) ndi_fmc_insert(rdip, DMA_HANDLE, mp, NULL); 761 mp->dmai_error.err_cf = impl_dma_check; 762 } 763 764 mp->dmai_flags |= DMAI_FLAGS_MAPPED; 765 return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 766 map_err: 767 pci_dvma_unregister_callbacks(pci_p, mp); 768 pci_dma_freepfn(mp); 769 err: 770 mp->dmai_flags &= DMAI_FLAGS_PRESERVE; 771 return (ret); 772 } 773 774 /* 775 * bus dma unbind handle entry point: 776 */ 777 /*ARGSUSED*/ 778 int 779 pci_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 780 { 781 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 782 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 783 iommu_t *iommu_p = pci_p->pci_iommu_p; 784 785 DEBUG3(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 786 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 787 if ((mp->dmai_flags & DMAI_FLAGS_INUSE) == 0) { 788 DEBUG0(DBG_DMA_UNBINDH, dip, "handle not in use\n"); 789 return (DDI_FAILURE); 790 } 791 792 mp->dmai_flags &= ~DMAI_FLAGS_MAPPED; 793 794 switch (PCI_DMA_TYPE(mp)) { 795 case DMAI_FLAGS_DVMA: 796 pci_dvma_unregister_callbacks(pci_p, mp); 797 pci_dma_sync_unmap(dip, rdip, mp); 798 pci_dvma_unmap(iommu_p, mp); 799 pci_dma_freepfn(mp); 800 break; 801 case DMAI_FLAGS_BYPASS: 802 case DMAI_FLAGS_PEER_TO_PEER: 803 pci_dma_freewin(mp); 804 break; 805 default: 806 panic("%s%d: pci_dma_unbindhdl:bad dma type %p", 807 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 808 /*NOTREACHED*/ 809 } 810 if (iommu_p->iommu_dvma_clid != 0) { 811 DEBUG0(DBG_DMA_UNBINDH, dip, "run dvma callback\n"); 812 ddi_run_callback(&iommu_p->iommu_dvma_clid); 813 } 814 if (pci_kmem_clid) { 815 DEBUG0(DBG_DMA_UNBINDH, dip, "run handle callback\n"); 816 ddi_run_callback(&pci_kmem_clid); 817 } 818 mp->dmai_flags &= DMAI_FLAGS_PRESERVE; 819 SYNC_BUF_PA(mp) = 0; 820 821 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 822 if (DEVI(rdip)->devi_fmhdl != NULL && 823 DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap)) { 824 (void) ndi_fmc_remove(rdip, DMA_HANDLE, mp); 825 } 826 } 827 828 return (DDI_SUCCESS); 829 } 830 831 832 /* 833 * bus dma win entry point: 834 */ 835 int 836 pci_dma_win(dev_info_t *dip, dev_info_t *rdip, 837 ddi_dma_handle_t handle, uint_t win, off_t *offp, 838 size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 839 { 840 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 841 DEBUG2(DBG_DMA_WIN, dip, "rdip=%s%d\n", 842 ddi_driver_name(rdip), ddi_get_instance(rdip)); 843 dump_dma_handle(DBG_DMA_WIN, dip, mp); 844 if (win >= mp->dmai_nwin) { 845 DEBUG1(DBG_DMA_WIN, dip, "%x out of range\n", win); 846 return (DDI_FAILURE); 847 } 848 849 switch (PCI_DMA_TYPE(mp)) { 850 case DMAI_FLAGS_DVMA: 851 if (win != PCI_DMA_CURWIN(mp)) { 852 pci_t *pci_p = 853 get_pci_soft_state(ddi_get_instance(dip)); 854 pci_dma_sync_unmap(dip, rdip, mp); 855 /* map_window sets dmai_mapping/size/offset */ 856 iommu_map_window(pci_p->pci_iommu_p, mp, win); 857 } 858 if (cookiep) 859 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, 860 mp->dmai_size); 861 if (ccountp) 862 *ccountp = 1; 863 break; 864 case DMAI_FLAGS_PEER_TO_PEER: 865 case DMAI_FLAGS_BYPASS: { 866 int i; 867 ddi_dma_cookie_t *ck_p; 868 pci_dma_win_t *win_p = mp->dmai_winlst; 869 870 for (i = 0; i < win; win_p = win_p->win_next, i++) 871 ; 872 ck_p = (ddi_dma_cookie_t *)(win_p + 1); 873 *cookiep = *ck_p; 874 mp->dmai_offset = win_p->win_offset; 875 mp->dmai_size = win_p->win_size; 876 mp->dmai_mapping = ck_p->dmac_laddress; 877 mp->dmai_cookie = ck_p + 1; 878 win_p->win_curseg = 0; 879 if (ccountp) 880 *ccountp = win_p->win_ncookies; 881 } 882 break; 883 default: 884 cmn_err(CE_WARN, "%s%d: pci_dma_win:bad dma type 0x%x", 885 ddi_driver_name(rdip), ddi_get_instance(rdip), 886 PCI_DMA_TYPE(mp)); 887 return (DDI_FAILURE); 888 } 889 if (cookiep) 890 DEBUG2(DBG_DMA_WIN, dip, 891 "cookie - dmac_address=%x dmac_size=%x\n", 892 cookiep->dmac_address, cookiep->dmac_size); 893 if (offp) 894 *offp = (off_t)mp->dmai_offset; 895 if (lenp) 896 *lenp = mp->dmai_size; 897 return (DDI_SUCCESS); 898 } 899 900 #ifdef DEBUG 901 static char *pci_dmactl_str[] = { 902 "DDI_DMA_FREE", 903 "DDI_DMA_SYNC", 904 "DDI_DMA_HTOC", 905 "DDI_DMA_KVADDR", 906 "DDI_DMA_MOVWIN", 907 "DDI_DMA_REPWIN", 908 "DDI_DMA_GETERR", 909 "DDI_DMA_COFF", 910 "DDI_DMA_NEXTWIN", 911 "DDI_DMA_NEXTSEG", 912 "DDI_DMA_SEGTOC", 913 "DDI_DMA_RESERVE", 914 "DDI_DMA_RELEASE", 915 "DDI_DMA_RESETH", 916 "DDI_DMA_CKSYNC", 917 "DDI_DMA_IOPB_ALLOC", 918 "DDI_DMA_IOPB_FREE", 919 "DDI_DMA_SMEM_ALLOC", 920 "DDI_DMA_SMEM_FREE", 921 "DDI_DMA_SET_SBUS64", 922 "DDI_DMA_REMAP" 923 }; 924 #endif 925 926 /* 927 * bus dma control entry point: 928 */ 929 int 930 pci_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 931 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 932 uint_t cache_flags) 933 { 934 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 935 DEBUG3(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", pci_dmactl_str[cmd], 936 ddi_driver_name(rdip), ddi_get_instance(rdip)); 937 938 switch (cmd) { 939 case DDI_DMA_FREE: 940 (void) pci_dma_unbindhdl(dip, rdip, handle); 941 (void) pci_dma_freehdl(dip, rdip, handle); 942 return (DDI_SUCCESS); 943 case DDI_DMA_RESERVE: { 944 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 945 return (pci_fdvma_reserve(dip, rdip, pci_p, 946 (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp)); 947 } 948 case DDI_DMA_RELEASE: { 949 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 950 return (pci_fdvma_release(dip, pci_p, mp)); 951 } 952 default: 953 break; 954 } 955 956 switch (PCI_DMA_TYPE(mp)) { 957 case DMAI_FLAGS_DVMA: 958 return (pci_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 959 cache_flags)); 960 case DMAI_FLAGS_PEER_TO_PEER: 961 case DMAI_FLAGS_BYPASS: 962 return (pci_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 963 cache_flags)); 964 default: 965 panic("%s%d: pci_dma_ctlops(%x):bad dma type %x", 966 ddi_driver_name(rdip), ddi_get_instance(rdip), cmd, 967 mp->dmai_flags); 968 /*NOTREACHED*/ 969 } 970 } 971 972 #ifdef DEBUG 973 int pci_peekfault_cnt = 0; 974 int pci_pokefault_cnt = 0; 975 #endif /* DEBUG */ 976 977 static int 978 pci_do_poke(pci_t *pci_p, peekpoke_ctlops_t *in_args) 979 { 980 pbm_t *pbm_p = pci_p->pci_pbm_p; 981 int err = DDI_SUCCESS; 982 on_trap_data_t otd; 983 984 mutex_enter(&pbm_p->pbm_pokefault_mutex); 985 pbm_p->pbm_ontrap_data = &otd; 986 987 /* Set up protected environment. */ 988 if (!on_trap(&otd, OT_DATA_ACCESS)) { 989 uintptr_t tramp = otd.ot_trampoline; 990 991 otd.ot_trampoline = (uintptr_t)&poke_fault; 992 err = do_poke(in_args->size, (void *)in_args->dev_addr, 993 (void *)in_args->host_addr); 994 otd.ot_trampoline = tramp; 995 } else 996 err = DDI_FAILURE; 997 998 /* 999 * Read the async fault register for the PBM to see it sees 1000 * a master-abort. 1001 */ 1002 pbm_clear_error(pbm_p); 1003 1004 if (otd.ot_trap & OT_DATA_ACCESS) 1005 err = DDI_FAILURE; 1006 1007 /* Take down protected environment. */ 1008 no_trap(); 1009 1010 pbm_p->pbm_ontrap_data = NULL; 1011 mutex_exit(&pbm_p->pbm_pokefault_mutex); 1012 1013 #ifdef DEBUG 1014 if (err == DDI_FAILURE) 1015 pci_pokefault_cnt++; 1016 #endif 1017 return (err); 1018 } 1019 1020 1021 static int 1022 pci_do_caut_put(pci_t *pci_p, peekpoke_ctlops_t *cautacc_ctlops_arg) 1023 { 1024 size_t size = cautacc_ctlops_arg->size; 1025 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1026 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1027 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1028 size_t repcount = cautacc_ctlops_arg->repcount; 1029 uint_t flags = cautacc_ctlops_arg->flags; 1030 1031 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1032 1033 /* 1034 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1035 * mutex. 1036 */ 1037 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1038 1039 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1040 for (; repcount; repcount--) { 1041 switch (size) { 1042 1043 case sizeof (uint8_t): 1044 i_ddi_put8(hp, (uint8_t *)dev_addr, 1045 *(uint8_t *)host_addr); 1046 break; 1047 1048 case sizeof (uint16_t): 1049 i_ddi_put16(hp, (uint16_t *)dev_addr, 1050 *(uint16_t *)host_addr); 1051 break; 1052 1053 case sizeof (uint32_t): 1054 i_ddi_put32(hp, (uint32_t *)dev_addr, 1055 *(uint32_t *)host_addr); 1056 break; 1057 1058 case sizeof (uint64_t): 1059 i_ddi_put64(hp, (uint64_t *)dev_addr, 1060 *(uint64_t *)host_addr); 1061 break; 1062 } 1063 1064 host_addr += size; 1065 1066 if (flags == DDI_DEV_AUTOINCR) 1067 dev_addr += size; 1068 1069 } 1070 } 1071 1072 i_ddi_notrap((ddi_acc_handle_t)hp); 1073 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1074 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1075 1076 if (hp->ahi_err->err_status != DDI_FM_OK) { 1077 /* Clear the expected fault from the handle before returning */ 1078 hp->ahi_err->err_status = DDI_FM_OK; 1079 return (DDI_FAILURE); 1080 } 1081 1082 return (DDI_SUCCESS); 1083 } 1084 1085 1086 static int 1087 pci_ctlops_poke(pci_t *pci_p, peekpoke_ctlops_t *in_args) 1088 { 1089 return (in_args->handle ? pci_do_caut_put(pci_p, in_args) : 1090 pci_do_poke(pci_p, in_args)); 1091 } 1092 1093 1094 static int 1095 pci_do_peek(pci_t *pci_p, peekpoke_ctlops_t *in_args) 1096 { 1097 int err = DDI_SUCCESS; 1098 on_trap_data_t otd; 1099 1100 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1101 uintptr_t tramp = otd.ot_trampoline; 1102 1103 otd.ot_trampoline = (uintptr_t)&peek_fault; 1104 err = do_peek(in_args->size, (void *)in_args->dev_addr, 1105 (void *)in_args->host_addr); 1106 otd.ot_trampoline = tramp; 1107 } else 1108 err = DDI_FAILURE; 1109 1110 no_trap(); 1111 1112 #ifdef DEBUG 1113 if (err == DDI_FAILURE) 1114 pci_peekfault_cnt++; 1115 #endif 1116 return (err); 1117 } 1118 1119 static int 1120 pci_do_caut_get(pci_t *pci_p, peekpoke_ctlops_t *cautacc_ctlops_arg) 1121 { 1122 size_t size = cautacc_ctlops_arg->size; 1123 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1124 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1125 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1126 size_t repcount = cautacc_ctlops_arg->repcount; 1127 uint_t flags = cautacc_ctlops_arg->flags; 1128 1129 int err = DDI_SUCCESS; 1130 1131 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1132 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1133 1134 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1135 for (; repcount; repcount--) { 1136 i_ddi_caut_get(size, (void *)dev_addr, 1137 (void *)host_addr); 1138 1139 host_addr += size; 1140 1141 if (flags == DDI_DEV_AUTOINCR) 1142 dev_addr += size; 1143 } 1144 } else { 1145 int i; 1146 uint8_t *ff_addr = (uint8_t *)host_addr; 1147 for (i = 0; i < size; i++) 1148 *ff_addr++ = 0xff; 1149 1150 err = DDI_FAILURE; 1151 } 1152 1153 i_ddi_notrap((ddi_acc_handle_t)hp); 1154 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1155 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1156 1157 return (err); 1158 } 1159 1160 1161 static int 1162 pci_ctlops_peek(pci_t *pci_p, peekpoke_ctlops_t *in_args, void *result) 1163 { 1164 result = (void *)in_args->host_addr; 1165 return (in_args->handle ? pci_do_caut_get(pci_p, in_args) : 1166 pci_do_peek(pci_p, in_args)); 1167 } 1168 1169 /* 1170 * get_reg_set_size 1171 * 1172 * Given a dev info pointer to a pci child and a register number, this 1173 * routine returns the size element of that reg set property. 1174 * return value: size of reg set on success, -1 on error 1175 */ 1176 static off_t 1177 get_reg_set_size(dev_info_t *child, int rnumber) 1178 { 1179 pci_regspec_t *pci_rp; 1180 off_t size; 1181 int i; 1182 1183 if (rnumber < 0) 1184 return (-1); 1185 1186 /* 1187 * Get the reg property for the device. 1188 */ 1189 if (ddi_getlongprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, "reg", 1190 (caddr_t)&pci_rp, &i) != DDI_SUCCESS) 1191 return (-1); 1192 1193 if (rnumber >= (i / (int)sizeof (pci_regspec_t))) { 1194 kmem_free(pci_rp, i); 1195 return (-1); 1196 } 1197 1198 size = pci_rp[rnumber].pci_size_low | 1199 ((uint64_t)pci_rp[rnumber].pci_size_hi << 32); 1200 kmem_free(pci_rp, i); 1201 return (size); 1202 } 1203 1204 1205 /* 1206 * control ops entry point: 1207 * 1208 * Requests handled completely: 1209 * DDI_CTLOPS_INITCHILD see init_child() for details 1210 * DDI_CTLOPS_UNINITCHILD 1211 * DDI_CTLOPS_REPORTDEV see report_dev() for details 1212 * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1 1213 * DDI_CTLOPS_REGSIZE 1214 * DDI_CTLOPS_NREGS 1215 * DDI_CTLOPS_DVMAPAGESIZE 1216 * DDI_CTLOPS_POKE 1217 * DDI_CTLOPS_PEEK 1218 * DDI_CTLOPS_QUIESCE 1219 * DDI_CTLOPS_UNQUIESCE 1220 * 1221 * All others passed to parent. 1222 */ 1223 int 1224 pci_ctlops(dev_info_t *dip, dev_info_t *rdip, 1225 ddi_ctl_enum_t op, void *arg, void *result) 1226 { 1227 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1228 1229 switch (op) { 1230 case DDI_CTLOPS_INITCHILD: 1231 return (init_child(pci_p, (dev_info_t *)arg)); 1232 1233 case DDI_CTLOPS_UNINITCHILD: 1234 return (uninit_child(pci_p, (dev_info_t *)arg)); 1235 1236 case DDI_CTLOPS_REPORTDEV: 1237 return (report_dev(rdip)); 1238 1239 case DDI_CTLOPS_IOMIN: 1240 1241 /* 1242 * If we are using the streaming cache, align at 1243 * least on a cache line boundary. Otherwise use 1244 * whatever alignment is passed in. 1245 */ 1246 1247 if ((uintptr_t)arg) { 1248 int val = *((int *)result); 1249 1250 val = maxbit(val, PCI_SBUF_LINE_SIZE); 1251 *((int *)result) = val; 1252 } 1253 return (DDI_SUCCESS); 1254 1255 case DDI_CTLOPS_REGSIZE: 1256 *((off_t *)result) = get_reg_set_size(rdip, *((int *)arg)); 1257 return (*((off_t *)result) == -1 ? DDI_FAILURE : DDI_SUCCESS); 1258 1259 case DDI_CTLOPS_NREGS: 1260 *((uint_t *)result) = get_nreg_set(rdip); 1261 return (DDI_SUCCESS); 1262 1263 case DDI_CTLOPS_DVMAPAGESIZE: 1264 *((ulong_t *)result) = IOMMU_PAGE_SIZE; 1265 return (DDI_SUCCESS); 1266 1267 case DDI_CTLOPS_POKE: 1268 return (pci_ctlops_poke(pci_p, (peekpoke_ctlops_t *)arg)); 1269 1270 case DDI_CTLOPS_PEEK: 1271 return (pci_ctlops_peek(pci_p, (peekpoke_ctlops_t *)arg, 1272 result)); 1273 1274 case DDI_CTLOPS_AFFINITY: 1275 break; 1276 1277 case DDI_CTLOPS_QUIESCE: 1278 return (pci_bus_quiesce(pci_p, rdip, result)); 1279 1280 case DDI_CTLOPS_UNQUIESCE: 1281 return (pci_bus_unquiesce(pci_p, rdip, result)); 1282 1283 default: 1284 break; 1285 } 1286 1287 /* 1288 * Now pass the request up to our parent. 1289 */ 1290 DEBUG2(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n", 1291 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1292 return (ddi_ctlops(dip, rdip, op, arg, result)); 1293 } 1294 1295 1296 /* ARGSUSED */ 1297 int 1298 pci_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1299 ddi_intr_handle_impl_t *hdlp, void *result) 1300 { 1301 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1302 ib_ino_t ino; 1303 int ret = DDI_SUCCESS; 1304 1305 switch (intr_op) { 1306 case DDI_INTROP_GETCAP: 1307 /* GetCap will always fail for all non PCI devices */ 1308 (void) pci_intx_get_cap(rdip, (int *)result); 1309 break; 1310 case DDI_INTROP_SETCAP: 1311 ret = DDI_ENOTSUP; 1312 break; 1313 case DDI_INTROP_ALLOC: 1314 *(int *)result = hdlp->ih_scratch1; 1315 break; 1316 case DDI_INTROP_FREE: 1317 break; 1318 case DDI_INTROP_GETPRI: 1319 *(int *)result = hdlp->ih_pri ? 1320 hdlp->ih_pri : pci_class_to_pil(rdip); 1321 break; 1322 case DDI_INTROP_SETPRI: 1323 break; 1324 case DDI_INTROP_ADDISR: 1325 ret = pci_add_intr(dip, rdip, hdlp); 1326 break; 1327 case DDI_INTROP_REMISR: 1328 ret = pci_remove_intr(dip, rdip, hdlp); 1329 break; 1330 case DDI_INTROP_GETTARGET: 1331 ino = IB_MONDO_TO_INO(pci_xlate_intr(dip, rdip, 1332 pci_p->pci_ib_p, IB_MONDO_TO_INO(hdlp->ih_vector))); 1333 ret = ib_get_intr_target(pci_p, ino, (int *)result); 1334 break; 1335 case DDI_INTROP_SETTARGET: 1336 ret = DDI_ENOTSUP; 1337 break; 1338 case DDI_INTROP_ENABLE: 1339 ret = ib_update_intr_state(pci_p, rdip, hdlp, 1340 PCI_INTR_STATE_ENABLE); 1341 break; 1342 case DDI_INTROP_DISABLE: 1343 ret = ib_update_intr_state(pci_p, rdip, hdlp, 1344 PCI_INTR_STATE_DISABLE); 1345 break; 1346 case DDI_INTROP_SETMASK: 1347 ret = pci_intx_set_mask(rdip); 1348 break; 1349 case DDI_INTROP_CLRMASK: 1350 ret = pci_intx_clr_mask(rdip); 1351 break; 1352 case DDI_INTROP_GETPENDING: 1353 ret = pci_intx_get_pending(rdip, (int *)result); 1354 break; 1355 case DDI_INTROP_NINTRS: 1356 case DDI_INTROP_NAVAIL: 1357 *(int *)result = i_ddi_get_intx_nintrs(rdip); 1358 break; 1359 case DDI_INTROP_SUPPORTED_TYPES: 1360 /* PCI nexus driver supports only fixed interrupts */ 1361 *(int *)result = i_ddi_get_intx_nintrs(rdip) ? 1362 DDI_INTR_TYPE_FIXED : 0; 1363 break; 1364 default: 1365 ret = DDI_ENOTSUP; 1366 break; 1367 } 1368 1369 return (ret); 1370 } 1371 1372 static void 1373 pci_init_hotplug(struct pci *pci_p) 1374 { 1375 pci_bus_range_t bus_range; 1376 dev_info_t *dip; 1377 1378 /* 1379 * Before initializing hotplug - open up 1380 * bus range. The busra module will 1381 * initialize its pool of bus numbers from 1382 * this. "busra" will be the agent that keeps 1383 * track of them during hotplug. Also, note, 1384 * that busra will remove any bus numbers 1385 * already in use from boot time. 1386 */ 1387 bus_range.lo = 0x0; 1388 bus_range.hi = 0xff; 1389 dip = pci_p->pci_dip; 1390 pci_p->hotplug_capable = B_FALSE; 1391 1392 /* 1393 * If this property exists, this nexus has hot-plug 1394 * slots. 1395 */ 1396 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1397 "hotplug-capable")) { 1398 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 1399 dip, "bus-range", 1400 (int *)&bus_range, 1401 2) != DDI_PROP_SUCCESS) { 1402 return; 1403 } 1404 1405 if (pcihp_init(dip) != DDI_SUCCESS) { 1406 return; 1407 } 1408 1409 if ((pcihp_ops = pcihp_get_cb_ops()) != NULL) { 1410 DEBUG2(DBG_ATTACH, dip, "%s%d hotplug enabled", 1411 ddi_driver_name(dip), ddi_get_instance(dip)); 1412 pci_p->hotplug_capable = B_TRUE; 1413 } 1414 } 1415 } 1416