1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * This is the nexus driver for SMBUS devices. It mostly does not use 31 * the SMBUS protocol so that it fits better into the solaris i2c 32 * framework. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/file.h> 38 #include <sys/open.h> 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/modctl.h> 42 #include <sys/stat.h> 43 #include <sys/kmem.h> 44 #include <sys/archsystm.h> 45 #include <sys/platform_module.h> 46 47 #include <sys/i2c/clients/i2c_client.h> 48 #include <sys/i2c/misc/i2c_svc.h> 49 #include <sys/i2c/misc/i2c_svc_impl.h> 50 #include <sys/i2c/nexus/smbus.h> 51 52 /* 53 * static function declarations 54 */ 55 static uint_t smbus_intr_cmn(smbus_t *smbus, char *src); 56 static void smbus_intr_timeout(void *arg); 57 static void smbus_resume(dev_info_t *dip); 58 static void smbus_suspend(dev_info_t *dip); 59 static int smbus_bus_ctl(dev_info_t *dip, dev_info_t *rdip, 60 ddi_ctl_enum_t op, void *arg, void *result); 61 static int smbus_acquire(smbus_t *, dev_info_t *dip, 62 i2c_transfer_t *tp); 63 static void smbus_release(smbus_t *); 64 static int smbus_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 65 static int smbus_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 66 static void smbus_free_regs(smbus_t *smbus); 67 static int smbus_setup_regs(dev_info_t *dip, smbus_t *smbus); 68 static void smbus_reportdev(dev_info_t *dip, dev_info_t *rdip); 69 static void smbus_uninitchild(dev_info_t *cdip); 70 static int smbus_initchild(dev_info_t *cdip); 71 static int smbus_rd(smbus_t *smbus); 72 static int smbus_wr(smbus_t *smbus); 73 static void smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags); 74 static uint8_t smbus_get(smbus_t *smbus, uint8_t reg); 75 static int smbus_dip_to_addr(dev_info_t *dip); 76 static uint_t smbus_intr(caddr_t arg); 77 static int smbus_switch(smbus_t *smbus); 78 79 static struct bus_ops smbus_busops = { 80 BUSO_REV, 81 nullbusmap, /* bus_map */ 82 NULL, /* bus_get_intrspec */ 83 NULL, /* bus_add_intrspec */ 84 NULL, /* bus_remove_intrspec */ 85 NULL, /* bus_map_fault */ 86 ddi_no_dma_map, /* bus_dma_map */ 87 ddi_no_dma_allochdl, /* bus_dma_allochdl */ 88 ddi_no_dma_freehdl, /* bus_dma_freehdl */ 89 ddi_no_dma_bindhdl, /* bus_dma_bindhdl */ 90 ddi_no_dma_unbindhdl, /* bus_unbindhdl */ 91 ddi_no_dma_flush, /* bus_dma_flush */ 92 ddi_no_dma_win, /* bus_dma_win */ 93 ddi_no_dma_mctl, /* bus_dma_ctl */ 94 smbus_bus_ctl, /* bus_ctl */ 95 ddi_bus_prop_op, /* bus_prop_op */ 96 NULL, /* bus_get_eventcookie */ 97 NULL, /* bus_add_eventcall */ 98 NULL, /* bus_remove_eventcall */ 99 NULL, /* bus_post_event */ 100 0, /* bus_intr_ctl */ 101 0, /* bus_config */ 102 0, /* bus_unconfig */ 103 0, /* bus_fm_init */ 104 0, /* bus_fm_fini */ 105 0, /* bus_fm_access_enter */ 106 0, /* bus_fm_access_exit */ 107 0, /* bus_power */ 108 i_ddi_intr_ops /* bus_intr_op */ 109 }; 110 111 struct cb_ops smbus_cb_ops = { 112 nodev, /* open */ 113 nodev, /* close */ 114 nodev, /* strategy */ 115 nodev, /* print */ 116 nodev, /* dump */ 117 nodev, /* read */ 118 nodev, /* write */ 119 nodev, /* ioctl */ 120 nodev, /* devmap */ 121 nodev, /* mmap */ 122 nodev, /* segmap */ 123 nochpoll, /* poll */ 124 ddi_prop_op, /* cb_prop_op */ 125 0, /* streamtab */ 126 D_MP | D_NEW /* Driver compatibility flag */ 127 }; 128 129 static struct dev_ops smbus_ops = { 130 DEVO_REV, 131 0, 132 ddi_no_info, 133 nulldev, 134 nulldev, 135 smbus_attach, 136 smbus_detach, 137 nodev, 138 &smbus_cb_ops, 139 &smbus_busops 140 }; 141 142 static struct modldrv modldrv = { 143 &mod_driverops, /* Type of module. This one is a driver */ 144 "SMBUS nexus Driver %I%", /* Name of the module. */ 145 &smbus_ops, /* driver ops */ 146 }; 147 148 static struct modlinkage modlinkage = { 149 MODREV_1, 150 &modldrv, 151 NULL 152 }; 153 154 /* 155 * Globals 156 */ 157 static void *smbus_state; 158 159 static int intr_timeout = INTR_TIMEOUT; 160 161 /* 162 * The "interrupt-priorities" property is how a driver can specify a SPARC 163 * PIL level to associate with each of its interrupt properties. Most 164 * self-identifying busses have a better mechanism for managing this, but I2C 165 * doesn't. 166 */ 167 int smbus_pil = SMBUS_PIL; 168 169 i2c_nexus_reg_t smbus_regvec = { 170 I2C_NEXUS_REV, 171 smbus_transfer, 172 }; 173 174 #ifdef DEBUG 175 176 static int smbus_print_lvl = 0; 177 static char msg_buff[1024]; 178 static kmutex_t msg_buf_lock; 179 180 void 181 smbus_print(int flags, const char *fmt, ...) 182 { 183 if (flags & smbus_print_lvl) { 184 va_list ap; 185 186 va_start(ap, fmt); 187 188 if (smbus_print_lvl & PRT_PROM) { 189 prom_vprintf(fmt, ap); 190 } else { 191 192 mutex_enter(&msg_buf_lock); 193 (void) vsprintf(msg_buff, fmt, ap); 194 if (smbus_print_lvl & PRT_BUFFONLY) { 195 cmn_err(CE_CONT, "?%s", msg_buff); 196 } else { 197 cmn_err(CE_CONT, "%s", msg_buff); 198 } 199 mutex_exit(&msg_buf_lock); 200 } 201 va_end(ap); 202 } 203 } 204 #endif /* DEBUG */ 205 206 int 207 _init(void) 208 { 209 int status; 210 211 status = ddi_soft_state_init(&smbus_state, sizeof (smbus_t), 212 1); 213 if (status != 0) { 214 215 return (status); 216 } 217 218 if ((status = mod_install(&modlinkage)) != 0) { 219 ddi_soft_state_fini(&smbus_state); 220 } else { 221 #ifdef DEBUG 222 mutex_init(&msg_buf_lock, NULL, MUTEX_DRIVER, NULL); 223 #endif 224 } 225 return (status); 226 } 227 228 int 229 _fini(void) 230 { 231 int status; 232 233 if ((status = mod_remove(&modlinkage)) == 0) { 234 ddi_soft_state_fini(&smbus_state); 235 #ifdef DEBUG 236 mutex_destroy(&msg_buf_lock); 237 #endif 238 } 239 240 return (status); 241 } 242 243 /* 244 * The loadable-module _info(9E) entry point 245 */ 246 int 247 _info(struct modinfo *modinfop) 248 { 249 return (mod_info(&modlinkage, modinfop)); 250 } 251 252 static void 253 smbus_interrupts_on(smbus_t *smbus) 254 { 255 int src_enable; 256 257 src_enable = ddi_get32(smbus->smbus_confighandle, 258 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 259 src_enable |= SMBUS_SMI; 260 ddi_put32(smbus->smbus_confighandle, 261 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA], 262 src_enable); 263 (void) ddi_get32(smbus->smbus_confighandle, 264 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 265 } 266 267 static void 268 smbus_interrupts_off(smbus_t *smbus) 269 { 270 int src_enable; 271 272 src_enable = ddi_get32(smbus->smbus_confighandle, 273 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 274 src_enable &= ~SMBUS_SMI; 275 ddi_put32(smbus->smbus_confighandle, 276 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA], 277 src_enable); 278 (void) ddi_get32(smbus->smbus_confighandle, 279 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_ENA]); 280 } 281 282 static void 283 smbus_dodetach(dev_info_t *dip) 284 { 285 smbus_t *smbus; 286 int instance = ddi_get_instance(dip); 287 288 smbus = ddi_get_soft_state(smbus_state, instance); 289 290 if (smbus == NULL) { 291 292 return; 293 } 294 295 cv_destroy(&smbus->smbus_cv); 296 mutex_destroy(&smbus->smbus_mutex); 297 298 if ((smbus->smbus_attachflags & INTERRUPT_PRI) != 0) { 299 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 300 "interrupt-priorities"); 301 } 302 303 smbus_free_regs(smbus); 304 305 if ((smbus->smbus_attachflags & NEXUS_REGISTER) != 0) { 306 i2c_nexus_unregister(dip); 307 } 308 if ((smbus->smbus_attachflags & IMUTEX) != 0) { 309 mutex_destroy(&smbus->smbus_imutex); 310 cv_destroy(&smbus->smbus_icv); 311 } 312 313 if (smbus->smbus_timeout != 0) { 314 (void) untimeout(smbus->smbus_timeout); 315 } 316 317 if ((smbus->smbus_attachflags & ADD_INTR) != 0) { 318 ddi_remove_intr(dip, 0, smbus->smbus_icookie); 319 } 320 321 ddi_soft_state_free(smbus_state, instance); 322 } 323 324 static int 325 smbus_doattach(dev_info_t *dip) 326 { 327 smbus_t *smbus; 328 int instance = ddi_get_instance(dip); 329 330 /* 331 * Allocate soft state structure. 332 */ 333 if (ddi_soft_state_zalloc(smbus_state, instance) != DDI_SUCCESS) { 334 335 goto bad; 336 } 337 338 smbus = ddi_get_soft_state(smbus_state, instance); 339 340 (void) snprintf(smbus->smbus_name, sizeof (smbus->smbus_name), 341 "%s%d", ddi_node_name(dip), instance); 342 343 smbus->smbus_dip = dip; 344 345 mutex_init(&smbus->smbus_mutex, NULL, MUTEX_DRIVER, NULL); 346 mutex_init(&smbus->smbus_imutex, NULL, MUTEX_DRIVER, NULL); 347 cv_init(&smbus->smbus_cv, NULL, CV_DRIVER, NULL); 348 cv_init(&smbus->smbus_intr_cv, NULL, CV_DRIVER, NULL); 349 350 if (smbus_setup_regs(dip, smbus) != DDI_SUCCESS) { 351 goto bad; 352 } 353 354 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 355 "interrupts") == 1) { 356 smbus->smbus_polling = 0; 357 /* 358 * The "interrupt-priorities" property is how a driver can 359 * specify a SPARC PIL level to associate with each of its 360 * interrupt properties. Most self-identifying busses have 361 * a better mechanism for managing this, but I2C doesn't. 362 */ 363 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, 364 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS, 365 "interrupt-priorities") != 1) { 366 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, 367 DDI_PROP_CANSLEEP, "interrupt-priorities", 368 (caddr_t)&smbus_pil, 369 sizeof (smbus_pil)); 370 smbus->smbus_attachflags |= INTERRUPT_PRI; 371 } 372 373 /* 374 * Clear status to clear any possible interrupt 375 */ 376 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 377 378 if (ddi_get_iblock_cookie(dip, 0, &smbus->smbus_icookie) != 379 DDI_SUCCESS) { 380 goto bad; 381 } 382 383 if (ddi_add_intr(dip, 0, NULL, NULL, smbus_intr, 384 (caddr_t)smbus) != DDI_SUCCESS) { 385 cmn_err(CE_WARN, "%s failed to add interrupt", 386 smbus->smbus_name); 387 goto bad; 388 } 389 smbus->smbus_attachflags |= ADD_INTR; 390 } else { 391 smbus->smbus_polling = 1; 392 /* Clear status */ 393 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 394 } 395 396 /* 397 * initialize a cv and mutex 398 */ 399 cv_init(&smbus->smbus_icv, NULL, CV_DRIVER, NULL); 400 mutex_init(&smbus->smbus_imutex, NULL, MUTEX_DRIVER, 401 (void *)smbus->smbus_icookie); 402 smbus->smbus_attachflags |= IMUTEX; 403 404 /* 405 * Register with the i2c framework 406 */ 407 i2c_nexus_register(dip, &smbus_regvec); 408 smbus->smbus_attachflags |= NEXUS_REGISTER; 409 410 return (DDI_SUCCESS); 411 412 bad: 413 smbus_dodetach(dip); 414 415 return (DDI_FAILURE); 416 } 417 418 static int 419 smbus_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 420 { 421 switch (cmd) { 422 case DDI_ATTACH: 423 424 return (smbus_doattach(dip)); 425 case DDI_RESUME: 426 smbus_resume(dip); 427 428 return (DDI_SUCCESS); 429 default: 430 431 return (DDI_FAILURE); 432 } 433 } 434 435 static int 436 smbus_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 437 { 438 switch (cmd) { 439 case DDI_DETACH: 440 smbus_dodetach(dip); 441 442 return (DDI_SUCCESS); 443 case DDI_SUSPEND: 444 smbus_suspend(dip); 445 446 return (DDI_SUCCESS); 447 default: 448 449 return (DDI_FAILURE); 450 } 451 } 452 453 static int 454 smbus_bus_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t op, 455 void *arg, void *result) 456 { 457 switch (op) { 458 case DDI_CTLOPS_INITCHILD: 459 460 return (smbus_initchild((dev_info_t *)arg)); 461 case DDI_CTLOPS_UNINITCHILD: 462 smbus_uninitchild((dev_info_t *)arg); 463 464 return (DDI_SUCCESS); 465 CTLOPS_REPORTDEV: 466 smbus_reportdev(dip, rdip); 467 468 return (DDI_SUCCESS); 469 case DDI_CTLOPS_DMAPMAPC: 470 case DDI_CTLOPS_POKE: 471 case DDI_CTLOPS_PEEK: 472 case DDI_CTLOPS_IOMIN: 473 case DDI_CTLOPS_REPORTINT: 474 case DDI_CTLOPS_SIDDEV: 475 case DDI_CTLOPS_SLAVEONLY: 476 case DDI_CTLOPS_AFFINITY: 477 case DDI_CTLOPS_PTOB: 478 case DDI_CTLOPS_BTOP: 479 case DDI_CTLOPS_BTOPR: 480 case DDI_CTLOPS_INTR_HILEVEL: 481 case DDI_CTLOPS_XLATE_INTRS: 482 case DDI_CTLOPS_DVMAPAGESIZE: 483 484 return (DDI_FAILURE); 485 default: 486 487 return (ddi_ctlops(dip, rdip, op, arg, result)); 488 } 489 } 490 491 static int 492 smbus_initchild(dev_info_t *cdip) 493 { 494 int32_t cell_size; 495 int len; 496 int32_t regs[2]; 497 int err; 498 smbus_ppvt_t *ppvt; 499 char name[30]; 500 501 SMBUS_PRINT((PRT_INIT, "smbus_initchild ENTER: %s\n", 502 ddi_node_name(cdip))); 503 504 len = sizeof (cell_size); 505 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip, 506 DDI_PROP_CANSLEEP, "#address-cells", 507 (caddr_t)&cell_size, &len); 508 if (err != DDI_PROP_SUCCESS || len != sizeof (cell_size)) { 509 cmn_err(CE_WARN, "cannot find address-cells"); 510 511 return (DDI_FAILURE); 512 } 513 514 len = sizeof (regs); 515 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip, 516 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, 517 "reg", (caddr_t)regs, &len); 518 519 if (err != DDI_PROP_SUCCESS) { 520 cmn_err(CE_WARN, "cannot get reg property"); 521 522 return (DDI_FAILURE); 523 } 524 525 ppvt = kmem_zalloc(sizeof (smbus_ppvt_t), KM_SLEEP); 526 ddi_set_parent_data(cdip, ppvt); 527 528 /* 529 * The reg property contains an unused first element (which is 530 * the mux addr on xcal), and the second element is the i2c bus 531 * address of the device. 532 */ 533 ppvt->smbus_ppvt_addr = regs[1]; 534 (void) sprintf(name, "%x", regs[1]); 535 536 ddi_set_name_addr(cdip, name); 537 538 SMBUS_PRINT((PRT_INIT, "smbus_initchild SUCCESS: %s\n", 539 ddi_node_name(cdip))); 540 541 return (DDI_SUCCESS); 542 } 543 544 static void 545 smbus_uninitchild(dev_info_t *cdip) 546 { 547 smbus_ppvt_t *ppvt; 548 549 ppvt = ddi_get_parent_data(cdip); 550 ddi_set_parent_data(cdip, NULL); 551 552 ddi_set_name_addr(cdip, NULL); 553 554 kmem_free(ppvt, sizeof (smbus_ppvt_t)); 555 556 SMBUS_PRINT((PRT_INIT, "smbus_uninitchild: %s\n", ddi_node_name(cdip))); 557 } 558 559 static void 560 smbus_reportdev(dev_info_t *dip, dev_info_t *rdip) 561 { 562 smbus_ppvt_t *ppvt; 563 564 ppvt = ddi_get_parent_data(rdip); 565 566 cmn_err(CE_CONT, "?%s%d at %s%d: addr 0x%x", 567 ddi_driver_name(rdip), ddi_get_instance(rdip), 568 ddi_driver_name(dip), ddi_get_instance(dip), 569 ppvt->smbus_ppvt_addr); 570 } 571 572 /* 573 * smbus_setup_regs() is called to map in the registers 574 * specific to the smbus. 575 */ 576 static int 577 smbus_setup_regs(dev_info_t *dip, smbus_t *smbus) 578 { 579 ddi_device_acc_attr_t attr; 580 int ret; 581 582 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 583 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 584 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 585 586 ret = ddi_regs_map_setup(dip, 1, (caddr_t *)&smbus->smbus_regaddr, 587 0, 0, &attr, &smbus->smbus_rhandle); 588 589 if (ret == DDI_FAILURE) { 590 cmn_err(CE_WARN, "%s unable to map regs", smbus->smbus_name); 591 592 } else if (ret == DDI_REGS_ACC_CONFLICT) { 593 cmn_err(CE_WARN, 594 "%s unable to map regs because of conflict", 595 smbus->smbus_name); 596 ret = DDI_FAILURE; 597 } 598 599 if (ret == DDI_FAILURE) { 600 601 return (ret); 602 } 603 604 ret = ddi_regs_map_setup(dip, 0, (caddr_t *)&smbus->smbus_configregaddr, 605 0, 0, &attr, &smbus->smbus_confighandle); 606 607 if (ret == DDI_FAILURE) { 608 cmn_err(CE_WARN, "%s unable to map config regs", 609 smbus->smbus_name); 610 611 } else if (ret == DDI_REGS_ACC_CONFLICT) { 612 cmn_err(CE_WARN, 613 "%s unable to map config regs because of conflict", 614 smbus->smbus_name); 615 ret = DDI_FAILURE; 616 } 617 618 return (ret); 619 } 620 621 /* 622 * smbus_free_regs() frees any registers previously allocated. 623 */ 624 static void 625 smbus_free_regs(smbus_t *smbus) 626 { 627 if (smbus->smbus_regaddr != NULL) { 628 ddi_regs_map_free(&smbus->smbus_rhandle); 629 } 630 631 if (smbus->smbus_configregaddr != NULL) { 632 ddi_regs_map_free(&smbus->smbus_confighandle); 633 } 634 } 635 636 /* 637 * smbus_dip_to_addr() takes a dip and returns an I2C address. 638 */ 639 static int 640 smbus_dip_to_addr(dev_info_t *cdip) 641 { 642 smbus_ppvt_t *ppvt; 643 644 ppvt = ddi_get_parent_data(cdip); 645 646 return (ppvt->smbus_ppvt_addr); 647 } 648 649 /* 650 * smbus_suspend() is called before the system suspends. Existing 651 * transfer in progress or waiting will complete, but new transfers are 652 * effectively blocked by "acquiring" the bus. 653 */ 654 static void 655 smbus_suspend(dev_info_t *dip) 656 { 657 smbus_t *smbus; 658 int instance; 659 660 instance = ddi_get_instance(dip); 661 smbus = ddi_get_soft_state(smbus_state, instance); 662 663 (void) smbus_acquire(smbus, NULL, NULL); 664 } 665 666 /* 667 * smbus_resume() is called when the system resumes from CPR. It releases 668 * the hold that was placed on the i2c bus, which allows any real 669 * transfers to continue. 670 */ 671 static void 672 smbus_resume(dev_info_t *dip) 673 { 674 smbus_t *smbus; 675 int instance; 676 677 instance = ddi_get_instance(dip); 678 smbus = ddi_get_soft_state(smbus_state, instance); 679 680 smbus_release(smbus); 681 } 682 683 /* 684 * smbus_acquire() is called by a thread wishing to "own" the SMbus. 685 * It should not be held across multiple transfers. 686 */ 687 static int 688 smbus_acquire(smbus_t *smbus, dev_info_t *dip, i2c_transfer_t *tp) 689 { 690 mutex_enter(&smbus->smbus_mutex); 691 while (smbus->smbus_busy) { 692 cv_wait(&smbus->smbus_cv, &smbus->smbus_mutex); 693 } 694 smbus->smbus_busy = 1; 695 mutex_exit(&smbus->smbus_mutex); 696 697 /* 698 * On systems where OBP shares a smbus controller with the 699 * OS, plat_shared_i2c_enter will serialize access to the 700 * smbus controller. Do not grab this lock during CPR 701 * suspend as the CPR thread also acquires this muxex 702 * through through prom_setprop which causes recursive 703 * mutex enter. 704 * 705 * dip == NULL during CPR. 706 */ 707 if ((&plat_shared_i2c_enter != NULL) && (dip != NULL)) { 708 plat_shared_i2c_enter(smbus->smbus_dip); 709 } 710 711 smbus->smbus_cur_tran = tp; 712 smbus->smbus_cur_dip = dip; 713 714 return (SMBUS_SUCCESS); 715 } 716 717 /* 718 * smbus_release() is called to release a hold made by smbus_acquire(). 719 */ 720 static void 721 smbus_release(smbus_t *smbus) 722 { 723 mutex_enter(&smbus->smbus_mutex); 724 smbus->smbus_busy = 0; 725 cv_signal(&smbus->smbus_cv); 726 smbus->smbus_cur_tran = NULL; 727 smbus->smbus_cur_dip = NULL; 728 mutex_exit(&smbus->smbus_mutex); 729 730 if ((&plat_shared_i2c_exit != NULL) && (smbus->smbus_cur_dip != NULL)) { 731 plat_shared_i2c_exit(smbus->smbus_dip); 732 } 733 } 734 735 static void 736 smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags) 737 { 738 ddi_acc_handle_t hp = smbus->smbus_rhandle; 739 uint8_t *reg_addr = smbus->smbus_regaddr; 740 uint8_t *config_addr = smbus->smbus_configregaddr; 741 ddi_acc_handle_t config_handle = smbus->smbus_confighandle; 742 743 ddi_put8(hp, ®_addr[reg], data); 744 745 SMBUS_PRINT((PRT_PUT, "smbus_put: addr = %p data = %x\n", 746 ®_addr[reg], data)); 747 748 /* 749 * if FLUSH flag is passed, read a config regs to make sure 750 * data written is flushed. 751 */ 752 if (flags & SMBUS_FLUSH) { 753 (void) ddi_get8(config_handle, &config_addr[0]); 754 } 755 } 756 757 static uint8_t 758 smbus_get(smbus_t *smbus, uint8_t reg) 759 { 760 761 ddi_acc_handle_t hp = smbus->smbus_rhandle; 762 uint8_t *regaddr = smbus->smbus_regaddr; 763 uint8_t data; 764 765 data = ddi_get8(hp, ®addr[reg]); 766 767 SMBUS_PRINT((PRT_GET, "smbus_get: data = %x\n", data)); 768 769 return (data); 770 } 771 772 773 /* 774 * The southbridge smbus device appears to have a feature where 775 * reads from the status register return 0 for a few microseconds 776 * after clearing the status. 777 * 778 * "status_wait_idle" allows for this by retrying until 779 * it gets the right answer or times out. The loop count 780 * and the delay are empirical. The routine uses up 781 * 400 us if it fails. 782 * 783 * The fact that this routine waits for 10 us before the 784 * first check is deliberate. 785 */ 786 static int 787 smbus_wait_idle(smbus_t *smbus) 788 { 789 int retries = 40; 790 int status; 791 792 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 793 do { 794 drv_usecwait(10); 795 status = smbus_get(smbus, SMB_STS); 796 } while (status != IDLE && --retries > 0); 797 return (status); 798 } 799 /* 800 * smbus_transfer is the function that is registered with 801 * I2C services to be called for each i2c transaction. 802 */ 803 int 804 smbus_transfer(dev_info_t *dip, i2c_transfer_t *tp) 805 { 806 smbus_t *smbus; 807 uint8_t status; 808 clock_t ctime; 809 810 smbus = ddi_get_soft_state(smbus_state, 811 ddi_get_instance(ddi_get_parent(dip))); 812 813 if (smbus_acquire(smbus, dip, tp) == SMBUS_FAILURE) { 814 tp->i2c_result = I2C_FAILURE; 815 816 return (I2C_FAILURE); 817 } 818 819 tp->i2c_r_resid = tp->i2c_rlen; 820 tp->i2c_w_resid = tp->i2c_wlen; 821 tp->i2c_result = I2C_SUCCESS; 822 smbus->smbus_retries = 0; 823 smbus->smbus_bytes_to_read = 0; 824 825 mutex_enter(&smbus->smbus_imutex); 826 827 SMBUS_PRINT((PRT_TRANS, "smbus_transfer: rlen=%d wlen=%d flags=%d", 828 tp->i2c_r_resid, tp->i2c_w_resid, tp->i2c_flags)); 829 830 /* 831 * First clear the status bits, then read them back to determine 832 * the current state. 833 */ 834 status = smbus_wait_idle(smbus); 835 836 if (status != IDLE) { 837 /* 838 * Try to issue bus reset 839 * First reset the state machine. 840 */ 841 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH); 842 status = smbus_wait_idle(smbus); 843 844 if (status != IDLE) { 845 846 smbus_put(smbus, SMB_TYP, T_OUT, SMBUS_FLUSH); 847 status = smbus_wait_idle(smbus); 848 if (status != IDLE) { 849 cmn_err(CE_WARN, 850 "%s smbus not idle. Unable to reset %x", 851 smbus->smbus_name, status); 852 smbus->smbus_cur_tran->i2c_result = I2C_FAILURE; 853 mutex_exit(&smbus->smbus_imutex); 854 smbus_release(smbus); 855 856 return (I2C_FAILURE); 857 } else { 858 cmn_err(CE_WARN, "%s T_OUT reset required", 859 smbus->smbus_name); 860 } 861 } 862 } 863 864 if (smbus_switch(smbus) != SMBUS_COMPLETE) { 865 if (smbus->smbus_polling) { 866 smbus->smbus_poll_complete = 0; 867 smbus->smbus_poll_retries = 0; 868 do { 869 drv_usecwait(SMBUS_POLL_INTERVAL); 870 (void) smbus_intr_cmn(smbus, SMBUS_POLL); 871 } while (!smbus->smbus_poll_complete); 872 } else { 873 /* 874 * Start a timeout as there is a bug in southbridge 875 * smbus where sometimes a transaction never starts, 876 * and needs to be reinitiated. 877 */ 878 879 smbus->smbus_timeout = timeout(smbus_intr_timeout, 880 smbus, drv_usectohz(intr_timeout)); 881 SMBUS_PRINT((PRT_TRANS, 882 "starting timeout in smbus_transfer %p", 883 smbus->smbus_timeout)); 884 885 ctime = ddi_get_lbolt(); 886 ctime += drv_usectohz(SMBUS_TRANS_TIMEOUT); 887 888 smbus_interrupts_on(smbus); 889 890 891 cv_wait(&smbus->smbus_icv, &smbus->smbus_imutex); 892 } 893 } 894 895 896 mutex_exit(&smbus->smbus_imutex); 897 smbus_release(smbus); 898 899 return (tp->i2c_result); 900 } 901 902 /* 903 * This is called by smbus_intr_cmn() to figure out whether to call 904 * smbus_wr or smbus_rd depending on the command and current state. 905 */ 906 static int 907 smbus_switch(smbus_t *smbus) 908 { 909 int ret; 910 i2c_transfer_t *tp = smbus->smbus_cur_tran; 911 912 if (tp == NULL) { 913 cmn_err(CE_WARN, 914 "%s smbus_cur_tran is NULL. Transaction failed", 915 smbus->smbus_name); 916 917 return (SMBUS_FAILURE); 918 } 919 920 smbus->smbus_saved_w_resid = tp->i2c_w_resid; 921 922 switch (tp->i2c_flags) { 923 case I2C_WR: 924 ret = smbus_wr(smbus); 925 break; 926 case I2C_RD: 927 ret = smbus_rd(smbus); 928 break; 929 case I2C_WR_RD: 930 /* 931 * We could do a bit more decoding here, 932 * to allow the transactions that would 933 * work as a single smbus command to 934 * be done as such. It's not really 935 * worth the trouble. 936 */ 937 if (tp->i2c_w_resid > 0) { 938 ret = smbus_wr(smbus); 939 } else { 940 ret = smbus_rd(smbus); 941 } 942 break; 943 default: 944 tp->i2c_result = I2C_FAILURE; 945 ret = SMBUS_COMPLETE; 946 break; 947 } 948 949 return (ret); 950 } 951 952 /* 953 * 954 */ 955 static void 956 smbus_intr_timeout(void *arg) 957 { 958 smbus_t *smbus = (smbus_t *)arg; 959 960 mutex_enter(&smbus->smbus_imutex); 961 /* 962 * If timeout is already cleared, it means interrupt arrived 963 * while timeout fired. In this case, just return from here. 964 */ 965 if (smbus->smbus_timeout == 0) { 966 967 mutex_exit(&smbus->smbus_imutex); 968 969 return; 970 } 971 972 (void) smbus_intr_cmn(smbus, SMBUS_TIMEOUT); 973 mutex_exit(&smbus->smbus_imutex); 974 } 975 976 /* 977 * smbus_intr() is the interrupt handler for smbus. 978 */ 979 static uint_t 980 smbus_intr(caddr_t arg) 981 { 982 smbus_t *smbus = (smbus_t *)arg; 983 uint32_t intr_status; 984 uint_t result; 985 986 /* 987 * Check to see if intr is really from smbus 988 */ 989 intr_status = ddi_get32(smbus->smbus_confighandle, 990 (uint32_t *)&smbus->smbus_configregaddr[SMBUS_SRC_STATUS]); 991 992 993 if ((intr_status & SMBUS_SMB_INTR_STATUS) == 0) { 994 SMBUS_PRINT((PRT_INTR, "smbus_intr: intr not from smbus\n")); 995 996 return (DDI_INTR_UNCLAIMED); 997 } 998 999 mutex_enter(&smbus->smbus_imutex); 1000 1001 /* 1002 * If timeout is already cleared, it means it arrived before the intr. 1003 * In that case, just return from here. 1004 */ 1005 if (smbus->smbus_timeout == 0) { 1006 1007 mutex_exit(&smbus->smbus_imutex); 1008 1009 return (DDI_INTR_CLAIMED); 1010 } 1011 1012 result = smbus_intr_cmn(smbus, SMBUS_INTR); 1013 mutex_exit(&smbus->smbus_imutex); 1014 return (result); 1015 } 1016 1017 /* 1018 * smbus_intr() is the interrupt handler for smbus. 1019 */ 1020 static uint_t 1021 smbus_intr_cmn(smbus_t *smbus, char *src) 1022 { 1023 i2c_transfer_t *tp; 1024 char error_str[128]; 1025 uint8_t status; 1026 int ret = SMBUS_SUCCESS; 1027 timeout_id_t timer_id; 1028 1029 ASSERT(mutex_owned(&smbus->smbus_imutex)); 1030 error_str[0] = '\0'; 1031 1032 smbus_interrupts_off(smbus); 1033 1034 tp = smbus->smbus_cur_tran; 1035 /* 1036 * This only happens when top half is interrupted or 1037 * times out, then the interrupt arrives. Interrupt 1038 * was already disabled by top half, so just exit. 1039 */ 1040 if (tp == NULL) { 1041 return (DDI_INTR_CLAIMED); 1042 } 1043 1044 /* 1045 * This wait is required before reading the status, otherwise 1046 * a parity error can occur which causes a panic. A bug with 1047 * southbridge SMBUS. 1048 */ 1049 drv_usecwait(15); 1050 status = smbus_get(smbus, SMB_STS); 1051 if (smbus->smbus_polling) { 1052 /* 1053 * If we are polling, then we expect not to 1054 * get the right answer for a while, 1055 * so we don't go on to that error stuff 1056 * until we've polled the status for a 1057 * few times. We check for errors here to save time, 1058 * otherwise we would have to wait for the full 1059 * poll timeout before dealing with them. 1060 */ 1061 if (status != (CMD_CMPL|IDLE) && 1062 (status & (FAILED|BUS_ERR|DRV_ERR)) == 0 && 1063 smbus->smbus_poll_retries++ < SMBUS_POLL_MAX_RETRIES) { 1064 return (DDI_INTR_CLAIMED); 1065 } 1066 /* 1067 * else either ... 1068 * [] the command has completed, or; 1069 * [] There has been an error, or; 1070 * [] we timed out waiting for something useful 1071 * to happen, so we go on to to the error handling bit that 1072 * follows, * which will reset the controller then restart the 1073 * whole transaction. 1074 * 1075 * In all cases, clear "poll_retries" for the next command or 1076 * retry 1077 */ 1078 smbus->smbus_poll_retries = 0; 1079 } 1080 1081 /* 1082 * A bug in southbridge SMBUS sometimes requires a reset. Status 1083 * should NOT be IDLE without any other bit set. If it is, the 1084 * transaction should be restarted. 1085 */ 1086 1087 if (status == IDLE) { 1088 (void) sprintf(error_str, "%s bus is idle, ", error_str); 1089 } 1090 1091 if ((status & CMD_CMPL) == 0) { 1092 (void) sprintf(error_str, "%s command failed to complete, ", 1093 error_str); 1094 } 1095 if (status & BUS_ERR) { 1096 (void) sprintf(error_str, "%s bus error, ", error_str); 1097 } 1098 if (status & FAILED) { 1099 (void) sprintf(error_str, "%s failed transaction, ", error_str); 1100 } 1101 if (status & DRV_ERR) { 1102 (void) sprintf(error_str, "%s timeout or bus reset", error_str); 1103 } 1104 1105 if (error_str[0] != '\0') { 1106 (void) sprintf(error_str, "%s %s ", error_str, src); 1107 } 1108 1109 /* 1110 * Clear status to clear the interrupt. 1111 */ 1112 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 1113 if (error_str[0] != '\0') { 1114 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH); 1115 if (smbus->smbus_retries++ < SMBUS_MAX_RETRIES) { 1116 /* 1117 * XXXX There was a panic here when the 1118 * intr timeout was greater than the timeout 1119 * for the entire transfer. 1120 * 1121 * Restore the value of w_resid before the 1122 * last transaction. r_resid doesn't need to 1123 * be restored because it is only decremented 1124 * after a successful read. Need to do this 1125 * here since smbus_switch() keys off of a 1126 * resid to know whether to call smbus_rd() or 1127 * smbus_wr(). 1128 */ 1129 tp->i2c_w_resid = smbus->smbus_saved_w_resid; 1130 smbus->smbus_bytes_to_read = 0; 1131 1132 SMBUS_PRINT((PRT_INTR_ERR, 1133 "retrying: %s %s w_resid=%d\n", error_str, 1134 src, tp->i2c_w_resid)); 1135 } else { 1136 cmn_err(CE_WARN, "%s max retries exceeded: %s", 1137 smbus->smbus_name, error_str); 1138 /* 1139 * bailing, but first will reset the bus. 1140 */ 1141 smbus_put(smbus, SMB_TYP, KILL, SMBUS_FLUSH); 1142 smbus_put(smbus, SMB_STS, 0xff, SMBUS_FLUSH); 1143 smbus->smbus_cur_tran->i2c_result = I2C_FAILURE; 1144 1145 ret = SMBUS_FAILURE; 1146 } 1147 } else { 1148 smbus->smbus_retries = 0; 1149 } 1150 1151 if (tp != NULL) { 1152 SMBUS_PRINT((PRT_INTR, "flags=%d wresid=%d r_resid=%d %s\n", 1153 tp->i2c_flags, tp->i2c_w_resid, tp->i2c_r_resid, src)); 1154 } 1155 1156 if (ret != SMBUS_FAILURE) { 1157 ret = smbus_switch(smbus); 1158 } 1159 1160 if (smbus->smbus_polling) { 1161 if (ret == SMBUS_COMPLETE || ret == SMBUS_FAILURE) { 1162 smbus->smbus_poll_complete = 1; 1163 } 1164 } else { 1165 /* 1166 * Disable previous timeout. In case it was about to fire this 1167 * will let it exit without doing anything. 1168 */ 1169 timer_id = smbus->smbus_timeout; 1170 smbus->smbus_timeout = 0; 1171 mutex_exit(&smbus->smbus_imutex); 1172 (void) untimeout(timer_id); 1173 mutex_enter(&smbus->smbus_imutex); 1174 if (ret == SMBUS_COMPLETE || ret == SMBUS_FAILURE) { 1175 cv_signal(&smbus->smbus_icv); 1176 } else { 1177 smbus_interrupts_on(smbus); 1178 smbus->smbus_timeout = timeout(smbus_intr_timeout, 1179 smbus, drv_usectohz(intr_timeout)); 1180 SMBUS_PRINT((PRT_INTR, "smbus_intr starting timeout %p " 1181 "%s", smbus->smbus_timeout, src)); 1182 } 1183 } 1184 1185 return (DDI_INTR_CLAIMED); 1186 } 1187 1188 /* 1189 * smbus_wr handles writes to the smbus. Unlike true I2C busses 1190 * such as provided by pcf8584, smbus attaches a start and stop bit for each 1191 * transaction, so this limits writes to the maximum number of bytes 1192 * in a single transaction, which is 33. 1193 * 1194 * If more than 33 bytes are contained in the transfer, a non-zero 1195 * residual has to be returned, and the calling driver has to restart 1196 * another transaction to complete writing out any remaining data. The 1197 * reason for this is that most devices require a register/offset as the 1198 * first byte to be written for each SMBUS transaction. 1199 */ 1200 static int 1201 smbus_wr(smbus_t *smbus) 1202 { 1203 i2c_transfer_t *tp = smbus->smbus_cur_tran; 1204 uint8_t addr = smbus_dip_to_addr(smbus->smbus_cur_dip); 1205 int bytes_written = 0; 1206 uint8_t a; 1207 uint8_t b; 1208 1209 if (tp->i2c_w_resid != tp->i2c_wlen) { 1210 return (SMBUS_COMPLETE); 1211 } 1212 1213 SMBUS_PRINT((PRT_WR, "smbus_wr: addr = %x resid = %d\n", 1214 addr, tp->i2c_w_resid)); 1215 1216 smbus_put(smbus, SMB_STS, 0xff, 0); 1217 1218 /* 1219 * Address must be re-written for each command and it has to 1220 * be written before SMB_TYP. 1221 */ 1222 smbus_put(smbus, DEV_ADDR, addr, 0); 1223 1224 switch (tp->i2c_w_resid) { 1225 1226 case 1: 1227 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1228 smbus_put(smbus, SMB_CMD, a, 0); 1229 smbus_put(smbus, SMB_TYP, SEND_BYTE, 0); 1230 SMBUS_PRINT((PRT_WR, "smbus_wr: send one byte:" 1231 " %d\n", a)); 1232 break; 1233 case 2: 1234 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1235 smbus_put(smbus, SMB_CMD, a, 0); 1236 1237 b = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1238 smbus_put(smbus, DEV_DATA0, b, 0); 1239 smbus_put(smbus, SMB_TYP, WR_BYTE, 0); 1240 SMBUS_PRINT((PRT_WR, "smbus_wr: send two bytes:" 1241 " %d %d\n", a, b)); 1242 break; 1243 1244 default: 1245 /* 1246 * Write out as many bytes as possible in a single command. 1247 * Note that BLK_DATA just creats a byte stream. ie, the 1248 * smbus protocol is not used or interpreted by this driver. 1249 */ 1250 smbus_put(smbus, SMB_TYP, WR_BLK, 0); 1251 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1252 1253 smbus_put(smbus, SMB_CMD, a, 0); 1254 1255 SMBUS_PRINT((PRT_WR, "smbus_wr: send multiple bytes: ")); 1256 SMBUS_PRINT((PRT_WR, "%x ", a)); 1257 1258 while (tp->i2c_w_resid != 0) { 1259 a = tp->i2c_wbuf[tp->i2c_wlen - tp->i2c_w_resid--]; 1260 smbus_put(smbus, BLK_DATA, a, 0); 1261 SMBUS_PRINT((PRT_WR, "%x ", a)); 1262 /* 1263 * Note that MAX_BLK_SEND defines how many bytes may 1264 * be sent to the BLK_DATA register. The leading byte 1265 * already sent to the SMB_CMD register doesn't count 1266 * But ALL the BLK_DATA bytes count so pre-increment 1267 * bytes_written before testing. 1268 */ 1269 if (++bytes_written == MAX_BLK_SEND) { 1270 break; 1271 } 1272 } 1273 SMBUS_PRINT((PRT_WR, "\n")); 1274 smbus_put(smbus, DEV_DATA0, bytes_written, 0); 1275 break; 1276 } 1277 1278 /* 1279 * writing anything to port reg starts transfer 1280 */ 1281 smbus_put(smbus, STR_PORT, 0, SMBUS_FLUSH); 1282 1283 return (SMBUS_PENDING); 1284 } 1285 1286 /* 1287 * smbus_rd handles reads to the smbus. Unlike a true I2C bus 1288 * such as provided by pcf8584, smbus attaches a start and stop bit 1289 * for each transaction, which limits reads to the maximum number of 1290 * bytes in a single SMBUS transaction. (Block reads don't 1291 * seem to work on smbus, and the southbridge documentation is poor). 1292 * 1293 * It doesn't appear that reads spanning multiple I2C transactions 1294 * (ie each with a start-stop) affects the transfer when reading 1295 * multiple bytes from devices with internal counters. The counter 1296 * is correctly maintained. 1297 * 1298 * RD_WORD and RD_BYTE write out the byte in the SMB_CMD register 1299 * before reading, so RCV_BYTE is used instead. 1300 * 1301 * Multi-byte reads iniatiate a SMBUS transaction for each byte to be 1302 * received. Because register/offset information doesn't need to 1303 * be resent for each I2C transaction (as opposed to when writing data), 1304 * the driver can continue reading data in separate SMBUS transactions 1305 * until the requested buffer is filled. 1306 */ 1307 static int 1308 smbus_rd(smbus_t *smbus) 1309 { 1310 i2c_transfer_t *tp = smbus->smbus_cur_tran; 1311 uint8_t addr = smbus_dip_to_addr(smbus->smbus_cur_dip); 1312 1313 if (smbus->smbus_bytes_to_read == 1) { 1314 tp->i2c_rbuf[tp->i2c_rlen - tp->i2c_r_resid] = 1315 smbus_get(smbus, DEV_DATA0); 1316 SMBUS_PRINT((PRT_RD, "smbus_rd: data in = %d\n", 1317 tp->i2c_rbuf[tp->i2c_rlen - tp->i2c_r_resid])); 1318 tp->i2c_r_resid--; 1319 smbus->smbus_bytes_to_read = 0; 1320 1321 if (tp->i2c_r_resid == 0) { 1322 return (SMBUS_COMPLETE); 1323 } 1324 } 1325 1326 /* 1327 * Address must be re-written for each command. It must 1328 * be written before SMB_TYP. 1329 */ 1330 smbus_put(smbus, DEV_ADDR, addr | I2C_READ, 0); 1331 1332 if (tp->i2c_r_resid == 0) { 1333 smbus->smbus_bytes_to_read = 0; 1334 1335 return (SMBUS_COMPLETE); 1336 } 1337 1338 smbus->smbus_bytes_to_read = 1; 1339 smbus_put(smbus, SMB_TYP, RCV_BYTE, 0); 1340 1341 smbus_put(smbus, SMB_STS, 0xff, 0); 1342 1343 SMBUS_PRINT((PRT_RD, "smbus_rd: starting a read addr = %x resid = %d " 1344 "bytes_to_read=%d\n", addr, tp->i2c_r_resid, 1345 smbus->smbus_bytes_to_read)); 1346 1347 smbus_put(smbus, STR_PORT, 0, SMBUS_FLUSH); 1348 1349 return (SMBUS_PENDING); 1350 } 1351