1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/ddi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/archsystm.h> 33 #include <sys/vmsystm.h> 34 #include <sys/machparam.h> 35 #include <sys/machsystm.h> 36 #include <sys/machthread.h> 37 #include <sys/cpu.h> 38 #include <sys/cmp.h> 39 #include <sys/elf_SPARC.h> 40 #include <vm/hat_sfmmu.h> 41 #include <vm/seg_kmem.h> 42 #include <sys/cpuvar.h> 43 #include <sys/cheetahregs.h> 44 #include <sys/us3_module.h> 45 #include <sys/async.h> 46 #include <sys/cmn_err.h> 47 #include <sys/debug.h> 48 #include <sys/dditypes.h> 49 #include <sys/prom_debug.h> 50 #include <sys/prom_plat.h> 51 #include <sys/cpu_module.h> 52 #include <sys/sysmacros.h> 53 #include <sys/intreg.h> 54 #include <sys/clock.h> 55 #include <sys/platform_module.h> 56 #include <sys/machtrap.h> 57 #include <sys/ontrap.h> 58 #include <sys/panic.h> 59 #include <sys/memlist.h> 60 #include <sys/bootconf.h> 61 #include <sys/ivintr.h> 62 #include <sys/atomic.h> 63 #include <sys/fm/protocol.h> 64 #include <sys/fm/cpu/UltraSPARC-III.h> 65 #include <vm/vm_dep.h> 66 67 #ifdef CHEETAHPLUS_ERRATUM_25 68 #include <sys/cyclic.h> 69 #endif /* CHEETAHPLUS_ERRATUM_25 */ 70 71 /* 72 * Note that 'Cheetah PRM' refers to: 73 * SPARC V9 JPS1 Implementation Supplement: Sun UltraSPARC-III 74 */ 75 76 /* 77 * Setup trap handlers. 78 */ 79 void 80 cpu_init_trap(void) 81 { 82 CH_SET_TRAP(tt_pil15, ch_pil15_interrupt_instr); 83 84 CH_SET_TRAP(tt0_fecc, fecc_err_instr); 85 CH_SET_TRAP(tt1_fecc, fecc_err_tl1_instr); 86 CH_SET_TRAP(tt1_swtrap0, fecc_err_tl1_cont_instr); 87 } 88 89 static int 90 getintprop(pnode_t node, char *name, int deflt) 91 { 92 int value; 93 94 switch (prom_getproplen(node, name)) { 95 case sizeof (int): 96 (void) prom_getprop(node, name, (caddr_t)&value); 97 break; 98 99 default: 100 value = deflt; 101 break; 102 } 103 104 return (value); 105 } 106 107 /* 108 * Set the magic constants of the implementation. 109 */ 110 /*ARGSUSED*/ 111 void 112 cpu_fiximp(pnode_t dnode) 113 { 114 int i, a; 115 116 static struct { 117 char *name; 118 int *var; 119 int defval; 120 } prop[] = { 121 "dcache-size", &dcache_size, CH_DCACHE_SIZE, 122 "dcache-line-size", &dcache_linesize, CH_DCACHE_LSIZE, 123 "icache-size", &icache_size, CH_ICACHE_SIZE, 124 "icache-line-size", &icache_linesize, CH_ICACHE_LSIZE, 125 "ecache-size", &ecache_size, CH_ECACHE_MAX_SIZE, 126 "ecache-line-size", &ecache_alignsize, CH_ECACHE_MAX_LSIZE, 127 "ecache-associativity", &ecache_associativity, CH_ECACHE_NWAY 128 }; 129 130 for (i = 0; i < sizeof (prop) / sizeof (prop[0]); i++) 131 *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval); 132 133 ecache_setsize = ecache_size / ecache_associativity; 134 135 vac_size = CH_VAC_SIZE; 136 vac_mask = MMU_PAGEMASK & (vac_size - 1); 137 i = 0; a = vac_size; 138 while (a >>= 1) 139 ++i; 140 vac_shift = i; 141 shm_alignment = vac_size; 142 vac = 1; 143 144 /* 145 * Cheetah's large page support has problems with large numbers of 146 * large pages, so just disable large pages out-of-the-box. 147 * Note that the other defaults are set in sun4u/vm/mach_vm_dep.c. 148 */ 149 max_uheap_lpsize = MMU_PAGESIZE; 150 max_ustack_lpsize = MMU_PAGESIZE; 151 max_privmap_lpsize = MMU_PAGESIZE; 152 max_utext_lpsize = MMU_PAGESIZE; 153 max_shm_lpsize = MMU_PAGESIZE; 154 max_bootlp_tteszc = TTE8K; 155 } 156 157 void 158 send_mondo_set(cpuset_t set) 159 { 160 int lo, busy, nack, shipped = 0; 161 uint16_t i, cpuids[IDSR_BN_SETS]; 162 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 163 uint64_t starttick, endtick, tick, lasttick; 164 #if (NCPU > IDSR_BN_SETS) 165 int index = 0; 166 int ncpuids = 0; 167 #endif 168 #ifdef CHEETAHPLUS_ERRATUM_25 169 int recovered = 0; 170 int cpuid; 171 #endif 172 173 ASSERT(!CPUSET_ISNULL(set)); 174 starttick = lasttick = gettick(); 175 176 #if (NCPU <= IDSR_BN_SETS) 177 for (i = 0; i < NCPU; i++) 178 if (CPU_IN_SET(set, i)) { 179 shipit(i, shipped); 180 nackmask |= IDSR_NACK_BIT(shipped); 181 cpuids[shipped++] = i; 182 CPUSET_DEL(set, i); 183 if (CPUSET_ISNULL(set)) 184 break; 185 } 186 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 187 #else 188 for (i = 0; i < NCPU; i++) 189 if (CPU_IN_SET(set, i)) { 190 ncpuids++; 191 192 /* 193 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 194 * find we have shipped to more than (IDSR_BN_SETS) 195 * CPUs, set "index" to the highest numbered CPU in 196 * the set so we can ship to other CPUs a bit later on. 197 */ 198 if (shipped < IDSR_BN_SETS) { 199 shipit(i, shipped); 200 nackmask |= IDSR_NACK_BIT(shipped); 201 cpuids[shipped++] = i; 202 CPUSET_DEL(set, i); 203 if (CPUSET_ISNULL(set)) 204 break; 205 } else 206 index = (int)i; 207 } 208 209 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 210 #endif 211 212 busymask = IDSR_NACK_TO_BUSY(nackmask); 213 busy = nack = 0; 214 endtick = starttick + xc_tick_limit; 215 for (;;) { 216 idsr = getidsr(); 217 #if (NCPU <= IDSR_BN_SETS) 218 if (idsr == 0) 219 break; 220 #else 221 if (idsr == 0 && shipped == ncpuids) 222 break; 223 #endif 224 tick = gettick(); 225 /* 226 * If there is a big jump between the current tick 227 * count and lasttick, we have probably hit a break 228 * point. Adjust endtick accordingly to avoid panic. 229 */ 230 if (tick > (lasttick + xc_tick_jump_limit)) 231 endtick += (tick - lasttick); 232 lasttick = tick; 233 if (tick > endtick) { 234 if (panic_quiesce) 235 return; 236 #ifdef CHEETAHPLUS_ERRATUM_25 237 cpuid = -1; 238 for (i = 0; i < IDSR_BN_SETS; i++) { 239 if (idsr & (IDSR_NACK_BIT(i) | 240 IDSR_BUSY_BIT(i))) { 241 cpuid = cpuids[i]; 242 break; 243 } 244 } 245 if (cheetah_sendmondo_recover && cpuid != -1 && 246 recovered == 0) { 247 if (mondo_recover(cpuid, i)) { 248 /* 249 * We claimed the whole memory or 250 * full scan is disabled. 251 */ 252 recovered++; 253 } 254 tick = gettick(); 255 endtick = tick + xc_tick_limit; 256 lasttick = tick; 257 /* 258 * Recheck idsr 259 */ 260 continue; 261 } else 262 #endif /* CHEETAHPLUS_ERRATUM_25 */ 263 { 264 cmn_err(CE_CONT, "send mondo timeout " 265 "[%d NACK %d BUSY]\nIDSR 0x%" 266 "" PRIx64 " cpuids:", nack, busy, idsr); 267 for (i = 0; i < IDSR_BN_SETS; i++) { 268 if (idsr & (IDSR_NACK_BIT(i) | 269 IDSR_BUSY_BIT(i))) { 270 cmn_err(CE_CONT, " 0x%x", 271 cpuids[i]); 272 } 273 } 274 cmn_err(CE_CONT, "\n"); 275 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 276 } 277 } 278 curnack = idsr & nackmask; 279 curbusy = idsr & busymask; 280 #if (NCPU > IDSR_BN_SETS) 281 if (shipped < ncpuids) { 282 uint64_t cpus_left; 283 uint16_t next = (uint16_t)index; 284 285 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 286 busymask; 287 288 if (cpus_left) { 289 do { 290 /* 291 * Sequence through and ship to the 292 * remainder of the CPUs in the system 293 * (e.g. other than the first 294 * (IDSR_BN_SETS)) in reverse order. 295 */ 296 lo = lowbit(cpus_left) - 1; 297 i = IDSR_BUSY_IDX(lo); 298 shipit(next, i); 299 shipped++; 300 cpuids[i] = next; 301 302 /* 303 * If we've processed all the CPUs, 304 * exit the loop now and save 305 * instructions. 306 */ 307 if (shipped == ncpuids) 308 break; 309 310 for ((index = ((int)next - 1)); 311 index >= 0; index--) 312 if (CPU_IN_SET(set, index)) { 313 next = (uint16_t)index; 314 break; 315 } 316 317 cpus_left &= ~(1ull << lo); 318 } while (cpus_left); 319 #ifdef CHEETAHPLUS_ERRATUM_25 320 /* 321 * Clear recovered because we are sending to 322 * a new set of targets. 323 */ 324 recovered = 0; 325 #endif 326 continue; 327 } 328 } 329 #endif 330 if (curbusy) { 331 busy++; 332 continue; 333 } 334 335 #ifdef SEND_MONDO_STATS 336 { 337 int n = gettick() - starttick; 338 if (n < 8192) 339 x_nack_stimes[n >> 7]++; 340 } 341 #endif 342 while (gettick() < (tick + sys_clock_mhz)) 343 ; 344 do { 345 lo = lowbit(curnack) - 1; 346 i = IDSR_NACK_IDX(lo); 347 shipit(cpuids[i], i); 348 curnack &= ~(1ull << lo); 349 } while (curnack); 350 nack++; 351 busy = 0; 352 } 353 #ifdef SEND_MONDO_STATS 354 { 355 int n = gettick() - starttick; 356 if (n < 8192) 357 x_set_stimes[n >> 7]++; 358 else 359 x_set_ltimes[(n >> 13) & 0xf]++; 360 } 361 x_set_cpus[shipped]++; 362 #endif 363 } 364 365 /* 366 * Handles error logging for implementation specific error types. 367 */ 368 /*ARGSUSED*/ 369 int 370 cpu_impl_async_log_err(void *flt, errorq_elem_t *eqep) 371 { 372 /* There aren't any error types which are specific to cheetah only */ 373 return (CH_ASYNC_LOG_UNKNOWN); 374 } 375 376 /* 377 * Figure out if Ecache is direct-mapped (Cheetah or Cheetah+ with Ecache 378 * control ECCR_ASSOC bit off or 2-way (Cheetah+ with ECCR_ASSOC on). 379 * We need to do this on the fly because we may have mixed Cheetah+'s with 380 * both direct and 2-way Ecaches. 381 */ 382 int 383 cpu_ecache_nway(void) 384 { 385 return (CH_ECACHE_NWAY); 386 } 387 388 /* 389 * Note that these are entered into the table: Fatal Errors (PERR, IERR, 390 * ISAP, EMU) first, orphaned UCU/UCC, AFAR Overwrite policy, finally IVU, IVC. 391 * Afar overwrite policy is: 392 * UCU,UCC > UE,EDU,WDU,CPU > CE,EDC,EMC,WDC,CPC > TO,BERR 393 */ 394 ecc_type_to_info_t ecc_type_to_info[] = { 395 396 /* Fatal Errors */ 397 C_AFSR_PERR, "PERR ", ECC_ALL_TRAPS, CPU_FATAL, 398 "PERR Fatal", 399 FM_EREPORT_PAYLOAD_SYSTEM2, 400 FM_EREPORT_CPU_USIII_PERR, 401 C_AFSR_IERR, "IERR ", ECC_ALL_TRAPS, CPU_FATAL, 402 "IERR Fatal", 403 FM_EREPORT_PAYLOAD_SYSTEM2, 404 FM_EREPORT_CPU_USIII_IERR, 405 C_AFSR_ISAP, "ISAP ", ECC_ALL_TRAPS, CPU_FATAL, 406 "ISAP Fatal", 407 FM_EREPORT_PAYLOAD_SYSTEM1, 408 FM_EREPORT_CPU_USIII_ISAP, 409 C_AFSR_EMU, "EMU ", ECC_ASYNC_TRAPS, CPU_FATAL, 410 "EMU Fatal", 411 FM_EREPORT_PAYLOAD_MEMORY, 412 FM_EREPORT_CPU_USIII_EMU, 413 414 /* Orphaned UCC/UCU Errors */ 415 C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS, CPU_ORPH, 416 "Orphaned UCU", 417 FM_EREPORT_PAYLOAD_L2_DATA, 418 FM_EREPORT_CPU_USIII_UCU, 419 C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS, CPU_ORPH, 420 "Orphaned UCC", 421 FM_EREPORT_PAYLOAD_L2_DATA, 422 FM_EREPORT_CPU_USIII_UCC, 423 424 /* UCU, UCC */ 425 C_AFSR_UCU, "UCU ", ECC_F_TRAP, CPU_UE_ECACHE, 426 "UCU", 427 FM_EREPORT_PAYLOAD_L2_DATA, 428 FM_EREPORT_CPU_USIII_UCU, 429 C_AFSR_UCC, "UCC ", ECC_F_TRAP, CPU_CE_ECACHE, 430 "UCC", 431 FM_EREPORT_PAYLOAD_L2_DATA, 432 FM_EREPORT_CPU_USIII_UCC, 433 434 /* UE, EDU:ST, EDU:BLD, WDU, CPU */ 435 C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS, CPU_UE, 436 "Uncorrectable system bus (UE)", 437 FM_EREPORT_PAYLOAD_MEMORY, 438 FM_EREPORT_CPU_USIII_UE, 439 C_AFSR_EDU, "EDU ", ECC_C_TRAP, CPU_UE_ECACHE_RETIRE, 440 "EDU:ST", 441 FM_EREPORT_PAYLOAD_L2_DATA, 442 FM_EREPORT_CPU_USIII_EDUST, 443 C_AFSR_EDU, "EDU ", ECC_D_TRAP, CPU_UE_ECACHE_RETIRE, 444 "EDU:BLD", 445 FM_EREPORT_PAYLOAD_L2_DATA, 446 FM_EREPORT_CPU_USIII_EDUBL, 447 C_AFSR_WDU, "WDU ", ECC_C_TRAP, CPU_UE_ECACHE_RETIRE, 448 "WDU", 449 FM_EREPORT_PAYLOAD_L2_DATA, 450 FM_EREPORT_CPU_USIII_WDU, 451 C_AFSR_CPU, "CPU ", ECC_C_TRAP, CPU_UE_ECACHE, 452 "CPU", 453 FM_EREPORT_PAYLOAD_L2_DATA, 454 FM_EREPORT_CPU_USIII_CPU, 455 456 /* CE, EDC, EMC, WDC, CPC */ 457 C_AFSR_CE, "CE ", ECC_C_TRAP, CPU_CE, 458 "Corrected system bus (CE)", 459 FM_EREPORT_PAYLOAD_MEMORY, 460 FM_EREPORT_CPU_USIII_CE, 461 C_AFSR_EDC, "EDC ", ECC_C_TRAP, CPU_CE_ECACHE, 462 "EDC", 463 FM_EREPORT_PAYLOAD_L2_DATA, 464 FM_EREPORT_CPU_USIII_EDC, 465 C_AFSR_EMC, "EMC ", ECC_C_TRAP, CPU_EMC, 466 "EMC", 467 FM_EREPORT_PAYLOAD_MEMORY, 468 FM_EREPORT_CPU_USIII_EMC, 469 C_AFSR_WDC, "WDC ", ECC_C_TRAP, CPU_CE_ECACHE, 470 "WDC", 471 FM_EREPORT_PAYLOAD_L2_DATA, 472 FM_EREPORT_CPU_USIII_WDC, 473 C_AFSR_CPC, "CPC ", ECC_C_TRAP, CPU_CE_ECACHE, 474 "CPC", 475 FM_EREPORT_PAYLOAD_L2_DATA, 476 FM_EREPORT_CPU_USIII_CPC, 477 478 /* TO, BERR */ 479 C_AFSR_TO, "TO ", ECC_ASYNC_TRAPS, CPU_TO, 480 "Timeout (TO)", 481 FM_EREPORT_PAYLOAD_IO, 482 FM_EREPORT_CPU_USIII_TO, 483 C_AFSR_BERR, "BERR ", ECC_ASYNC_TRAPS, CPU_BERR, 484 "Bus Error (BERR)", 485 FM_EREPORT_PAYLOAD_IO, 486 FM_EREPORT_CPU_USIII_BERR, 487 488 /* IVU, IVC */ 489 C_AFSR_IVU, "IVU ", ECC_C_TRAP, CPU_IV, 490 "IVU", 491 FM_EREPORT_PAYLOAD_SYSTEM1, 492 FM_EREPORT_CPU_USIII_IVU, 493 C_AFSR_IVC, "IVC ", ECC_C_TRAP, CPU_IV, 494 "IVC", 495 FM_EREPORT_PAYLOAD_SYSTEM1, 496 FM_EREPORT_CPU_USIII_IVC, 497 498 0, NULL, 0, 0, 499 NULL, 500 FM_EREPORT_PAYLOAD_UNKNOWN, 501 FM_EREPORT_CPU_USIII_UNKNOWN, 502 }; 503 504 /* 505 * Prioritized list of Error bits for AFAR overwrite. 506 * See Cheetah PRM P.6.1 507 * Class 4: UCC, UCU 508 * Class 3: UE, EDU, EMU, WDU, CPU 509 * Class 2: CE, EDC, EMC, WDC, CPC 510 * Class 1: TO, BERR 511 */ 512 uint64_t afar_overwrite[] = { 513 C_AFSR_UCC | C_AFSR_UCU, 514 C_AFSR_UE | C_AFSR_EDU | C_AFSR_EMU | C_AFSR_WDU | C_AFSR_CPU, 515 C_AFSR_CE | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | C_AFSR_CPC, 516 C_AFSR_TO | C_AFSR_BERR, 517 0 518 }; 519 520 /* 521 * Prioritized list of Error bits for ESYND overwrite. 522 * See Cheetah PRM P.6.2 523 * Class 2: UE, IVU, EDU, WDU, UCU, CPU 524 * Class 1: CE, IVC, EDC, WDC, UCC, CPC 525 */ 526 uint64_t esynd_overwrite[] = { 527 C_AFSR_UE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | C_AFSR_UCU | 528 C_AFSR_CPU, 529 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_UCC | 530 C_AFSR_CPC, 531 0 532 }; 533 534 /* 535 * Prioritized list of Error bits for MSYND overwrite. 536 * See Cheetah PRM P.6.3 537 * Class 2: EMU 538 * Class 1: EMC 539 */ 540 uint64_t msynd_overwrite[] = { 541 C_AFSR_EMU, 542 C_AFSR_EMC, 543 0 544 }; 545 546 /* 547 * change cpu speed bits -- new speed will be normal-speed/divisor. 548 * 549 * The Jalapeno memory controllers are required to drain outstanding 550 * memory transactions within 32 JBus clocks in order to be ready 551 * to enter Estar mode. In some corner cases however, that time 552 * fell short. 553 * 554 * A safe software solution is to force MCU to act like in Estar mode, 555 * then delay 1us (in ppm code) prior to assert J_CHNG_L signal. 556 * To reverse the effect, upon exiting Estar, software restores the 557 * MCU to its original state. 558 */ 559 /* ARGSUSED1 */ 560 void 561 cpu_change_speed(uint64_t divisor, uint64_t arg2) 562 { 563 bus_config_eclk_t *bceclk; 564 uint64_t reg; 565 processor_info_t *pi = &(CPU->cpu_type_info); 566 567 for (bceclk = bus_config_eclk; bceclk->divisor; bceclk++) { 568 if (bceclk->divisor != divisor) 569 continue; 570 reg = get_safari_config(); 571 reg &= ~SAFARI_CONFIG_ECLK_MASK; 572 reg |= bceclk->mask; 573 set_safari_config(reg); 574 CPU->cpu_m.divisor = (uchar_t)divisor; 575 CPU->cpu_curr_clock = 576 (((uint64_t)pi->pi_clock * 1000000) / divisor); 577 return; 578 } 579 /* 580 * We will reach here only if OBP and kernel don't agree on 581 * the speeds supported by the CPU. 582 */ 583 cmn_err(CE_WARN, "cpu_change_speed: bad divisor %" PRIu64, divisor); 584 } 585 586 /* 587 * Cpu private initialization. This includes allocating the cpu_private 588 * data structure, initializing it, and initializing the scrubber for this 589 * cpu. This function calls cpu_init_ecache_scrub_dr to init the scrubber. 590 * We use kmem_cache_create for the cheetah private data structure because 591 * it needs to be allocated on a PAGESIZE (8192) byte boundary. 592 */ 593 void 594 cpu_init_private(struct cpu *cp) 595 { 596 cheetah_private_t *chprp; 597 int i; 598 599 ASSERT(CPU_PRIVATE(cp) == NULL); 600 601 /* LINTED: E_TRUE_LOGICAL_EXPR */ 602 ASSERT((offsetof(cheetah_private_t, chpr_tl1_err_data) + 603 sizeof (ch_err_tl1_data_t) * CH_ERR_TL1_TLMAX) <= PAGESIZE); 604 605 /* 606 * Running with a Cheetah+, Jaguar, or Panther on a Cheetah CPU 607 * machine is not a supported configuration. Attempting to do so 608 * may result in unpredictable failures (e.g. running Cheetah+ 609 * CPUs with Cheetah E$ disp flush) so don't allow it. 610 * 611 * This is just defensive code since this configuration mismatch 612 * should have been caught prior to OS execution. 613 */ 614 if (!IS_CHEETAH(cpunodes[cp->cpu_id].implementation)) { 615 cmn_err(CE_PANIC, "CPU%d: UltraSPARC-III+/IV/IV+ not" 616 " supported on UltraSPARC-III code\n", cp->cpu_id); 617 } 618 619 /* 620 * If the ch_private_cache has not been created, create it. 621 */ 622 if (ch_private_cache == NULL) { 623 ch_private_cache = kmem_cache_create("ch_private_cache", 624 sizeof (cheetah_private_t), PAGESIZE, NULL, NULL, 625 NULL, NULL, static_arena, 0); 626 } 627 628 chprp = CPU_PRIVATE(cp) = kmem_cache_alloc(ch_private_cache, KM_SLEEP); 629 630 bzero(chprp, sizeof (cheetah_private_t)); 631 chprp->chpr_fecctl0_logout.clo_data.chd_afar = LOGOUT_INVALID; 632 chprp->chpr_cecc_logout.clo_data.chd_afar = LOGOUT_INVALID; 633 chprp->chpr_async_logout.clo_data.chd_afar = LOGOUT_INVALID; 634 for (i = 0; i < CH_ERR_TL1_TLMAX; i++) 635 chprp->chpr_tl1_err_data[i].ch_err_tl1_logout.clo_data.chd_afar 636 = LOGOUT_INVALID; 637 638 chprp->chpr_icache_size = CH_ICACHE_SIZE; 639 chprp->chpr_icache_linesize = CH_ICACHE_LSIZE; 640 641 cpu_init_ecache_scrub_dr(cp); 642 643 chprp->chpr_ec_set_size = cpunodes[cp->cpu_id].ecache_size / 644 cpu_ecache_nway(); 645 646 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 647 ch_err_tl1_paddrs[cp->cpu_id] = va_to_pa(chprp); 648 ASSERT(ch_err_tl1_paddrs[cp->cpu_id] != -1); 649 } 650 651 /* 652 * Clear the error state registers for this CPU. 653 * For Cheetah, just clear the AFSR 654 */ 655 void 656 set_cpu_error_state(ch_cpu_errors_t *cpu_error_regs) 657 { 658 set_asyncflt(cpu_error_regs->afsr & ~C_AFSR_FATAL_ERRS); 659 } 660 661 /* 662 * For Cheetah, the error recovery code uses an alternate flush area in the 663 * TL>0 fast ECC handler. ecache_tl1_flushaddr is the physical address of 664 * this exclusive displacement flush area. 665 */ 666 uint64_t ecache_tl1_flushaddr = (uint64_t)-1; /* physaddr for E$ flushing */ 667 668 /* 669 * Allocate and initialize the exclusive displacement flush area. 670 * Called twice. The first time allocates virtual address. The second 671 * call looks up the physical address. 672 */ 673 caddr_t 674 ecache_init_scrub_flush_area(caddr_t alloc_base) 675 { 676 static caddr_t ecache_tl1_virtaddr; 677 678 if (alloc_base != NULL) { 679 /* 680 * Need to allocate an exclusive flush area that is twice the 681 * largest supported E$ size, physically contiguous, and 682 * aligned on twice the largest E$ size boundary. 683 */ 684 unsigned size = 2 * CH_ECACHE_8M_SIZE; 685 caddr_t va = (caddr_t)roundup((uintptr_t)alloc_base, size); 686 687 ecache_tl1_virtaddr = va; 688 alloc_base = va + size; 689 690 } else { 691 /* 692 * Get the physical address of the exclusive flush area. 693 */ 694 ASSERT(ecache_tl1_virtaddr != NULL); 695 ecache_tl1_flushaddr = va_to_pa(ecache_tl1_virtaddr); 696 ASSERT(ecache_tl1_flushaddr != ((uint64_t)-1)); 697 } 698 699 return (alloc_base); 700 } 701 702 /* 703 * Update cpu_offline_set so the scrubber knows which cpus are offline 704 */ 705 /*ARGSUSED*/ 706 int 707 cpu_scrub_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 708 { 709 switch (what) { 710 case CPU_ON: 711 case CPU_INIT: 712 CPUSET_DEL(cpu_offline_set, cpuid); 713 break; 714 case CPU_OFF: 715 CPUSET_ADD(cpu_offline_set, cpuid); 716 break; 717 default: 718 break; 719 } 720 return (0); 721 } 722