1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/ddi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/archsystm.h> 33 #include <sys/vmsystm.h> 34 #include <sys/machparam.h> 35 #include <sys/machsystm.h> 36 #include <sys/machthread.h> 37 #include <sys/cpu.h> 38 #include <sys/cmp.h> 39 #include <sys/elf_SPARC.h> 40 #include <vm/vm_dep.h> 41 #include <vm/hat_sfmmu.h> 42 #include <vm/seg_kpm.h> 43 #include <sys/cpuvar.h> 44 #include <sys/opl_olympus_regs.h> 45 #include <sys/opl_module.h> 46 #include <sys/async.h> 47 #include <sys/cmn_err.h> 48 #include <sys/debug.h> 49 #include <sys/dditypes.h> 50 #include <sys/cpu_module.h> 51 #include <sys/sysmacros.h> 52 #include <sys/intreg.h> 53 #include <sys/clock.h> 54 #include <sys/platform_module.h> 55 #include <sys/ontrap.h> 56 #include <sys/panic.h> 57 #include <sys/memlist.h> 58 #include <sys/ndifm.h> 59 #include <sys/ddifm.h> 60 #include <sys/fm/protocol.h> 61 #include <sys/fm/util.h> 62 #include <sys/fm/cpu/SPARC64-VI.h> 63 #include <sys/dtrace.h> 64 #include <sys/watchpoint.h> 65 #include <sys/promif.h> 66 67 /* 68 * Internal functions. 69 */ 70 static int cpu_sync_log_err(void *flt); 71 static void cpu_payload_add_aflt(struct async_flt *, nvlist_t *, nvlist_t *); 72 static void opl_cpu_sync_error(struct regs *, ulong_t, ulong_t, uint_t, uint_t); 73 static int cpu_flt_in_memory(opl_async_flt_t *, uint64_t); 74 75 /* 76 * Error counters resetting interval. 77 */ 78 static int opl_async_check_interval = 60; /* 1 min */ 79 80 uint_t cpu_impl_dual_pgsz = 1; 81 82 /* 83 * PA[22:0] represent Displacement in Jupiter 84 * configuration space. 85 */ 86 uint_t root_phys_addr_lo_mask = 0x7fffffu; 87 88 /* 89 * set in /etc/system to control logging of user BERR/TO's 90 */ 91 int cpu_berr_to_verbose = 0; 92 93 static int min_ecache_size; 94 static uint_t priv_hcl_1; 95 static uint_t priv_hcl_2; 96 static uint_t priv_hcl_4; 97 static uint_t priv_hcl_8; 98 99 /* 100 * Olympus error log 101 */ 102 static opl_errlog_t *opl_err_log; 103 104 /* 105 * UE is classified into four classes (MEM, CHANNEL, CPU, PATH). 106 * No any other ecc_type_info insertion is allowed in between the following 107 * four UE classess. 108 */ 109 ecc_type_to_info_t ecc_type_to_info[] = { 110 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 111 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 112 FM_EREPORT_CPU_UE_MEM, 113 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 114 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 115 FM_EREPORT_CPU_UE_CHANNEL, 116 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 117 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 118 FM_EREPORT_CPU_UE_CPU, 119 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 120 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 121 FM_EREPORT_CPU_UE_PATH, 122 SFSR_BERR, "BERR ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 123 "Bus Error", FM_EREPORT_PAYLOAD_SYNC, 124 FM_EREPORT_CPU_BERR, 125 SFSR_TO, "TO ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 126 "Bus Timeout", FM_EREPORT_PAYLOAD_SYNC, 127 FM_EREPORT_CPU_BTO, 128 SFSR_TLB_MUL, "TLB_MUL ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 129 "TLB MultiHit", FM_EREPORT_PAYLOAD_SYNC, 130 FM_EREPORT_CPU_MTLB, 131 SFSR_TLB_PRT, "TLB_PRT ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 132 "TLB Parity", FM_EREPORT_PAYLOAD_SYNC, 133 FM_EREPORT_CPU_TLBP, 134 135 UGESR_IAUG_CRE, "IAUG_CRE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 136 "IAUG CRE", FM_EREPORT_PAYLOAD_URGENT, 137 FM_EREPORT_CPU_CRE, 138 UGESR_IAUG_TSBCTXT, "IAUG_TSBCTXT", 139 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 140 "IAUG TSBCTXT", FM_EREPORT_PAYLOAD_URGENT, 141 FM_EREPORT_CPU_TSBCTX, 142 UGESR_IUG_TSBP, "IUG_TSBP", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 143 "IUG TSBP", FM_EREPORT_PAYLOAD_URGENT, 144 FM_EREPORT_CPU_TSBP, 145 UGESR_IUG_PSTATE, "IUG_PSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 146 "IUG PSTATE", FM_EREPORT_PAYLOAD_URGENT, 147 FM_EREPORT_CPU_PSTATE, 148 UGESR_IUG_TSTATE, "IUG_TSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 149 "IUG TSTATE", FM_EREPORT_PAYLOAD_URGENT, 150 FM_EREPORT_CPU_TSTATE, 151 UGESR_IUG_F, "IUG_F", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 152 "IUG FREG", FM_EREPORT_PAYLOAD_URGENT, 153 FM_EREPORT_CPU_IUG_F, 154 UGESR_IUG_R, "IUG_R", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 155 "IUG RREG", FM_EREPORT_PAYLOAD_URGENT, 156 FM_EREPORT_CPU_IUG_R, 157 UGESR_AUG_SDC, "AUG_SDC", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 158 "AUG SDC", FM_EREPORT_PAYLOAD_URGENT, 159 FM_EREPORT_CPU_SDC, 160 UGESR_IUG_WDT, "IUG_WDT", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 161 "IUG WDT", FM_EREPORT_PAYLOAD_URGENT, 162 FM_EREPORT_CPU_WDT, 163 UGESR_IUG_DTLB, "IUG_DTLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 164 "IUG DTLB", FM_EREPORT_PAYLOAD_URGENT, 165 FM_EREPORT_CPU_DTLB, 166 UGESR_IUG_ITLB, "IUG_ITLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 167 "IUG ITLB", FM_EREPORT_PAYLOAD_URGENT, 168 FM_EREPORT_CPU_ITLB, 169 UGESR_IUG_COREERR, "IUG_COREERR", 170 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 171 "IUG COREERR", FM_EREPORT_PAYLOAD_URGENT, 172 FM_EREPORT_CPU_CORE, 173 UGESR_MULTI_DAE, "MULTI_DAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 174 "MULTI DAE", FM_EREPORT_PAYLOAD_URGENT, 175 FM_EREPORT_CPU_DAE, 176 UGESR_MULTI_IAE, "MULTI_IAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 177 "MULTI IAE", FM_EREPORT_PAYLOAD_URGENT, 178 FM_EREPORT_CPU_IAE, 179 UGESR_MULTI_UGE, "MULTI_UGE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 180 "MULTI UGE", FM_EREPORT_PAYLOAD_URGENT, 181 FM_EREPORT_CPU_UGE, 182 0, NULL, 0, 0, 183 NULL, 0, 0, 184 }; 185 186 int (*p2get_mem_info)(int synd_code, uint64_t paddr, 187 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 188 int *segsp, int *banksp, int *mcidp); 189 190 191 /* 192 * Setup trap handlers for 0xA, 0x32, 0x40 trap types. 193 */ 194 void 195 cpu_init_trap(void) 196 { 197 OPL_SET_TRAP(tt0_iae, opl_serr_instr); 198 OPL_SET_TRAP(tt1_iae, opl_serr_instr); 199 OPL_SET_TRAP(tt0_dae, opl_serr_instr); 200 OPL_SET_TRAP(tt1_dae, opl_serr_instr); 201 OPL_SET_TRAP(tt0_asdat, opl_ugerr_instr); 202 OPL_SET_TRAP(tt1_asdat, opl_ugerr_instr); 203 } 204 205 static int 206 getintprop(pnode_t node, char *name, int deflt) 207 { 208 int value; 209 210 switch (prom_getproplen(node, name)) { 211 case sizeof (int): 212 (void) prom_getprop(node, name, (caddr_t)&value); 213 break; 214 215 default: 216 value = deflt; 217 break; 218 } 219 220 return (value); 221 } 222 223 /* 224 * Set the magic constants of the implementation. 225 */ 226 /*ARGSUSED*/ 227 void 228 cpu_fiximp(pnode_t dnode) 229 { 230 int i, a; 231 extern int vac_size, vac_shift; 232 extern uint_t vac_mask; 233 234 static struct { 235 char *name; 236 int *var; 237 int defval; 238 } prop[] = { 239 "l1-dcache-size", &dcache_size, OPL_DCACHE_SIZE, 240 "l1-dcache-line-size", &dcache_linesize, OPL_DCACHE_LSIZE, 241 "l1-icache-size", &icache_size, OPL_ICACHE_SIZE, 242 "l1-icache-line-size", &icache_linesize, OPL_ICACHE_LSIZE, 243 "l2-cache-size", &ecache_size, OPL_ECACHE_SIZE, 244 "l2-cache-line-size", &ecache_alignsize, OPL_ECACHE_LSIZE, 245 "l2-cache-associativity", &ecache_associativity, OPL_ECACHE_NWAY 246 }; 247 248 for (i = 0; i < sizeof (prop) / sizeof (prop[0]); i++) 249 *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval); 250 251 ecache_setsize = ecache_size / ecache_associativity; 252 253 vac_size = OPL_VAC_SIZE; 254 vac_mask = MMU_PAGEMASK & (vac_size - 1); 255 i = 0; a = vac_size; 256 while (a >>= 1) 257 ++i; 258 vac_shift = i; 259 shm_alignment = vac_size; 260 vac = 1; 261 } 262 263 #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 264 /* 265 * Quick and dirty way to redefine locally in 266 * OPL the value of IDSR_BN_SETS to 31 instead 267 * of the standard 32 value. This is to workaround 268 * REV_B of Olympus_c processor's problem in handling 269 * more than 31 xcall broadcast. 270 */ 271 #undef IDSR_BN_SETS 272 #define IDSR_BN_SETS 31 273 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 274 275 void 276 send_mondo_set(cpuset_t set) 277 { 278 int lo, busy, nack, shipped = 0; 279 uint16_t i, cpuids[IDSR_BN_SETS]; 280 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 281 uint64_t starttick, endtick, tick, lasttick; 282 #if (NCPU > IDSR_BN_SETS) 283 int index = 0; 284 int ncpuids = 0; 285 #endif 286 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 287 int bn_sets = IDSR_BN_SETS; 288 uint64_t ver; 289 290 ASSERT(NCPU > bn_sets); 291 #endif 292 293 ASSERT(!CPUSET_ISNULL(set)); 294 starttick = lasttick = gettick(); 295 296 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 297 ver = ultra_getver(); 298 if (((ULTRA_VER_IMPL(ver)) == OLYMPUS_C_IMPL) && 299 ((OLYMPUS_REV_MASK(ver)) == OLYMPUS_C_A)) 300 bn_sets = 1; 301 #endif 302 303 #if (NCPU <= IDSR_BN_SETS) 304 for (i = 0; i < NCPU; i++) 305 if (CPU_IN_SET(set, i)) { 306 shipit(i, shipped); 307 nackmask |= IDSR_NACK_BIT(shipped); 308 cpuids[shipped++] = i; 309 CPUSET_DEL(set, i); 310 if (CPUSET_ISNULL(set)) 311 break; 312 } 313 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 314 #else 315 for (i = 0; i < NCPU; i++) 316 if (CPU_IN_SET(set, i)) { 317 ncpuids++; 318 319 /* 320 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 321 * find we have shipped to more than (IDSR_BN_SETS) 322 * CPUs, set "index" to the highest numbered CPU in 323 * the set so we can ship to other CPUs a bit later on. 324 */ 325 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 326 if (shipped < bn_sets) { 327 #else 328 if (shipped < IDSR_BN_SETS) { 329 #endif 330 shipit(i, shipped); 331 nackmask |= IDSR_NACK_BIT(shipped); 332 cpuids[shipped++] = i; 333 CPUSET_DEL(set, i); 334 if (CPUSET_ISNULL(set)) 335 break; 336 } else 337 index = (int)i; 338 } 339 340 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 341 #endif 342 343 busymask = IDSR_NACK_TO_BUSY(nackmask); 344 busy = nack = 0; 345 endtick = starttick + xc_tick_limit; 346 for (;;) { 347 idsr = getidsr(); 348 #if (NCPU <= IDSR_BN_SETS) 349 if (idsr == 0) 350 break; 351 #else 352 if (idsr == 0 && shipped == ncpuids) 353 break; 354 #endif 355 tick = gettick(); 356 /* 357 * If there is a big jump between the current tick 358 * count and lasttick, we have probably hit a break 359 * point. Adjust endtick accordingly to avoid panic. 360 */ 361 if (tick > (lasttick + xc_tick_jump_limit)) 362 endtick += (tick - lasttick); 363 lasttick = tick; 364 if (tick > endtick) { 365 if (panic_quiesce) 366 return; 367 cmn_err(CE_CONT, "send mondo timeout " 368 "[%d NACK %d BUSY]\nIDSR 0x%" 369 "" PRIx64 " cpuids:", nack, busy, idsr); 370 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 371 for (i = 0; i < bn_sets; i++) { 372 #else 373 for (i = 0; i < IDSR_BN_SETS; i++) { 374 #endif 375 if (idsr & (IDSR_NACK_BIT(i) | 376 IDSR_BUSY_BIT(i))) { 377 cmn_err(CE_CONT, " 0x%x", 378 cpuids[i]); 379 } 380 } 381 cmn_err(CE_CONT, "\n"); 382 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 383 } 384 curnack = idsr & nackmask; 385 curbusy = idsr & busymask; 386 387 #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 388 /* 389 * Only proceed to send more xcalls if all the 390 * cpus in the previous IDSR_BN_SETS were completed. 391 */ 392 if (curbusy) { 393 busy++; 394 continue; 395 } 396 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 397 398 #if (NCPU > IDSR_BN_SETS) 399 if (shipped < ncpuids) { 400 uint64_t cpus_left; 401 uint16_t next = (uint16_t)index; 402 403 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 404 busymask; 405 406 if (cpus_left) { 407 do { 408 /* 409 * Sequence through and ship to the 410 * remainder of the CPUs in the system 411 * (e.g. other than the first 412 * (IDSR_BN_SETS)) in reverse order. 413 */ 414 lo = lowbit(cpus_left) - 1; 415 i = IDSR_BUSY_IDX(lo); 416 shipit(next, i); 417 shipped++; 418 cpuids[i] = next; 419 420 /* 421 * If we've processed all the CPUs, 422 * exit the loop now and save 423 * instructions. 424 */ 425 if (shipped == ncpuids) 426 break; 427 428 for ((index = ((int)next - 1)); 429 index >= 0; index--) 430 if (CPU_IN_SET(set, index)) { 431 next = (uint16_t)index; 432 break; 433 } 434 435 cpus_left &= ~(1ull << lo); 436 } while (cpus_left); 437 continue; 438 } 439 } 440 #endif 441 #ifndef OLYMPUS_C_REV_B_ERRATA_XCALL 442 if (curbusy) { 443 busy++; 444 continue; 445 } 446 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 447 #ifdef SEND_MONDO_STATS 448 { 449 int n = gettick() - starttick; 450 if (n < 8192) 451 x_nack_stimes[n >> 7]++; 452 } 453 #endif 454 while (gettick() < (tick + sys_clock_mhz)) 455 ; 456 do { 457 lo = lowbit(curnack) - 1; 458 i = IDSR_NACK_IDX(lo); 459 shipit(cpuids[i], i); 460 curnack &= ~(1ull << lo); 461 } while (curnack); 462 nack++; 463 busy = 0; 464 } 465 #ifdef SEND_MONDO_STATS 466 { 467 int n = gettick() - starttick; 468 if (n < 8192) 469 x_set_stimes[n >> 7]++; 470 else 471 x_set_ltimes[(n >> 13) & 0xf]++; 472 } 473 x_set_cpus[shipped]++; 474 #endif 475 } 476 477 /* 478 * Cpu private initialization. 479 */ 480 void 481 cpu_init_private(struct cpu *cp) 482 { 483 if (!(IS_OLYMPUS_C(cpunodes[cp->cpu_id].implementation))) { 484 cmn_err(CE_PANIC, "CPU%d Impl %d: Only SPARC64-VI is supported", 485 cp->cpu_id, cpunodes[cp->cpu_id].implementation); 486 } 487 488 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 489 } 490 491 void 492 cpu_setup(void) 493 { 494 extern int at_flags; 495 extern int disable_delay_tlb_flush, delay_tlb_flush; 496 extern int cpc_has_overflow_intr; 497 extern int disable_text_largepages; 498 extern int use_text_pgsz4m; 499 uint64_t cpu0_log; 500 extern uint64_t opl_cpu0_err_log; 501 502 /* 503 * Initialize Error log Scratch register for error handling. 504 */ 505 506 cpu0_log = va_to_pa(&opl_cpu0_err_log); 507 opl_error_setup(cpu0_log); 508 509 /* 510 * Enable MMU translating multiple page sizes for 511 * sITLB and sDTLB. 512 */ 513 opl_mpg_enable(); 514 515 /* 516 * Setup chip-specific trap handlers. 517 */ 518 cpu_init_trap(); 519 520 cache |= (CACHE_VAC | CACHE_PTAG | CACHE_IOCOHERENT); 521 522 at_flags = EF_SPARC_32PLUS | EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3; 523 524 /* 525 * Due to the number of entries in the fully-associative tlb 526 * this may have to be tuned lower than in spitfire. 527 */ 528 pp_slots = MIN(8, MAXPP_SLOTS); 529 530 /* 531 * Block stores do not invalidate all pages of the d$, pagecopy 532 * et. al. need virtual translations with virtual coloring taken 533 * into consideration. prefetch/ldd will pollute the d$ on the 534 * load side. 535 */ 536 pp_consistent_coloring = PPAGE_STORE_VCOLORING | PPAGE_LOADS_POLLUTE; 537 538 if (use_page_coloring) { 539 do_pg_coloring = 1; 540 if (use_virtual_coloring) 541 do_virtual_coloring = 1; 542 } 543 544 isa_list = 545 "sparcv9+vis2 sparcv9+vis sparcv9 " 546 "sparcv8plus+vis2 sparcv8plus+vis sparcv8plus " 547 "sparcv8 sparcv8-fsmuld sparcv7 sparc"; 548 549 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2; 550 551 /* 552 * On SPARC64-VI, there's no hole in the virtual address space 553 */ 554 hole_start = hole_end = 0; 555 556 /* 557 * The kpm mapping window. 558 * kpm_size: 559 * The size of a single kpm range. 560 * The overall size will be: kpm_size * vac_colors. 561 * kpm_vbase: 562 * The virtual start address of the kpm range within the kernel 563 * virtual address space. kpm_vbase has to be kpm_size aligned. 564 */ 565 kpm_size = (size_t)(128ull * 1024 * 1024 * 1024 * 1024); /* 128TB */ 566 kpm_size_shift = 47; 567 kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8EB */ 568 kpm_smallpages = 1; 569 570 /* 571 * The traptrace code uses either %tick or %stick for 572 * timestamping. We have %stick so we can use it. 573 */ 574 traptrace_use_stick = 1; 575 576 /* 577 * SPARC64-VI has a performance counter overflow interrupt 578 */ 579 cpc_has_overflow_intr = 1; 580 581 /* 582 * Use SPARC64-VI flush-all support 583 */ 584 if (!disable_delay_tlb_flush) 585 delay_tlb_flush = 1; 586 587 /* 588 * Declare that this architecture/cpu combination does not support 589 * fpRAS. 590 */ 591 fpras_implemented = 0; 592 593 /* 594 * Enable 4M pages to be used for mapping user text by default. Don't 595 * use large pages for initialized data segments since we may not know 596 * at exec() time what should be the preferred large page size for DTLB 597 * programming. 598 */ 599 use_text_pgsz4m = 1; 600 disable_text_largepages = (1 << TTE64K) | (1 << TTE512K) | 601 (1 << TTE32M) | (1 << TTE256M); 602 } 603 604 /* 605 * Called by setcpudelay 606 */ 607 void 608 cpu_init_tick_freq(void) 609 { 610 /* 611 * For SPARC64-VI we want to use the system clock rate as 612 * the basis for low level timing, due to support of mixed 613 * speed CPUs and power managment. 614 */ 615 if (system_clock_freq == 0) 616 cmn_err(CE_PANIC, "setcpudelay: invalid system_clock_freq"); 617 618 sys_tick_freq = system_clock_freq; 619 } 620 621 #ifdef SEND_MONDO_STATS 622 uint32_t x_one_stimes[64]; 623 uint32_t x_one_ltimes[16]; 624 uint32_t x_set_stimes[64]; 625 uint32_t x_set_ltimes[16]; 626 uint32_t x_set_cpus[NCPU]; 627 uint32_t x_nack_stimes[64]; 628 #endif 629 630 /* 631 * Note: A version of this function is used by the debugger via the KDI, 632 * and must be kept in sync with this version. Any changes made to this 633 * function to support new chips or to accomodate errata must also be included 634 * in the KDI-specific version. See us3_kdi.c. 635 */ 636 void 637 send_one_mondo(int cpuid) 638 { 639 int busy, nack; 640 uint64_t idsr, starttick, endtick, tick, lasttick; 641 uint64_t busymask; 642 643 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 644 starttick = lasttick = gettick(); 645 shipit(cpuid, 0); 646 endtick = starttick + xc_tick_limit; 647 busy = nack = 0; 648 busymask = IDSR_BUSY; 649 for (;;) { 650 idsr = getidsr(); 651 if (idsr == 0) 652 break; 653 654 tick = gettick(); 655 /* 656 * If there is a big jump between the current tick 657 * count and lasttick, we have probably hit a break 658 * point. Adjust endtick accordingly to avoid panic. 659 */ 660 if (tick > (lasttick + xc_tick_jump_limit)) 661 endtick += (tick - lasttick); 662 lasttick = tick; 663 if (tick > endtick) { 664 if (panic_quiesce) 665 return; 666 cmn_err(CE_PANIC, "send mondo timeout " 667 "(target 0x%x) [%d NACK %d BUSY]", 668 cpuid, nack, busy); 669 } 670 671 if (idsr & busymask) { 672 busy++; 673 continue; 674 } 675 drv_usecwait(1); 676 shipit(cpuid, 0); 677 nack++; 678 busy = 0; 679 } 680 #ifdef SEND_MONDO_STATS 681 { 682 int n = gettick() - starttick; 683 if (n < 8192) 684 x_one_stimes[n >> 7]++; 685 else 686 x_one_ltimes[(n >> 13) & 0xf]++; 687 } 688 #endif 689 } 690 691 /* 692 * init_mmu_page_sizes is set to one after the bootup time initialization 693 * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a 694 * valid value. 695 * 696 * mmu_disable_ism_large_pages and mmu_disable_large_pages are the mmu-specific 697 * versions of disable_ism_large_pages and disable_large_pages, and feed back 698 * into those two hat variables at hat initialization time. 699 * 700 */ 701 int init_mmu_page_sizes = 0; 702 static int mmu_disable_ism_large_pages = ((1 << TTE64K) | 703 (1 << TTE512K) | (1 << TTE256M)); 704 static int mmu_disable_large_pages = 0; 705 706 /* 707 * Re-initialize mmu_page_sizes and friends, for SPARC64-VI mmu support. 708 * Called during very early bootup from check_cpus_set(). 709 * Can be called to verify that mmu_page_sizes are set up correctly. 710 * 711 * Set Olympus defaults. We do not use the function parameter. 712 */ 713 /*ARGSUSED*/ 714 int 715 mmu_init_mmu_page_sizes(int32_t not_used) 716 { 717 if (!init_mmu_page_sizes) { 718 mmu_page_sizes = MMU_PAGE_SIZES; 719 mmu_hashcnt = MAX_HASHCNT; 720 mmu_ism_pagesize = MMU_PAGESIZE32M; 721 mmu_exported_pagesize_mask = (1 << TTE8K) | 722 (1 << TTE64K) | (1 << TTE512K) | (1 << TTE4M) | 723 (1 << TTE32M) | (1 << TTE256M); 724 init_mmu_page_sizes = 1; 725 return (0); 726 } 727 return (1); 728 } 729 730 /* SPARC64-VI worst case DTLB parameters */ 731 #ifndef LOCKED_DTLB_ENTRIES 732 #define LOCKED_DTLB_ENTRIES 5 /* 2 user TSBs, 2 nucleus, + OBP */ 733 #endif 734 #define TOTAL_DTLB_ENTRIES 32 735 #define AVAIL_32M_ENTRIES 0 736 #define AVAIL_256M_ENTRIES 0 737 #define AVAIL_DTLB_ENTRIES (TOTAL_DTLB_ENTRIES - LOCKED_DTLB_ENTRIES) 738 static uint64_t ttecnt_threshold[MMU_PAGE_SIZES] = { 739 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 740 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 741 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES}; 742 743 size_t 744 mmu_map_pgsz(size_t pgsize) 745 { 746 struct proc *p = curproc; 747 struct as *as = p->p_as; 748 struct hat *hat = as->a_hat; 749 uint_t pgsz0, pgsz1; 750 size_t size0, size1; 751 752 ASSERT(mmu_page_sizes == max_mmu_page_sizes); 753 pgsz0 = hat->sfmmu_pgsz[0]; 754 pgsz1 = hat->sfmmu_pgsz[1]; 755 size0 = hw_page_array[pgsz0].hp_size; 756 size1 = hw_page_array[pgsz1].hp_size; 757 /* Allow use of a larger pagesize if neither TLB is reprogrammed. */ 758 if ((pgsz0 == TTE8K) && (pgsz1 == TTE8K)) { 759 return (pgsize); 760 /* Allow use of requested pagesize if TLB is reprogrammed to it. */ 761 } else if ((pgsize == size0) || (pgsize == size1)) { 762 return (pgsize); 763 /* Use larger reprogrammed TLB size if pgsize is atleast that big. */ 764 } else if (pgsz1 > pgsz0) { 765 if (pgsize >= size1) 766 return (size1); 767 /* Use smaller reprogrammed TLB size if pgsize is atleast that big. */ 768 } else { 769 if (pgsize >= size0) 770 return (size0); 771 } 772 return (pgsize); 773 } 774 775 /* 776 * The function returns the mmu-specific values for the 777 * hat's disable_large_pages and disable_ism_large_pages variables. 778 */ 779 int 780 mmu_large_pages_disabled(uint_t flag) 781 { 782 int pages_disable = 0; 783 784 if (flag == HAT_LOAD) { 785 pages_disable = mmu_disable_large_pages; 786 } else if (flag == HAT_LOAD_SHARE) { 787 pages_disable = mmu_disable_ism_large_pages; 788 } 789 return (pages_disable); 790 } 791 792 /* 793 * mmu_init_large_pages is called with the desired ism_pagesize parameter. 794 * It may be called from set_platform_defaults, if some value other than 32M 795 * is desired. mmu_ism_pagesize is the tunable. If it has a bad value, 796 * then only warn, since it would be bad form to panic due to a user typo. 797 * 798 * The function re-initializes the mmu_disable_ism_large_pages variable. 799 */ 800 void 801 mmu_init_large_pages(size_t ism_pagesize) 802 { 803 switch (ism_pagesize) { 804 case MMU_PAGESIZE4M: 805 mmu_disable_ism_large_pages = ((1 << TTE64K) | 806 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 807 break; 808 case MMU_PAGESIZE32M: 809 mmu_disable_ism_large_pages = ((1 << TTE64K) | 810 (1 << TTE512K) | (1 << TTE256M)); 811 break; 812 case MMU_PAGESIZE256M: 813 mmu_disable_ism_large_pages = ((1 << TTE64K) | 814 (1 << TTE512K) | (1 << TTE32M)); 815 break; 816 default: 817 cmn_err(CE_WARN, "Unrecognized mmu_ism_pagesize value 0x%lx", 818 ism_pagesize); 819 break; 820 } 821 } 822 823 /*ARGSUSED*/ 824 uint_t 825 mmu_preferred_pgsz(struct hat *hat, caddr_t addr, size_t len) 826 { 827 sfmmu_t *sfmmup = (sfmmu_t *)hat; 828 uint_t pgsz0, pgsz1; 829 uint_t szc, maxszc = mmu_page_sizes - 1; 830 size_t pgsz; 831 extern int disable_large_pages; 832 833 pgsz0 = (uint_t)sfmmup->sfmmu_pgsz[0]; 834 pgsz1 = (uint_t)sfmmup->sfmmu_pgsz[1]; 835 836 /* 837 * If either of the TLBs are reprogrammed, choose 838 * the largest mapping size as the preferred size, 839 * if it fits the size and alignment constraints. 840 * Else return the largest mapping size that fits, 841 * if neither TLB is reprogrammed. 842 */ 843 if (pgsz0 > TTE8K || pgsz1 > TTE8K) { 844 if (pgsz1 > pgsz0) { /* First try pgsz1 */ 845 pgsz = hw_page_array[pgsz1].hp_size; 846 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 847 return (pgsz1); 848 } 849 if (pgsz0 > TTE8K) { /* Then try pgsz0, if !TTE8K */ 850 pgsz = hw_page_array[pgsz0].hp_size; 851 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 852 return (pgsz0); 853 } 854 } else { /* Otherwise pick best fit if neither TLB is reprogrammed. */ 855 for (szc = maxszc; szc > TTE8K; szc--) { 856 if (disable_large_pages & (1 << szc)) 857 continue; 858 859 pgsz = hw_page_array[szc].hp_size; 860 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 861 return (szc); 862 } 863 } 864 return (TTE8K); 865 } 866 867 /* 868 * Function to reprogram the TLBs when page sizes used 869 * by a process change significantly. 870 */ 871 void 872 mmu_setup_page_sizes(struct hat *hat, uint64_t *ttecnt) 873 { 874 extern int page_szc(size_t); 875 uint8_t pgsz0, pgsz1; 876 877 /* 878 * Don't program 2nd dtlb for kernel and ism hat 879 */ 880 if (hat->sfmmu_ismhat || hat == ksfmmup) 881 return; 882 883 /* 884 * hat->sfmmu_pgsz[] is an array whose elements 885 * contain a sorted order of page sizes. Element 886 * 0 is the most commonly used page size, followed 887 * by element 1, and so on. 888 * 889 * ttecnt[] is an array of per-page-size page counts 890 * mapped into the process. 891 * 892 * If the HAT's choice for page sizes is unsuitable, 893 * we can override it here. The new values written 894 * to the array will be handed back to us later to 895 * do the actual programming of the TLB hardware. 896 * 897 */ 898 pgsz0 = (uint8_t)MIN(hat->sfmmu_pgsz[0], hat->sfmmu_pgsz[1]); 899 pgsz1 = (uint8_t)MAX(hat->sfmmu_pgsz[0], hat->sfmmu_pgsz[1]); 900 901 /* 902 * This implements PAGESIZE programming of the sTLB 903 * if large TTE counts don't exceed the thresholds. 904 */ 905 if (ttecnt[pgsz0] < ttecnt_threshold[pgsz0]) 906 pgsz0 = page_szc(MMU_PAGESIZE); 907 if (ttecnt[pgsz1] < ttecnt_threshold[pgsz1]) 908 pgsz1 = page_szc(MMU_PAGESIZE); 909 hat->sfmmu_pgsz[0] = pgsz0; 910 hat->sfmmu_pgsz[1] = pgsz1; 911 /* otherwise, accept what the HAT chose for us */ 912 } 913 914 /* 915 * The HAT calls this function when an MMU context is allocated so that we 916 * can reprogram the large TLBs appropriately for the new process using 917 * the context. 918 * 919 * The caller must hold the HAT lock. 920 */ 921 void 922 mmu_set_ctx_page_sizes(struct hat *hat) 923 { 924 uint8_t pgsz0, pgsz1; 925 uint8_t new_cext; 926 927 ASSERT(sfmmu_hat_lock_held(hat)); 928 /* 929 * Don't program 2nd dtlb for kernel and ism hat 930 */ 931 if (hat->sfmmu_ismhat || hat == ksfmmup) 932 return; 933 934 /* 935 * If supported, reprogram the TLBs to a larger pagesize. 936 */ 937 pgsz0 = hat->sfmmu_pgsz[0]; 938 pgsz1 = hat->sfmmu_pgsz[1]; 939 ASSERT(pgsz0 < mmu_page_sizes); 940 ASSERT(pgsz1 < mmu_page_sizes); 941 new_cext = TAGACCEXT_MKSZPAIR(pgsz1, pgsz0); 942 if (hat->sfmmu_cext != new_cext) { 943 #ifdef DEBUG 944 int i; 945 /* 946 * assert cnum should be invalid, this is because pagesize 947 * can only be changed after a proc's ctxs are invalidated. 948 */ 949 for (i = 0; i < max_mmu_ctxdoms; i++) { 950 ASSERT(hat->sfmmu_ctxs[i].cnum == INVALID_CONTEXT); 951 } 952 #endif /* DEBUG */ 953 hat->sfmmu_cext = new_cext; 954 } 955 /* 956 * sfmmu_setctx_sec() will take care of the 957 * rest of the dirty work for us. 958 */ 959 } 960 961 /* 962 * Return processor specific async error structure 963 * size used. 964 */ 965 int 966 cpu_aflt_size(void) 967 { 968 return (sizeof (opl_async_flt_t)); 969 } 970 971 /* 972 * The cpu_sync_log_err() function is called via the [uc]e_drain() function to 973 * post-process CPU events that are dequeued. As such, it can be invoked 974 * from softint context, from AST processing in the trap() flow, or from the 975 * panic flow. We decode the CPU-specific data, and take appropriate actions. 976 * Historically this entry point was used to log the actual cmn_err(9F) text; 977 * now with FMA it is used to prepare 'flt' to be converted into an ereport. 978 * With FMA this function now also returns a flag which indicates to the 979 * caller whether the ereport should be posted (1) or suppressed (0). 980 */ 981 /*ARGSUSED*/ 982 static int 983 cpu_sync_log_err(void *flt) 984 { 985 opl_async_flt_t *opl_flt = (opl_async_flt_t *)flt; 986 struct async_flt *aflt = (struct async_flt *)flt; 987 988 /* 989 * No extra processing of urgent error events. 990 * Always generate ereports for these events. 991 */ 992 if (aflt->flt_status == OPL_ECC_URGENT_TRAP) 993 return (1); 994 995 /* 996 * Additional processing for synchronous errors. 997 */ 998 switch (opl_flt->flt_type) { 999 case OPL_CPU_INV_SFSR: 1000 return (1); 1001 1002 case OPL_CPU_SYNC_UE: 1003 /* 1004 * The validity: SFSR_MK_UE bit has been checked 1005 * in opl_cpu_sync_error() 1006 * No more check is required. 1007 * 1008 * opl_flt->flt_eid_mod and flt_eid_sid have been set by H/W, 1009 * and they have been retrieved in cpu_queue_events() 1010 */ 1011 1012 if (opl_flt->flt_eid_mod == OPL_ERRID_MEM) { 1013 ASSERT(aflt->flt_in_memory); 1014 /* 1015 * We want to skip logging only if ALL the following 1016 * conditions are true: 1017 * 1018 * 1. We are not panicing already. 1019 * 2. The error is a memory error. 1020 * 3. There is only one error. 1021 * 4. The error is on a retired page. 1022 * 5. The error occurred under on_trap 1023 * protection AFLT_PROT_EC 1024 */ 1025 if (!panicstr && aflt->flt_prot == AFLT_PROT_EC && 1026 page_retire_check(aflt->flt_addr, NULL) == 0) { 1027 /* 1028 * Do not log an error from 1029 * the retired page 1030 */ 1031 softcall(ecc_page_zero, (void *)aflt->flt_addr); 1032 return (0); 1033 } 1034 if (!panicstr) 1035 cpu_page_retire(opl_flt); 1036 } 1037 return (1); 1038 1039 case OPL_CPU_SYNC_OTHERS: 1040 /* 1041 * For the following error cases, the processor HW does 1042 * not set the flt_eid_mod/flt_eid_sid. Instead, SW will attempt 1043 * to assign appropriate values here to reflect what we 1044 * think is the most likely cause of the problem w.r.t to 1045 * the particular error event. For Buserr and timeout 1046 * error event, we will assign OPL_ERRID_CHANNEL as the 1047 * most likely reason. For TLB parity or multiple hit 1048 * error events, we will assign the reason as 1049 * OPL_ERRID_CPU (cpu related problem) and set the 1050 * flt_eid_sid to point to the cpuid. 1051 */ 1052 1053 if (opl_flt->flt_bit & (SFSR_BERR|SFSR_TO)) { 1054 /* 1055 * flt_eid_sid will not be used for this case. 1056 */ 1057 opl_flt->flt_eid_mod = OPL_ERRID_CHANNEL; 1058 } 1059 if (opl_flt->flt_bit & (SFSR_TLB_MUL|SFSR_TLB_PRT)) { 1060 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1061 opl_flt->flt_eid_sid = aflt->flt_inst; 1062 } 1063 1064 /* 1065 * In case of no effective error bit 1066 */ 1067 if ((opl_flt->flt_bit & SFSR_ERRS) == 0) { 1068 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1069 opl_flt->flt_eid_sid = aflt->flt_inst; 1070 } 1071 break; 1072 1073 default: 1074 return (1); 1075 } 1076 return (1); 1077 } 1078 1079 /* 1080 * Retire the bad page that may contain the flushed error. 1081 */ 1082 void 1083 cpu_page_retire(opl_async_flt_t *opl_flt) 1084 { 1085 struct async_flt *aflt = (struct async_flt *)opl_flt; 1086 (void) page_retire(aflt->flt_addr, PR_UE); 1087 } 1088 1089 /* 1090 * Invoked by error_init() early in startup and therefore before 1091 * startup_errorq() is called to drain any error Q - 1092 * 1093 * startup() 1094 * startup_end() 1095 * error_init() 1096 * cpu_error_init() 1097 * errorq_init() 1098 * errorq_drain() 1099 * start_other_cpus() 1100 * 1101 * The purpose of this routine is to create error-related taskqs. Taskqs 1102 * are used for this purpose because cpu_lock can't be grabbed from interrupt 1103 * context. 1104 * 1105 */ 1106 /*ARGSUSED*/ 1107 void 1108 cpu_error_init(int items) 1109 { 1110 opl_err_log = (opl_errlog_t *) 1111 kmem_alloc(ERRLOG_ALLOC_SZ, KM_SLEEP); 1112 if ((uint64_t)opl_err_log & MMU_PAGEOFFSET) 1113 cmn_err(CE_PANIC, "The base address of the error log " 1114 "is not page aligned"); 1115 } 1116 1117 /* 1118 * We route all errors through a single switch statement. 1119 */ 1120 void 1121 cpu_ue_log_err(struct async_flt *aflt) 1122 { 1123 switch (aflt->flt_class) { 1124 case CPU_FAULT: 1125 if (cpu_sync_log_err(aflt)) 1126 cpu_ereport_post(aflt); 1127 break; 1128 1129 case BUS_FAULT: 1130 bus_async_log_err(aflt); 1131 break; 1132 1133 default: 1134 cmn_err(CE_WARN, "discarding async error %p with invalid " 1135 "fault class (0x%x)", (void *)aflt, aflt->flt_class); 1136 return; 1137 } 1138 } 1139 1140 /* 1141 * Routine for panic hook callback from panic_idle(). 1142 * 1143 * Nothing to do here. 1144 */ 1145 void 1146 cpu_async_panic_callb(void) 1147 { 1148 } 1149 1150 /* 1151 * Routine to return a string identifying the physical name 1152 * associated with a memory/cache error. 1153 */ 1154 /*ARGSUSED*/ 1155 int 1156 cpu_get_mem_unum(int synd_status, ushort_t flt_synd, uint64_t flt_stat, 1157 uint64_t flt_addr, int flt_bus_id, int flt_in_memory, 1158 ushort_t flt_status, char *buf, int buflen, int *lenp) 1159 { 1160 int synd_code; 1161 int ret; 1162 1163 /* 1164 * An AFSR of -1 defaults to a memory syndrome. 1165 */ 1166 synd_code = (int)flt_synd; 1167 1168 if (&plat_get_mem_unum) { 1169 if ((ret = plat_get_mem_unum(synd_code, flt_addr, flt_bus_id, 1170 flt_in_memory, flt_status, buf, buflen, lenp)) != 0) { 1171 buf[0] = '\0'; 1172 *lenp = 0; 1173 } 1174 return (ret); 1175 } 1176 buf[0] = '\0'; 1177 *lenp = 0; 1178 return (ENOTSUP); 1179 } 1180 1181 /* 1182 * Wrapper for cpu_get_mem_unum() routine that takes an 1183 * async_flt struct rather than explicit arguments. 1184 */ 1185 int 1186 cpu_get_mem_unum_aflt(int synd_status, struct async_flt *aflt, 1187 char *buf, int buflen, int *lenp) 1188 { 1189 /* 1190 * We always pass -1 so that cpu_get_mem_unum will interpret this as a 1191 * memory error. 1192 */ 1193 return (cpu_get_mem_unum(synd_status, aflt->flt_synd, 1194 (uint64_t)-1, 1195 aflt->flt_addr, aflt->flt_bus_id, aflt->flt_in_memory, 1196 aflt->flt_status, buf, buflen, lenp)); 1197 } 1198 1199 /* 1200 * This routine is a more generic interface to cpu_get_mem_unum() 1201 * that may be used by other modules (e.g. mm). 1202 */ 1203 /*ARGSUSED*/ 1204 int 1205 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1206 char *buf, int buflen, int *lenp) 1207 { 1208 int synd_status, flt_in_memory, ret; 1209 ushort_t flt_status = 0; 1210 char unum[UNUM_NAMLEN]; 1211 1212 /* 1213 * Check for an invalid address. 1214 */ 1215 if (afar == (uint64_t)-1) 1216 return (ENXIO); 1217 1218 if (synd == (uint64_t)-1) 1219 synd_status = AFLT_STAT_INVALID; 1220 else 1221 synd_status = AFLT_STAT_VALID; 1222 1223 flt_in_memory = (*afsr & SFSR_MEMORY) && 1224 pf_is_memory(afar >> MMU_PAGESHIFT); 1225 1226 ret = cpu_get_mem_unum(synd_status, (ushort_t)synd, *afsr, afar, 1227 CPU->cpu_id, flt_in_memory, flt_status, unum, 1228 UNUM_NAMLEN, lenp); 1229 if (ret != 0) 1230 return (ret); 1231 1232 if (*lenp >= buflen) 1233 return (ENAMETOOLONG); 1234 1235 (void) strncpy(buf, unum, buflen); 1236 1237 return (0); 1238 } 1239 1240 /* 1241 * Routine to return memory information associated 1242 * with a physical address and syndrome. 1243 */ 1244 /*ARGSUSED*/ 1245 int 1246 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1247 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1248 int *segsp, int *banksp, int *mcidp) 1249 { 1250 int synd_code = (int)synd; 1251 1252 if (afar == (uint64_t)-1) 1253 return (ENXIO); 1254 1255 if (p2get_mem_info != NULL) 1256 return ((p2get_mem_info)(synd_code, afar, 1257 mem_sizep, seg_sizep, bank_sizep, 1258 segsp, banksp, mcidp)); 1259 else 1260 return (ENOTSUP); 1261 } 1262 1263 /* 1264 * Routine to return a string identifying the physical 1265 * name associated with a cpuid. 1266 */ 1267 int 1268 cpu_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 1269 { 1270 int ret; 1271 char unum[UNUM_NAMLEN]; 1272 1273 if (&plat_get_cpu_unum) { 1274 if ((ret = plat_get_cpu_unum(cpuid, unum, UNUM_NAMLEN, lenp)) 1275 != 0) 1276 return (ret); 1277 } else { 1278 return (ENOTSUP); 1279 } 1280 1281 if (*lenp >= buflen) 1282 return (ENAMETOOLONG); 1283 1284 (void) strncpy(buf, unum, *lenp); 1285 1286 return (0); 1287 } 1288 1289 /* 1290 * This routine exports the name buffer size. 1291 */ 1292 size_t 1293 cpu_get_name_bufsize() 1294 { 1295 return (UNUM_NAMLEN); 1296 } 1297 1298 /* 1299 * Flush the entire ecache by ASI_L2_CNTL.U2_FLUSH 1300 */ 1301 void 1302 cpu_flush_ecache(void) 1303 { 1304 flush_ecache(ecache_flushaddr, cpunodes[CPU->cpu_id].ecache_size, 1305 cpunodes[CPU->cpu_id].ecache_linesize); 1306 } 1307 1308 static uint8_t 1309 flt_to_trap_type(struct async_flt *aflt) 1310 { 1311 if (aflt->flt_status & OPL_ECC_ISYNC_TRAP) 1312 return (TRAP_TYPE_ECC_I); 1313 if (aflt->flt_status & OPL_ECC_DSYNC_TRAP) 1314 return (TRAP_TYPE_ECC_D); 1315 if (aflt->flt_status & OPL_ECC_URGENT_TRAP) 1316 return (TRAP_TYPE_URGENT); 1317 return (-1); 1318 } 1319 1320 /* 1321 * Encode the data saved in the opl_async_flt_t struct into 1322 * the FM ereport payload. 1323 */ 1324 /* ARGSUSED */ 1325 static void 1326 cpu_payload_add_aflt(struct async_flt *aflt, nvlist_t *payload, 1327 nvlist_t *resource) 1328 { 1329 opl_async_flt_t *opl_flt = (opl_async_flt_t *)aflt; 1330 char unum[UNUM_NAMLEN]; 1331 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1332 int len; 1333 1334 1335 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFSR) { 1336 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFSR, 1337 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1338 } 1339 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFAR) { 1340 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFAR, 1341 DATA_TYPE_UINT64, aflt->flt_addr, NULL); 1342 } 1343 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_UGESR) { 1344 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_UGESR, 1345 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1346 } 1347 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PC) { 1348 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PC, 1349 DATA_TYPE_UINT64, (uint64_t)aflt->flt_pc, NULL); 1350 } 1351 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TL) { 1352 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TL, 1353 DATA_TYPE_UINT8, (uint8_t)aflt->flt_tl, NULL); 1354 } 1355 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TT) { 1356 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TT, 1357 DATA_TYPE_UINT8, flt_to_trap_type(aflt), NULL); 1358 } 1359 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PRIV) { 1360 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PRIV, 1361 DATA_TYPE_BOOLEAN_VALUE, 1362 (aflt->flt_priv ? B_TRUE : B_FALSE), NULL); 1363 } 1364 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_FLT_STATUS) { 1365 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FLT_STATUS, 1366 DATA_TYPE_UINT64, (uint64_t)aflt->flt_status, NULL); 1367 } 1368 1369 switch (opl_flt->flt_eid_mod) { 1370 case OPL_ERRID_CPU: 1371 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1372 (u_longlong_t)cpunodes[opl_flt->flt_eid_sid].device_id); 1373 (void) fm_fmri_cpu_set(resource, FM_CPU_SCHEME_VERSION, 1374 NULL, opl_flt->flt_eid_sid, 1375 (uint8_t *)&cpunodes[opl_flt->flt_eid_sid].version, 1376 sbuf); 1377 fm_payload_set(payload, 1378 FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1379 DATA_TYPE_NVLIST, resource, NULL); 1380 break; 1381 1382 case OPL_ERRID_CHANNEL: 1383 /* 1384 * No resource is created but the cpumem DE will find 1385 * the defective path by retreiving EID from SFSR which is 1386 * included in the payload. 1387 */ 1388 break; 1389 1390 case OPL_ERRID_MEM: 1391 (void) cpu_get_mem_unum_aflt(0, aflt, unum, UNUM_NAMLEN, &len); 1392 (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1393 NULL, unum, NULL, (uint64_t)-1); 1394 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1395 DATA_TYPE_NVLIST, resource, NULL); 1396 break; 1397 1398 case OPL_ERRID_PATH: 1399 /* 1400 * No resource is created but the cpumem DE will find 1401 * the defective path by retreiving EID from SFSR which is 1402 * included in the payload. 1403 */ 1404 break; 1405 } 1406 } 1407 1408 /* 1409 * Returns whether fault address is valid for this error bit and 1410 * whether the address is "in memory" (i.e. pf_is_memory returns 1). 1411 */ 1412 /*ARGSUSED*/ 1413 static int 1414 cpu_flt_in_memory(opl_async_flt_t *opl_flt, uint64_t t_afsr_bit) 1415 { 1416 struct async_flt *aflt = (struct async_flt *)opl_flt; 1417 1418 if (aflt->flt_status & (OPL_ECC_SYNC_TRAP)) { 1419 return ((t_afsr_bit & SFSR_MEMORY) && 1420 pf_is_memory(aflt->flt_addr >> MMU_PAGESHIFT)); 1421 } 1422 return (0); 1423 } 1424 1425 /* 1426 * In OPL SCF does the stick synchronization. 1427 */ 1428 void 1429 sticksync_slave(void) 1430 { 1431 } 1432 1433 /* 1434 * In OPL SCF does the stick synchronization. 1435 */ 1436 void 1437 sticksync_master(void) 1438 { 1439 } 1440 1441 /* 1442 * Cpu private unitialization. OPL cpus do not use the private area. 1443 */ 1444 void 1445 cpu_uninit_private(struct cpu *cp) 1446 { 1447 cmp_delete_cpu(cp->cpu_id); 1448 } 1449 1450 /* 1451 * Always flush an entire cache. 1452 */ 1453 void 1454 cpu_error_ecache_flush(void) 1455 { 1456 cpu_flush_ecache(); 1457 } 1458 1459 void 1460 cpu_ereport_post(struct async_flt *aflt) 1461 { 1462 char *cpu_type, buf[FM_MAX_CLASS]; 1463 nv_alloc_t *nva = NULL; 1464 nvlist_t *ereport, *detector, *resource; 1465 errorq_elem_t *eqep; 1466 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1467 1468 if (aflt->flt_panic || panicstr) { 1469 eqep = errorq_reserve(ereport_errorq); 1470 if (eqep == NULL) 1471 return; 1472 ereport = errorq_elem_nvl(ereport_errorq, eqep); 1473 nva = errorq_elem_nva(ereport_errorq, eqep); 1474 } else { 1475 ereport = fm_nvlist_create(nva); 1476 } 1477 1478 /* 1479 * Create the scheme "cpu" FMRI. 1480 */ 1481 detector = fm_nvlist_create(nva); 1482 resource = fm_nvlist_create(nva); 1483 switch (cpunodes[aflt->flt_inst].implementation) { 1484 case OLYMPUS_C_IMPL: 1485 cpu_type = FM_EREPORT_CPU_SPARC64_VI; 1486 break; 1487 default: 1488 cpu_type = FM_EREPORT_CPU_UNSUPPORTED; 1489 break; 1490 } 1491 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1492 (u_longlong_t)cpunodes[aflt->flt_inst].device_id); 1493 (void) fm_fmri_cpu_set(detector, FM_CPU_SCHEME_VERSION, NULL, 1494 aflt->flt_inst, (uint8_t *)&cpunodes[aflt->flt_inst].version, 1495 sbuf); 1496 1497 /* 1498 * Encode all the common data into the ereport. 1499 */ 1500 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", 1501 FM_ERROR_CPU, cpu_type, aflt->flt_erpt_class); 1502 1503 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 1504 fm_ena_generate(aflt->flt_id, FM_ENA_FMT1), detector, NULL); 1505 1506 /* 1507 * Encode the error specific data that was saved in 1508 * the async_flt structure into the ereport. 1509 */ 1510 cpu_payload_add_aflt(aflt, ereport, resource); 1511 1512 if (aflt->flt_panic || panicstr) { 1513 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 1514 } else { 1515 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 1516 fm_nvlist_destroy(ereport, FM_NVA_FREE); 1517 fm_nvlist_destroy(detector, FM_NVA_FREE); 1518 fm_nvlist_destroy(resource, FM_NVA_FREE); 1519 } 1520 } 1521 1522 void 1523 cpu_run_bus_error_handlers(struct async_flt *aflt, int expected) 1524 { 1525 int status; 1526 ddi_fm_error_t de; 1527 1528 bzero(&de, sizeof (ddi_fm_error_t)); 1529 1530 de.fme_version = DDI_FME_VERSION; 1531 de.fme_ena = fm_ena_generate(aflt->flt_id, FM_ENA_FMT1); 1532 de.fme_flag = expected; 1533 de.fme_bus_specific = (void *)aflt->flt_addr; 1534 status = ndi_fm_handler_dispatch(ddi_root_node(), NULL, &de); 1535 if ((aflt->flt_prot == AFLT_PROT_NONE) && (status == DDI_FM_FATAL)) 1536 aflt->flt_panic = 1; 1537 } 1538 1539 void 1540 cpu_errorq_dispatch(char *error_class, void *payload, size_t payload_sz, 1541 errorq_t *eqp, uint_t flag) 1542 { 1543 struct async_flt *aflt = (struct async_flt *)payload; 1544 1545 aflt->flt_erpt_class = error_class; 1546 errorq_dispatch(eqp, payload, payload_sz, flag); 1547 } 1548 1549 void 1550 adjust_hw_copy_limits(int ecache_size) 1551 { 1552 /* 1553 * Set hw copy limits. 1554 * 1555 * /etc/system will be parsed later and can override one or more 1556 * of these settings. 1557 * 1558 * At this time, ecache size seems only mildly relevant. 1559 * We seem to run into issues with the d-cache and stalls 1560 * we see on misses. 1561 * 1562 * Cycle measurement indicates that 2 byte aligned copies fare 1563 * little better than doing things with VIS at around 512 bytes. 1564 * 4 byte aligned shows promise until around 1024 bytes. 8 Byte 1565 * aligned is faster whenever the source and destination data 1566 * in cache and the total size is less than 2 Kbytes. The 2K 1567 * limit seems to be driven by the 2K write cache. 1568 * When more than 2K of copies are done in non-VIS mode, stores 1569 * backup in the write cache. In VIS mode, the write cache is 1570 * bypassed, allowing faster cache-line writes aligned on cache 1571 * boundaries. 1572 * 1573 * In addition, in non-VIS mode, there is no prefetching, so 1574 * for larger copies, the advantage of prefetching to avoid even 1575 * occasional cache misses is enough to justify using the VIS code. 1576 * 1577 * During testing, it was discovered that netbench ran 3% slower 1578 * when hw_copy_limit_8 was 2K or larger. Apparently for server 1579 * applications, data is only used once (copied to the output 1580 * buffer, then copied by the network device off the system). Using 1581 * the VIS copy saves more L2 cache state. Network copies are 1582 * around 1.3K to 1.5K in size for historical reasons. 1583 * 1584 * Therefore, a limit of 1K bytes will be used for the 8 byte 1585 * aligned copy even for large caches and 8 MB ecache. The 1586 * infrastructure to allow different limits for different sized 1587 * caches is kept to allow further tuning in later releases. 1588 */ 1589 1590 if (min_ecache_size == 0 && use_hw_bcopy) { 1591 /* 1592 * First time through - should be before /etc/system 1593 * is read. 1594 * Could skip the checks for zero but this lets us 1595 * preserve any debugger rewrites. 1596 */ 1597 if (hw_copy_limit_1 == 0) { 1598 hw_copy_limit_1 = VIS_COPY_THRESHOLD; 1599 priv_hcl_1 = hw_copy_limit_1; 1600 } 1601 if (hw_copy_limit_2 == 0) { 1602 hw_copy_limit_2 = 2 * VIS_COPY_THRESHOLD; 1603 priv_hcl_2 = hw_copy_limit_2; 1604 } 1605 if (hw_copy_limit_4 == 0) { 1606 hw_copy_limit_4 = 4 * VIS_COPY_THRESHOLD; 1607 priv_hcl_4 = hw_copy_limit_4; 1608 } 1609 if (hw_copy_limit_8 == 0) { 1610 hw_copy_limit_8 = 4 * VIS_COPY_THRESHOLD; 1611 priv_hcl_8 = hw_copy_limit_8; 1612 } 1613 min_ecache_size = ecache_size; 1614 } else { 1615 /* 1616 * MP initialization. Called *after* /etc/system has 1617 * been parsed. One CPU has already been initialized. 1618 * Need to cater for /etc/system having scragged one 1619 * of our values. 1620 */ 1621 if (ecache_size == min_ecache_size) { 1622 /* 1623 * Same size ecache. We do nothing unless we 1624 * have a pessimistic ecache setting. In that 1625 * case we become more optimistic (if the cache is 1626 * large enough). 1627 */ 1628 if (hw_copy_limit_8 == 4 * VIS_COPY_THRESHOLD) { 1629 /* 1630 * Need to adjust hw_copy_limit* from our 1631 * pessimistic uniprocessor value to a more 1632 * optimistic UP value *iff* it hasn't been 1633 * reset. 1634 */ 1635 if ((ecache_size > 1048576) && 1636 (priv_hcl_8 == hw_copy_limit_8)) { 1637 if (ecache_size <= 2097152) 1638 hw_copy_limit_8 = 4 * 1639 VIS_COPY_THRESHOLD; 1640 else if (ecache_size <= 4194304) 1641 hw_copy_limit_8 = 4 * 1642 VIS_COPY_THRESHOLD; 1643 else 1644 hw_copy_limit_8 = 4 * 1645 VIS_COPY_THRESHOLD; 1646 priv_hcl_8 = hw_copy_limit_8; 1647 } 1648 } 1649 } else if (ecache_size < min_ecache_size) { 1650 /* 1651 * A different ecache size. Can this even happen? 1652 */ 1653 if (priv_hcl_8 == hw_copy_limit_8) { 1654 /* 1655 * The previous value that we set 1656 * is unchanged (i.e., it hasn't been 1657 * scragged by /etc/system). Rewrite it. 1658 */ 1659 if (ecache_size <= 1048576) 1660 hw_copy_limit_8 = 8 * 1661 VIS_COPY_THRESHOLD; 1662 else if (ecache_size <= 2097152) 1663 hw_copy_limit_8 = 8 * 1664 VIS_COPY_THRESHOLD; 1665 else if (ecache_size <= 4194304) 1666 hw_copy_limit_8 = 8 * 1667 VIS_COPY_THRESHOLD; 1668 else 1669 hw_copy_limit_8 = 10 * 1670 VIS_COPY_THRESHOLD; 1671 priv_hcl_8 = hw_copy_limit_8; 1672 min_ecache_size = ecache_size; 1673 } 1674 } 1675 } 1676 } 1677 1678 #define VIS_BLOCKSIZE 64 1679 1680 int 1681 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 1682 { 1683 int ret, watched; 1684 1685 watched = watch_disable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1686 ret = dtrace_blksuword32(addr, data, 0); 1687 if (watched) 1688 watch_enable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1689 1690 return (ret); 1691 } 1692 1693 void 1694 opl_cpu_reg_init() 1695 { 1696 uint64_t this_cpu_log; 1697 1698 /* 1699 * We do not need to re-initialize cpu0 registers. 1700 */ 1701 if (cpu[getprocessorid()] == &cpu0) 1702 return; 1703 1704 /* 1705 * Initialize Error log Scratch register for error handling. 1706 */ 1707 1708 this_cpu_log = va_to_pa((void*)(((uint64_t)opl_err_log) + 1709 ERRLOG_BUFSZ * (getprocessorid()))); 1710 opl_error_setup(this_cpu_log); 1711 1712 /* 1713 * Enable MMU translating multiple page sizes for 1714 * sITLB and sDTLB. 1715 */ 1716 opl_mpg_enable(); 1717 } 1718 1719 /* 1720 * Queue one event in ue_queue based on ecc_type_to_info entry. 1721 */ 1722 static void 1723 cpu_queue_one_event(opl_async_flt_t *opl_flt, char *reason, 1724 ecc_type_to_info_t *eccp) 1725 { 1726 struct async_flt *aflt = (struct async_flt *)opl_flt; 1727 1728 if (reason && 1729 strlen(reason) + strlen(eccp->ec_reason) < MAX_REASON_STRING) { 1730 (void) strcat(reason, eccp->ec_reason); 1731 } 1732 1733 opl_flt->flt_bit = eccp->ec_afsr_bit; 1734 opl_flt->flt_type = eccp->ec_flt_type; 1735 aflt->flt_in_memory = cpu_flt_in_memory(opl_flt, opl_flt->flt_bit); 1736 aflt->flt_payload = eccp->ec_err_payload; 1737 1738 ASSERT(aflt->flt_status & (OPL_ECC_SYNC_TRAP|OPL_ECC_URGENT_TRAP)); 1739 cpu_errorq_dispatch(eccp->ec_err_class, 1740 (void *)opl_flt, sizeof (opl_async_flt_t), 1741 ue_queue, 1742 aflt->flt_panic); 1743 } 1744 1745 /* 1746 * Queue events on async event queue one event per error bit. 1747 * Return number of events queued. 1748 */ 1749 int 1750 cpu_queue_events(opl_async_flt_t *opl_flt, char *reason, uint64_t t_afsr_errs) 1751 { 1752 struct async_flt *aflt = (struct async_flt *)opl_flt; 1753 ecc_type_to_info_t *eccp; 1754 int nevents = 0; 1755 1756 /* 1757 * Queue expected errors, error bit and fault type must must match 1758 * in the ecc_type_to_info table. 1759 */ 1760 for (eccp = ecc_type_to_info; t_afsr_errs != 0 && eccp->ec_desc != NULL; 1761 eccp++) { 1762 if ((eccp->ec_afsr_bit & t_afsr_errs) != 0 && 1763 (eccp->ec_flags & aflt->flt_status) != 0) { 1764 /* 1765 * UE error event can be further 1766 * classified/breakdown into finer granularity 1767 * based on the flt_eid_mod value set by HW. We do 1768 * special handling here so that we can report UE 1769 * error in finer granularity as ue_mem, 1770 * ue_channel, ue_cpu or ue_path. 1771 */ 1772 if (eccp->ec_flt_type == OPL_CPU_SYNC_UE) { 1773 opl_flt->flt_eid_mod = 1774 (aflt->flt_stat & SFSR_EID_MOD) 1775 >> SFSR_EID_MOD_SHIFT; 1776 opl_flt->flt_eid_sid = 1777 (aflt->flt_stat & SFSR_EID_SID) 1778 >> SFSR_EID_SID_SHIFT; 1779 /* 1780 * Need to advance eccp pointer by flt_eid_mod 1781 * so that we get an appropriate ecc pointer 1782 * 1783 * EID # of advances 1784 * ---------------------------------- 1785 * OPL_ERRID_MEM 0 1786 * OPL_ERRID_CHANNEL 1 1787 * OPL_ERRID_CPU 2 1788 * OPL_ERRID_PATH 3 1789 */ 1790 eccp += opl_flt->flt_eid_mod; 1791 } 1792 cpu_queue_one_event(opl_flt, reason, eccp); 1793 t_afsr_errs &= ~eccp->ec_afsr_bit; 1794 nevents++; 1795 } 1796 } 1797 1798 return (nevents); 1799 } 1800 1801 /* 1802 * Sync. error wrapper functions. 1803 * We use these functions in order to transfer here from the 1804 * nucleus trap handler information about trap type (data or 1805 * instruction) and trap level (0 or above 0). This way we 1806 * get rid of using SFSR's reserved bits. 1807 */ 1808 1809 #define OPL_SYNC_TL0 0 1810 #define OPL_SYNC_TL1 1 1811 #define OPL_ISYNC_ERR 0 1812 #define OPL_DSYNC_ERR 1 1813 1814 void 1815 opl_cpu_isync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1816 { 1817 uint64_t t_sfar = p_sfar; 1818 uint64_t t_sfsr = p_sfsr; 1819 1820 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1821 OPL_SYNC_TL0, OPL_ISYNC_ERR); 1822 } 1823 1824 void 1825 opl_cpu_isync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1826 { 1827 uint64_t t_sfar = p_sfar; 1828 uint64_t t_sfsr = p_sfsr; 1829 1830 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1831 OPL_SYNC_TL1, OPL_ISYNC_ERR); 1832 } 1833 1834 void 1835 opl_cpu_dsync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1836 { 1837 uint64_t t_sfar = p_sfar; 1838 uint64_t t_sfsr = p_sfsr; 1839 1840 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1841 OPL_SYNC_TL0, OPL_DSYNC_ERR); 1842 } 1843 1844 void 1845 opl_cpu_dsync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1846 { 1847 uint64_t t_sfar = p_sfar; 1848 uint64_t t_sfsr = p_sfsr; 1849 1850 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1851 OPL_SYNC_TL1, OPL_DSYNC_ERR); 1852 } 1853 1854 /* 1855 * The fj sync err handler transfers control here for UE, BERR, TO, TLB_MUL 1856 * and TLB_PRT. 1857 * This function is designed based on cpu_deferred_error(). 1858 */ 1859 1860 static void 1861 opl_cpu_sync_error(struct regs *rp, ulong_t t_sfar, ulong_t t_sfsr, 1862 uint_t tl, uint_t derr) 1863 { 1864 opl_async_flt_t opl_flt; 1865 struct async_flt *aflt; 1866 int trampolined = 0; 1867 char pr_reason[MAX_REASON_STRING]; 1868 uint64_t log_sfsr; 1869 int expected = DDI_FM_ERR_UNEXPECTED; 1870 ddi_acc_hdl_t *hp; 1871 1872 /* 1873 * We need to look at p_flag to determine if the thread detected an 1874 * error while dumping core. We can't grab p_lock here, but it's ok 1875 * because we just need a consistent snapshot and we know that everyone 1876 * else will store a consistent set of bits while holding p_lock. We 1877 * don't have to worry about a race because SDOCORE is set once prior 1878 * to doing i/o from the process's address space and is never cleared. 1879 */ 1880 uint_t pflag = ttoproc(curthread)->p_flag; 1881 1882 pr_reason[0] = '\0'; 1883 1884 /* 1885 * handle the specific error 1886 */ 1887 bzero(&opl_flt, sizeof (opl_async_flt_t)); 1888 aflt = (struct async_flt *)&opl_flt; 1889 aflt->flt_id = gethrtime_waitfree(); 1890 aflt->flt_bus_id = getprocessorid(); 1891 aflt->flt_inst = CPU->cpu_id; 1892 aflt->flt_stat = t_sfsr; 1893 aflt->flt_addr = t_sfar; 1894 aflt->flt_pc = (caddr_t)rp->r_pc; 1895 aflt->flt_prot = (uchar_t)AFLT_PROT_NONE; 1896 aflt->flt_class = (uchar_t)CPU_FAULT; 1897 aflt->flt_priv = (uchar_t) 1898 (tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 1 : 0)); 1899 aflt->flt_tl = (uchar_t)tl; 1900 aflt->flt_panic = (uchar_t)(tl != 0 || aft_testfatal != 0 || 1901 (t_sfsr & (SFSR_TLB_MUL|SFSR_TLB_PRT)) != 0); 1902 aflt->flt_core = (pflag & SDOCORE) ? 1 : 0; 1903 aflt->flt_status = (derr) ? OPL_ECC_DSYNC_TRAP : OPL_ECC_ISYNC_TRAP; 1904 1905 /* 1906 * If SFSR.FV is not set, both SFSR and SFAR/SFPAR values are uncertain. 1907 * So, clear all error bits to avoid mis-handling and force the system 1908 * panicked. 1909 * We skip all the procedures below down to the panic message call. 1910 */ 1911 if (!(t_sfsr & SFSR_FV)) { 1912 opl_flt.flt_type = OPL_CPU_INV_SFSR; 1913 aflt->flt_panic = 1; 1914 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 1915 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, 1916 (void *)&opl_flt, sizeof (opl_async_flt_t), ue_queue, 1917 aflt->flt_panic); 1918 fm_panic("%sErrors(s)", "invalid SFSR"); 1919 } 1920 1921 /* 1922 * If either UE and MK bit is off, this is not valid UE error. 1923 * If it is not valid UE error, clear UE & MK_UE bits to prevent 1924 * mis-handling below. 1925 * aflt->flt_stat keeps the original bits as a reference. 1926 */ 1927 if ((t_sfsr & (SFSR_MK_UE|SFSR_UE)) != 1928 (SFSR_MK_UE|SFSR_UE)) { 1929 t_sfsr &= ~(SFSR_MK_UE|SFSR_UE); 1930 } 1931 1932 /* 1933 * If the trap occurred in privileged mode at TL=0, we need to check to 1934 * see if we were executing in the kernel under on_trap() or t_lofault 1935 * protection. If so, modify the saved registers so that we return 1936 * from the trap to the appropriate trampoline routine. 1937 */ 1938 if (!aflt->flt_panic && aflt->flt_priv && tl == 0) { 1939 if (curthread->t_ontrap != NULL) { 1940 on_trap_data_t *otp = curthread->t_ontrap; 1941 1942 if (otp->ot_prot & OT_DATA_EC) { 1943 aflt->flt_prot = (uchar_t)AFLT_PROT_EC; 1944 otp->ot_trap |= (ushort_t)OT_DATA_EC; 1945 rp->r_pc = otp->ot_trampoline; 1946 rp->r_npc = rp->r_pc + 4; 1947 trampolined = 1; 1948 } 1949 1950 if ((t_sfsr & (SFSR_TO | SFSR_BERR)) && 1951 (otp->ot_prot & OT_DATA_ACCESS)) { 1952 aflt->flt_prot = (uchar_t)AFLT_PROT_ACCESS; 1953 otp->ot_trap |= (ushort_t)OT_DATA_ACCESS; 1954 rp->r_pc = otp->ot_trampoline; 1955 rp->r_npc = rp->r_pc + 4; 1956 trampolined = 1; 1957 /* 1958 * for peeks and caut_gets errors are expected 1959 */ 1960 hp = (ddi_acc_hdl_t *)otp->ot_handle; 1961 if (!hp) 1962 expected = DDI_FM_ERR_PEEK; 1963 else if (hp->ah_acc.devacc_attr_access == 1964 DDI_CAUTIOUS_ACC) 1965 expected = DDI_FM_ERR_EXPECTED; 1966 } 1967 1968 } else if (curthread->t_lofault) { 1969 aflt->flt_prot = AFLT_PROT_COPY; 1970 rp->r_g1 = EFAULT; 1971 rp->r_pc = curthread->t_lofault; 1972 rp->r_npc = rp->r_pc + 4; 1973 trampolined = 1; 1974 } 1975 } 1976 1977 /* 1978 * If we're in user mode or we're doing a protected copy, we either 1979 * want the ASTON code below to send a signal to the user process 1980 * or we want to panic if aft_panic is set. 1981 * 1982 * If we're in privileged mode and we're not doing a copy, then we 1983 * need to check if we've trampolined. If we haven't trampolined, 1984 * we should panic. 1985 */ 1986 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 1987 if (t_sfsr & (SFSR_ERRS & ~(SFSR_BERR | SFSR_TO))) 1988 aflt->flt_panic |= aft_panic; 1989 } else if (!trampolined) { 1990 aflt->flt_panic = 1; 1991 } 1992 1993 /* 1994 * If we've trampolined due to a privileged TO or BERR, or if an 1995 * unprivileged TO or BERR occurred, we don't want to enqueue an 1996 * event for that TO or BERR. Queue all other events (if any) besides 1997 * the TO/BERR. 1998 */ 1999 log_sfsr = t_sfsr; 2000 if (trampolined) { 2001 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 2002 } else if (!aflt->flt_priv) { 2003 /* 2004 * User mode, suppress messages if 2005 * cpu_berr_to_verbose is not set. 2006 */ 2007 if (!cpu_berr_to_verbose) 2008 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 2009 } 2010 2011 if (((log_sfsr & SFSR_ERRS) && 2012 (cpu_queue_events(&opl_flt, pr_reason, t_sfsr) == 0)) || 2013 ((t_sfsr & SFSR_ERRS) == 0)) { 2014 opl_flt.flt_type = OPL_CPU_INV_SFSR; 2015 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 2016 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, 2017 (void *)&opl_flt, sizeof (opl_async_flt_t), ue_queue, 2018 aflt->flt_panic); 2019 } 2020 2021 if (t_sfsr & (SFSR_UE|SFSR_TO|SFSR_BERR)) { 2022 cpu_run_bus_error_handlers(aflt, expected); 2023 } 2024 2025 /* 2026 * Panic here if aflt->flt_panic has been set. Enqueued errors will 2027 * be logged as part of the panic flow. 2028 */ 2029 if (aflt->flt_panic) { 2030 if (pr_reason[0] == 0) 2031 strcpy(pr_reason, "invalid SFSR "); 2032 2033 fm_panic("%sErrors(s)", pr_reason); 2034 } 2035 2036 /* 2037 * If we queued an error and we are going to return from the trap and 2038 * the error was in user mode or inside of a copy routine, set AST flag 2039 * so the queue will be drained before returning to user mode. The 2040 * AST processing will also act on our failure policy. 2041 */ 2042 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 2043 int pcb_flag = 0; 2044 2045 if (t_sfsr & (SFSR_ERRS & 2046 ~(SFSR_BERR | SFSR_TO))) 2047 pcb_flag |= ASYNC_HWERR; 2048 2049 if (t_sfsr & SFSR_BERR) 2050 pcb_flag |= ASYNC_BERR; 2051 2052 if (t_sfsr & SFSR_TO) 2053 pcb_flag |= ASYNC_BTO; 2054 2055 ttolwp(curthread)->lwp_pcb.pcb_flags |= pcb_flag; 2056 aston(curthread); 2057 } 2058 } 2059 2060 /*ARGSUSED*/ 2061 void 2062 opl_cpu_urgent_error(struct regs *rp, ulong_t p_ugesr, ulong_t tl) 2063 { 2064 opl_async_flt_t opl_flt; 2065 struct async_flt *aflt; 2066 char pr_reason[MAX_REASON_STRING]; 2067 2068 /* normalize tl */ 2069 tl = (tl >= 2 ? 1 : 0); 2070 pr_reason[0] = '\0'; 2071 2072 bzero(&opl_flt, sizeof (opl_async_flt_t)); 2073 aflt = (struct async_flt *)&opl_flt; 2074 aflt->flt_id = gethrtime_waitfree(); 2075 aflt->flt_bus_id = getprocessorid(); 2076 aflt->flt_inst = CPU->cpu_id; 2077 aflt->flt_stat = p_ugesr; 2078 aflt->flt_pc = (caddr_t)rp->r_pc; 2079 aflt->flt_class = (uchar_t)CPU_FAULT; 2080 aflt->flt_tl = tl; 2081 aflt->flt_priv = (uchar_t) 2082 (tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 1 : 0)); 2083 aflt->flt_status = OPL_ECC_URGENT_TRAP; 2084 aflt->flt_panic = 1; 2085 /* 2086 * HW does not set mod/sid in case of urgent error. 2087 * So we have to set it here. 2088 */ 2089 opl_flt.flt_eid_mod = OPL_ERRID_CPU; 2090 opl_flt.flt_eid_sid = aflt->flt_inst; 2091 2092 if (cpu_queue_events(&opl_flt, pr_reason, p_ugesr) == 0) { 2093 opl_flt.flt_type = OPL_CPU_INV_UGESR; 2094 aflt->flt_payload = FM_EREPORT_PAYLOAD_URGENT; 2095 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_URG, 2096 (void *)&opl_flt, sizeof (opl_async_flt_t), 2097 ue_queue, aflt->flt_panic); 2098 } 2099 2100 fm_panic("Urgent Error"); 2101 } 2102 2103 /* 2104 * Initialization error counters resetting. 2105 */ 2106 /* ARGSUSED */ 2107 static void 2108 opl_ras_online(void *arg, cpu_t *cp, cyc_handler_t *hdlr, cyc_time_t *when) 2109 { 2110 hdlr->cyh_func = (cyc_func_t)ras_cntr_reset; 2111 hdlr->cyh_level = CY_LOW_LEVEL; 2112 hdlr->cyh_arg = (void *)(uintptr_t)cp->cpu_id; 2113 2114 when->cyt_when = cp->cpu_id * (((hrtime_t)NANOSEC * 10)/ NCPU); 2115 when->cyt_interval = (hrtime_t)NANOSEC * opl_async_check_interval; 2116 } 2117 2118 void 2119 cpu_mp_init(void) 2120 { 2121 cyc_omni_handler_t hdlr; 2122 2123 hdlr.cyo_online = opl_ras_online; 2124 hdlr.cyo_offline = NULL; 2125 hdlr.cyo_arg = NULL; 2126 mutex_enter(&cpu_lock); 2127 (void) cyclic_add_omni(&hdlr); 2128 mutex_exit(&cpu_lock); 2129 } 2130 2131 /*ARGSUSED*/ 2132 void 2133 mmu_init_kernel_pgsz(struct hat *hat) 2134 { 2135 } 2136 2137 size_t 2138 mmu_get_kernel_lpsize(size_t lpsize) 2139 { 2140 uint_t tte; 2141 2142 if (lpsize == 0) { 2143 /* no setting for segkmem_lpsize in /etc/system: use default */ 2144 return (MMU_PAGESIZE4M); 2145 } 2146 2147 for (tte = TTE8K; tte <= TTE4M; tte++) { 2148 if (lpsize == TTEBYTES(tte)) 2149 return (lpsize); 2150 } 2151 2152 return (TTEBYTES(TTE8K)); 2153 } 2154 2155 /* 2156 * The following are functions that are unused in 2157 * OPL cpu module. They are defined here to resolve 2158 * dependencies in the "unix" module. 2159 * Unused functions that should never be called in 2160 * OPL are coded with ASSERT(0). 2161 */ 2162 2163 void 2164 cpu_disable_errors(void) 2165 {} 2166 2167 void 2168 cpu_enable_errors(void) 2169 { ASSERT(0); } 2170 2171 /*ARGSUSED*/ 2172 void 2173 cpu_ce_scrub_mem_err(struct async_flt *ecc, boolean_t t) 2174 { ASSERT(0); } 2175 2176 /*ARGSUSED*/ 2177 void 2178 cpu_faulted_enter(struct cpu *cp) 2179 {} 2180 2181 /*ARGSUSED*/ 2182 void 2183 cpu_faulted_exit(struct cpu *cp) 2184 {} 2185 2186 /*ARGSUSED*/ 2187 void 2188 cpu_check_allcpus(struct async_flt *aflt) 2189 {} 2190 2191 /*ARGSUSED*/ 2192 void 2193 cpu_ce_log_err(struct async_flt *aflt, errorq_elem_t *t) 2194 { ASSERT(0); } 2195 2196 /*ARGSUSED*/ 2197 void 2198 cpu_check_ce(int flag, uint64_t pa, caddr_t va, uint_t psz) 2199 { ASSERT(0); } 2200 2201 /*ARGSUSED*/ 2202 void 2203 cpu_ce_count_unum(struct async_flt *ecc, int len, char *unum) 2204 { ASSERT(0); } 2205 2206 /*ARGSUSED*/ 2207 void 2208 cpu_busy_ecache_scrub(struct cpu *cp) 2209 {} 2210 2211 /*ARGSUSED*/ 2212 void 2213 cpu_idle_ecache_scrub(struct cpu *cp) 2214 {} 2215 2216 /* ARGSUSED */ 2217 void 2218 cpu_change_speed(uint64_t divisor, uint64_t arg2) 2219 { ASSERT(0); } 2220 2221 void 2222 cpu_init_cache_scrub(void) 2223 {} 2224 2225 /* ARGSUSED */ 2226 int 2227 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 2228 { 2229 if (&plat_get_mem_sid) { 2230 return (plat_get_mem_sid(unum, buf, buflen, lenp)); 2231 } else { 2232 return (ENOTSUP); 2233 } 2234 } 2235 2236 /* ARGSUSED */ 2237 int 2238 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 2239 { 2240 if (&plat_get_mem_addr) { 2241 return (plat_get_mem_addr(unum, sid, offset, addrp)); 2242 } else { 2243 return (ENOTSUP); 2244 } 2245 } 2246 2247 /* ARGSUSED */ 2248 int 2249 cpu_get_mem_offset(uint64_t flt_addr, uint64_t *offp) 2250 { 2251 if (&plat_get_mem_offset) { 2252 return (plat_get_mem_offset(flt_addr, offp)); 2253 } else { 2254 return (ENOTSUP); 2255 } 2256 } 2257 2258 /*ARGSUSED*/ 2259 void 2260 itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2261 { ASSERT(0); } 2262 2263 /*ARGSUSED*/ 2264 void 2265 dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2266 { ASSERT(0); } 2267 2268 /*ARGSUSED*/ 2269 void 2270 read_ecc_data(struct async_flt *aflt, short verbose, short ce_err) 2271 { ASSERT(0); } 2272 2273 /*ARGSUSED*/ 2274 int 2275 ce_scrub_xdiag_recirc(struct async_flt *aflt, errorq_t *eqp, 2276 errorq_elem_t *eqep, size_t afltoffset) 2277 { 2278 ASSERT(0); 2279 return (0); 2280 } 2281 2282 /*ARGSUSED*/ 2283 char * 2284 flt_to_error_type(struct async_flt *aflt) 2285 { 2286 ASSERT(0); 2287 return (NULL); 2288 } 2289