1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/sunddi.h> 32 #include <sys/esunddi.h> 33 #include <sys/sunndi.h> 34 #include <sys/ddi.h> 35 #include <sys/modctl.h> 36 #include <sys/sysmacros.h> 37 #include <sys/note.h> 38 39 #include <sys/platform_module.h> 40 #include <sys/errno.h> 41 #include <sys/i2c/clients/i2c_client.h> 42 #include <sys/cherrystone.h> 43 #include <sys/machsystm.h> 44 #include <sys/promif.h> 45 #include <vm/page.h> 46 #include <sys/memnode.h> 47 #include <vm/vm_dep.h> 48 49 /* Cherrystone Keyswitch Information */ 50 #define CHERRY_KEY_POLL_PORT 3 51 #define CHERRY_KEY_POLL_BIT 2 52 #define CHERRY_KEY_POLL_INTVL 10 53 54 #define SHARED_PCF8584_PATH "/pci@9,700000/ebus@1/i2c@1,2e/nvram@4,a4" 55 static dev_info_t *shared_pcf8584_dip; 56 static kmutex_t cherry_pcf8584_mutex; 57 58 static boolean_t key_locked_bit; 59 static clock_t keypoll_timeout_hz; 60 61 /* 62 * For software memory interleaving support. 63 */ 64 static void update_mem_bounds(int, int, int, uint64_t, uint64_t); 65 66 static uint64_t 67 slice_table[CHERRYSTONE_SBD_SLOTS][CHERRYSTONE_CPUS_PER_BOARD] 68 [CHERRYSTONE_BANKS_PER_MC][2]; 69 70 #define SLICE_PA 0 71 #define SLICE_SPAN 1 72 73 /* Function prototypes */ 74 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 75 76 int (*cherry_ssc050_get_port_bit) (dev_info_t *, int, int, uint8_t *, int); 77 extern void (*abort_seq_handler)(); 78 79 static int cherry_dev_search(dev_info_t *, void *); 80 static void keyswitch_poll(void *); 81 static void cherry_abort_seq_handler(char *msg); 82 83 /* Function definitions from this point forward. */ 84 85 int 86 set_platform_tsb_spares() 87 { 88 return (0); 89 } 90 91 void 92 startup_platform(void) 93 { 94 /* 95 * Disable an active h/w watchdog timer 96 * upon exit to OBP. 97 */ 98 extern int disable_watchdog_on_exit; 99 disable_watchdog_on_exit = 1; 100 101 mutex_init(&cherry_pcf8584_mutex, NULL, NULL, NULL); 102 } 103 104 #pragma weak mmu_init_large_pages 105 106 void 107 set_platform_defaults(void) 108 { 109 extern void mmu_init_large_pages(size_t); 110 111 if ((mmu_page_sizes == max_mmu_page_sizes) && 112 (mmu_ism_pagesize != MMU_PAGESIZE32M)) { 113 if (&mmu_init_large_pages) 114 mmu_init_large_pages(mmu_ism_pagesize); 115 } 116 } 117 118 void 119 load_platform_modules(void) 120 { 121 if (modload("drv", "pmc") < 0) { 122 cmn_err(CE_NOTE, "pmc driver failed to load"); 123 } 124 } 125 126 void 127 load_platform_drivers(void) 128 { 129 char **drv; 130 dev_info_t *i2cnexus_dip; 131 dev_info_t *keysw_dip = NULL; 132 133 static char *boot_time_drivers[] = { 134 "todds1287", 135 "mc-us3", 136 "ssc050", 137 NULL 138 }; 139 140 for (drv = boot_time_drivers; *drv; drv++) { 141 if (i_ddi_attach_hw_nodes(*drv) != DDI_SUCCESS) 142 cmn_err(CE_WARN, "Failed to install \"%s\" driver.", 143 *drv); 144 } 145 146 /* 147 * mc-us3 and ssc050 must stay loaded for plat_get_mem_unum() 148 * and keyswitch_poll() 149 */ 150 (void) ddi_hold_driver(ddi_name_to_major("mc-us3")); 151 (void) ddi_hold_driver(ddi_name_to_major("ssc050")); 152 153 /* Gain access into the ssc050_get_port function */ 154 cherry_ssc050_get_port_bit = (int (*) (dev_info_t *, int, int, 155 uint8_t *, int)) modgetsymvalue("ssc050_get_port_bit", 0); 156 if (cherry_ssc050_get_port_bit == NULL) { 157 cmn_err(CE_WARN, "cannot find ssc050_get_port_bit"); 158 return; 159 } 160 161 e_ddi_walk_driver("i2c-ssc050", cherry_dev_search, (void *)&keysw_dip); 162 ASSERT(keysw_dip != NULL); 163 164 keypoll_timeout_hz = drv_usectohz(10 * MICROSEC); 165 keyswitch_poll(keysw_dip); 166 abort_seq_handler = cherry_abort_seq_handler; 167 168 /* 169 * Figure out which pcf8584_dip is shared with OBP for the nvram 170 * device, so the lock can be acquired. 171 */ 172 173 i2cnexus_dip = e_ddi_hold_devi_by_path(SHARED_PCF8584_PATH, 0); 174 175 ASSERT(i2cnexus_dip != NULL); 176 shared_pcf8584_dip = ddi_get_parent(i2cnexus_dip); 177 178 ndi_hold_devi(shared_pcf8584_dip); 179 ndi_rele_devi(i2cnexus_dip); 180 } 181 182 static int 183 cherry_dev_search(dev_info_t *dip, void *arg) 184 { 185 int *dev_regs; /* Info about where the device is. */ 186 uint_t len; 187 int err; 188 189 if (strcmp(ddi_binding_name(dip), "i2c-ssc050") != 0) 190 return (DDI_WALK_CONTINUE); 191 192 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 193 DDI_PROP_DONTPASS, "reg", &dev_regs, &len); 194 if (err != DDI_PROP_SUCCESS) { 195 return (DDI_WALK_CONTINUE); 196 } 197 /* 198 * regs[0] contains the bus number and regs[1] 199 * contains the device address of the i2c device. 200 * 0x82 is the device address of the i2c device 201 * from which the key switch position is read. 202 */ 203 if (dev_regs[0] == 0 && dev_regs[1] == 0x82) { 204 *((dev_info_t **)arg) = dip; 205 ddi_prop_free(dev_regs); 206 return (DDI_WALK_TERMINATE); 207 } 208 ddi_prop_free(dev_regs); 209 return (DDI_WALK_CONTINUE); 210 } 211 212 static void 213 keyswitch_poll(void *arg) 214 { 215 dev_info_t *dip = arg; 216 uchar_t port_byte; 217 int port = CHERRY_KEY_POLL_PORT; 218 int bit = CHERRY_KEY_POLL_BIT; 219 int err; 220 221 err = cherry_ssc050_get_port_bit(dip, port, bit, 222 &port_byte, I2C_NOSLEEP); 223 if (err != 0) { 224 return; 225 } 226 227 key_locked_bit = (boolean_t)((port_byte & 0x1)); 228 timeout(keyswitch_poll, (caddr_t)dip, keypoll_timeout_hz); 229 } 230 231 static void 232 cherry_abort_seq_handler(char *msg) 233 { 234 if (key_locked_bit == 0) 235 cmn_err(CE_CONT, "KEY in LOCKED position, " 236 "ignoring debug enter sequence"); 237 else { 238 debug_enter(msg); 239 } 240 } 241 242 243 /*ARGSUSED*/ 244 int 245 plat_cpu_poweron(struct cpu *cp) 246 { 247 return (ENOTSUP); /* not supported on this platform */ 248 } 249 250 /*ARGSUSED*/ 251 int 252 plat_cpu_poweroff(struct cpu *cp) 253 { 254 return (ENOTSUP); /* not supported on this platform */ 255 } 256 257 /* 258 * Given a pfn, return the board and beginning/end of the page's 259 * memory controller's address range. 260 */ 261 static int 262 plat_discover_slice(pfn_t pfn, pfn_t *first, pfn_t *last) 263 { 264 int bd, cpu, bank; 265 266 for (bd = 0; bd < CHERRYSTONE_SBD_SLOTS; bd++) { 267 for (cpu = 0; cpu < CHERRYSTONE_CPUS_PER_BOARD; cpu++) { 268 for (bank = 0; bank < CHERRYSTONE_BANKS_PER_MC; 269 bank++) { 270 uint64_t *slice = slice_table[bd][cpu][bank]; 271 uint64_t base = btop(slice[SLICE_PA]); 272 uint64_t len = btop(slice[SLICE_SPAN]); 273 if (len && pfn >= base && pfn < (base + len)) { 274 *first = base; 275 *last = base + len - 1; 276 return (bd); 277 } 278 } 279 } 280 } 281 panic("plat_discover_slice: no slice for pfn 0x%lx\n", pfn); 282 /* NOTREACHED */ 283 } 284 285 /* 286 * This index is used to associate a given pfn to a place on the freelist. 287 * This results in dispersing pfn assignment over all the boards in the 288 * system. 289 * Choose the index randomly to prevent clustering pages of different 290 * colors on the same board. 291 */ 292 static uint_t random_idx(int ubound); 293 294 /* 295 * Theory of operation: 296 * - When the system walks the prom tree, it calls the platform 297 * function plat_fill_mc() for each memory-controller node found 298 * in map_wellknown(). 299 * - The plat_fill_mc() function interrogates the memory controller 300 * to find out if it controls memory. If it does, the physical 301 * address and span are recorded in a lookup table. 302 * - During VM init, the VM calls plat_freelist_process() to shuffle 303 * the page freelists. This is done after the page freelists are 304 * coalesced, but before the system goes live, since we need to be 305 * able to get the exclusive lock on all the pages. 306 * - plat_freelist_process() removes all pages from the freelists, 307 * and sorts them out into per-board freelists. It does this by 308 * using the lookup table that was built earlier. It then 309 * round-robins across the per-board freelists and frees each page, 310 * leaving an even distribution of pages across the system. 311 */ 312 void 313 plat_freelist_process(int mnode) 314 { 315 page_t *page, **freelist; 316 page_t *bdlist[CHERRYSTONE_SBD_SLOTS]; 317 page_t **sortlist[CHERRYSTONE_SBD_SLOTS]; 318 uint32_t idx, idy, size, color, max_color, lbn; 319 uint32_t bd_flags, bd_cnt, result, bds; 320 pfn_t slice_start, slice_end, pfn; 321 kmutex_t *pcm; 322 int mtype; 323 324 /* 325 * Sort through freelists one memory type and size at a time. 326 */ 327 for (mtype = 0; mtype < MAX_MEM_TYPES; mtype++) { 328 for (size = 0; size < mmu_page_sizes; size++) { 329 /* 330 * Compute the maximum # of phys colors based on 331 * page size. 332 */ 333 max_color = page_get_pagecolors(size); 334 335 /* 336 * Sort through freelists one color at a time. 337 */ 338 for (color = 0; color < max_color; color++) { 339 bd_cnt = 0; 340 bd_flags = 0; 341 slice_start = (pfn_t)-1; 342 slice_end = (pfn_t)-1; 343 344 for (idx = 0; idx < CHERRYSTONE_SBD_SLOTS; 345 idx++) { 346 bdlist[idx] = NULL; 347 sortlist[idx] = NULL; 348 } 349 350 freelist = &PAGE_FREELISTS(mnode, size, 351 color, mtype); 352 353 if (*freelist == NULL) 354 continue; 355 356 /* 357 * Acquire per-color freelist lock. 358 */ 359 pcm = PC_BIN_MUTEX(mnode, color, PG_FREE_LIST); 360 mutex_enter(pcm); 361 362 /* 363 * Go through freelist, sorting pages out 364 * into per-board lists. 365 */ 366 while (*freelist) { 367 page = *freelist; 368 result = page_trylock(page, SE_EXCL); 369 ASSERT(result); 370 371 /* 372 * Delete from freelist. 373 */ 374 if (size != 0) { 375 page_vpsub(freelist, page); 376 } else { 377 mach_page_sub(freelist, page); 378 } 379 380 pfn = page->p_pagenum; 381 if (pfn < slice_start || 382 pfn > slice_end) 383 lbn = plat_discover_slice(pfn, 384 &slice_start, &slice_end); 385 386 /* 387 * Add to per-board list. 388 */ 389 if (size != 0) { 390 page_vpadd(&bdlist[lbn], page); 391 } else { 392 mach_page_add(&bdlist[lbn], 393 page); 394 } 395 396 /* 397 * Seen this board yet? 398 */ 399 if ((bd_flags & (1 << lbn)) == 0) { 400 bd_flags |= (1 << lbn); 401 bd_cnt++; 402 } 403 page_unlock(page); 404 } 405 406 /* 407 * Make the sortlist so 408 * bd_cnt choices show up 409 */ 410 bds = 0; 411 for (idx = 0; idx < CHERRYSTONE_SBD_SLOTS; 412 idx++) { 413 if (bdlist[idx]) 414 sortlist[bds++] = &bdlist[idx]; 415 } 416 417 /* 418 * Set random start. 419 */ 420 (void) random_idx(-color); 421 422 /* 423 * now rebuild the freelist by shuffling 424 * pages from bd lists 425 */ 426 while (bd_cnt) { 427 /* 428 * get "random" index between 0 & 429 * bd_cnt 430 */ 431 ASSERT(bd_cnt && 432 (bd_cnt < CHERRYSTONE_SBD_SLOTS+1)); 433 434 idx = random_idx(bd_cnt); 435 436 page = *sortlist[idx]; 437 result = page_trylock(page, SE_EXCL); 438 ASSERT(result); 439 440 /* 441 * Delete from sort list and add 442 * to freelist. 443 */ 444 if (size != 0) { 445 page_vpsub(sortlist[idx], page); 446 page_vpadd(freelist, page); 447 } else { 448 mach_page_sub(sortlist[idx], 449 page); 450 mach_page_add(freelist, page); 451 } 452 453 pfn = page->p_pagenum; 454 if (pfn < slice_start || 455 pfn > slice_end) 456 lbn = plat_discover_slice(pfn, 457 &slice_start, &slice_end); 458 459 /* 460 * Is this the last page this list? 461 */ 462 if (*sortlist[idx] == NULL) { 463 bd_flags &= ~(1 << lbn); 464 --bd_cnt; 465 466 /* 467 * redo the sortlist so only 468 * bd_cnt choices show up 469 */ 470 bds = 0; 471 for (idy = 0; 472 idy < CHERRYSTONE_SBD_SLOTS; 473 idy++) { 474 if (bdlist[idy]) { 475 sortlist[bds++] 476 = &bdlist[idy]; 477 } 478 } 479 } 480 page_unlock(page); 481 } 482 mutex_exit(pcm); 483 } 484 } 485 } 486 } 487 488 /* 489 * If ubound > 0, will return an int between 0 & ubound 490 * If ubound < 0, will set "random seed" 491 */ 492 static uint_t 493 random_idx(int ubound) 494 { 495 static int idx = 0; 496 497 if (ubound > 0) { 498 idx = (idx + 1) % ubound; 499 return (idx); 500 } 501 idx = -ubound; 502 return (0); 503 } 504 505 /* 506 * Called for each board/cpu/PA range detected in plat_fill_mc(). 507 */ 508 static void 509 update_mem_bounds(int boardid, int cpuid, int bankid, 510 uint64_t base, uint64_t size) 511 { 512 slice_table[boardid][cpuid][bankid][SLICE_PA] = base; 513 slice_table[boardid][cpuid][bankid][SLICE_SPAN] = size; 514 } 515 516 /* 517 * Dynamically detect memory slices in the system by decoding 518 * the cpu memory decoder registers at boot time. 519 */ 520 void 521 plat_fill_mc(dnode_t nodeid) 522 { 523 uint64_t mc_addr, saf_addr; 524 uint64_t mc_decode[CHERRYSTONE_BANKS_PER_MC]; 525 uint64_t base, size; 526 uint64_t saf_mask; 527 uint64_t offset; 528 uint32_t regs[4]; 529 int len; 530 int local_mc; 531 int portid; 532 int boardid; 533 int cpuid; 534 int i; 535 536 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) || 537 (portid == -1)) 538 return; 539 540 /* 541 * Decode the board number from the MC portid. Assumes 542 * portid == safari agentid. 543 */ 544 boardid = CHERRYSTONE_GETSLOT(portid); 545 cpuid = CHERRYSTONE_GETSID(portid); 546 547 /* 548 * The "reg" property returns 4 32-bit values. The first two are 549 * combined to form a 64-bit address. The second two are for a 550 * 64-bit size, but we don't actually need to look at that value. 551 */ 552 len = prom_getproplen(nodeid, "reg"); 553 if (len != (sizeof (uint32_t) * 4)) { 554 prom_printf("Warning: malformed 'reg' property\n"); 555 return; 556 } 557 if (prom_getprop(nodeid, "reg", (caddr_t)regs) < 0) 558 return; 559 mc_addr = ((uint64_t)regs[0]) << 32; 560 mc_addr |= (uint64_t)regs[1]; 561 562 /* 563 * Figure out whether the memory controller we are examining 564 * belongs to this CPU or a different one. 565 */ 566 saf_addr = lddsafaddr(8); 567 saf_mask = (uint64_t)SAF_MASK; 568 if ((mc_addr & saf_mask) == saf_addr) 569 local_mc = 1; 570 else 571 local_mc = 0; 572 573 for (i = 0; i < CHERRYSTONE_BANKS_PER_MC; i++) { 574 /* 575 * Memory decode masks are at offsets 0x10 - 0x28. 576 */ 577 offset = 0x10 + (i << 3); 578 579 /* 580 * If the memory controller is local to this CPU, we use 581 * the special ASI to read the decode registers. 582 * Otherwise, we load the values from a magic address in 583 * I/O space. 584 */ 585 if (local_mc) 586 mc_decode[i] = lddmcdecode(offset); 587 else 588 mc_decode[i] = lddphysio(mc_addr | offset); 589 590 /* 591 * If the upper bit is set, we have a valid mask 592 */ 593 if ((int64_t)mc_decode[i] < 0) { 594 /* 595 * The memory decode register is a bitmask field, 596 * so we can decode that into both a base and 597 * a span. 598 */ 599 base = MC_BASE(mc_decode[i]) << PHYS2UM_SHIFT; 600 size = MC_UK2SPAN(mc_decode[i]); 601 update_mem_bounds(boardid, cpuid, i, base, size); 602 } 603 } 604 } 605 606 /* 607 * No platform drivers on this platform 608 */ 609 char *platform_module_list[] = { 610 (char *)0 611 }; 612 613 /*ARGSUSED*/ 614 void 615 plat_tod_fault(enum tod_fault_type tod_bad) 616 { 617 } 618 619 /*ARGSUSED*/ 620 int 621 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 622 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 623 { 624 if (flt_in_memory && (p2get_mem_unum != NULL)) 625 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8), 626 buf, buflen, lenp)); 627 else 628 return (ENOTSUP); 629 } 630 631 /* 632 * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3 633 * driver giving each platform the opportunity to add platform 634 * specific label information to the unum for ECC error logging purposes. 635 */ 636 void 637 plat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm) 638 { 639 _NOTE(ARGUNUSED(bank, dimm)) 640 641 char board = CHERRYSTONE_GETSLOT_LABEL(mcid); 642 char old_unum[UNUM_NAMLEN]; 643 644 strcpy(old_unum, unum); 645 snprintf(unum, UNUM_NAMLEN, "Slot %c: %s", board, old_unum); 646 } 647 648 int 649 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 650 { 651 char board = CHERRYSTONE_GETSLOT_LABEL(cpuid); 652 653 if (snprintf(buf, buflen, "Slot %c", board) >= buflen) { 654 return (ENOSPC); 655 } else { 656 *lenp = strlen(buf); 657 return (0); 658 } 659 } 660 661 /* 662 * Cherrystone's BBC pcf8584 controller is used by both OBP and the OS's i2c 663 * drivers. The 'eeprom' command executes OBP code to handle property requests. 664 * If eeprom didn't do this, or if the controllers were partitioned so that all 665 * devices on a given controller were driven by either OBP or the OS, this 666 * wouldn't be necessary. 667 * 668 * Note that getprop doesn't have the same issue as it reads from cached 669 * memory in OBP. 670 */ 671 672 /* 673 * Common locking enter code 674 */ 675 void 676 plat_setprop_enter(void) 677 { 678 mutex_enter(&cherry_pcf8584_mutex); 679 } 680 681 /* 682 * Common locking exit code 683 */ 684 void 685 plat_setprop_exit(void) 686 { 687 mutex_exit(&cherry_pcf8584_mutex); 688 } 689 690 /* 691 * Called by pcf8584 driver 692 */ 693 void 694 plat_shared_i2c_enter(dev_info_t *i2cnexus_dip) 695 { 696 if (i2cnexus_dip == shared_pcf8584_dip) { 697 plat_setprop_enter(); 698 } 699 } 700 701 /* 702 * Called by pcf8584 driver 703 */ 704 void 705 plat_shared_i2c_exit(dev_info_t *i2cnexus_dip) 706 { 707 if (i2cnexus_dip == shared_pcf8584_dip) { 708 plat_setprop_exit(); 709 } 710 } 711