1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_INTR_H 27 #define _SYS_INTR_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Each cpu allocates an interrupt request pool with the size of 37 * INTR_PENDING_MAX entries. 38 * XXX this number needs to be tuned 39 */ 40 #define INTR_PENDING_MAX 64 41 #define INTR_POOL_SIZE (sizeof (struct intr_req) * INTR_PENDING_MAX) 42 43 /* 44 * Each cpu allocates two arrays, intr_head[] and intr_tail[], with the size of 45 * PIL_LEVELS each. 46 * 47 * The entry 0 of the arrays are the head and the tail of the interrupt 48 * request free list. 49 * 50 * The entries 1-15 of the arrays are the head and the tail of interrupt 51 * level 1-15 request queues. 52 */ 53 #define PIL_LEVELS 16 /* 0 : for the interrupt request free list */ 54 /* 1-15 : for the pil level 1-15 */ 55 56 #define PIL_1 1 57 #define PIL_2 2 58 #define PIL_3 3 59 #define PIL_4 4 60 #define PIL_5 5 61 #define PIL_6 6 62 #define PIL_7 7 63 #define PIL_8 8 64 #define PIL_9 9 65 #define PIL_10 10 66 #define PIL_11 11 67 #define PIL_12 12 68 #define PIL_13 13 69 #define PIL_14 14 70 #define PIL_15 15 71 72 #ifndef _ASM 73 extern uint_t poke_cpu_inum; 74 extern size_t intr_add_max; 75 extern uint_t intr_add_div; 76 extern size_t intr_add_pools; 77 extern struct intr_req *intr_add_head; 78 extern struct intr_req *intr_add_tail; 79 extern void intr_init(struct cpu *); 80 extern void init_intr_pool(struct cpu *); 81 extern void cleanup_intr_pool(struct cpu *); 82 83 /* 84 * interrupt request entry 85 * 86 * - each cpu has an interrupt request free list formed thru 87 * init_intr_pool(); intr_head[0] and intr_tail[0] are the head 88 * and tail of the free list 89 * 90 * - always get a free intr_req from the intr_head[0] and 91 * return a served intr_req to intr_tail[0] 92 * 93 * - when vec_interrupt() is called, an interrupt request queue is built 94 * according to the pil level, intr_head[pil] points to the first 95 * interrupt request entry and intr_tail[pil] points to the last one 96 * 97 */ 98 struct intr_req { 99 uint_t intr_number; 100 struct intr_req *intr_next; 101 }; 102 103 #endif /* !_ASM */ 104 105 #ifdef __cplusplus 106 } 107 #endif 108 109 #endif /* _SYS_INTR_H */ 110