1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 1994, 1997-2002 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_INTR_H 28 #define _SYS_INTR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Each cpu allocates an interrupt request pool with the size of 38 * INTR_PENDING_MAX entries. 39 * XXX this number needs to be tuned 40 */ 41 #define INTR_PENDING_MAX 64 42 #define INTR_POOL_SIZE (sizeof (struct intr_req) * INTR_PENDING_MAX) 43 44 /* 45 * Allocate threads and stacks for interrupt handling. 46 */ 47 #define NINTR_THREADS (LOCK_LEVEL) /* number of interrupt threads */ 48 49 /* 50 * Each cpu allocates two arrays, intr_head[] and intr_tail[], with the size of 51 * PIL_LEVELS each. 52 * 53 * The entry 0 of the arrays are the head and the tail of the interrupt 54 * request free list. 55 * 56 * The entries 1-15 of the arrays are the head and the tail of interrupt 57 * level 1-15 request queues. 58 */ 59 #define PIL_LEVELS 16 /* 0 : for the interrupt request free list */ 60 /* 1-15 : for the pil level 1-15 */ 61 62 #define PIL_1 1 63 #define PIL_2 2 64 #define PIL_3 3 65 #define PIL_4 4 66 #define PIL_5 5 67 #define PIL_6 6 68 #define PIL_7 7 69 #define PIL_8 8 70 #define PIL_9 9 71 #define PIL_10 10 72 #define PIL_11 11 73 #define PIL_12 12 74 #define PIL_13 13 75 #define PIL_14 14 76 #define PIL_15 15 77 78 #ifndef _ASM 79 extern uint_t poke_cpu_inum; 80 extern size_t intr_add_max; 81 extern uint_t intr_add_div; 82 extern size_t intr_add_pools; 83 extern struct intr_req *intr_add_head; 84 extern struct intr_req *intr_add_tail; 85 extern void intr_init(struct cpu *); 86 extern void init_intr_pool(struct cpu *); 87 extern void cleanup_intr_pool(struct cpu *); 88 89 /* 90 * interrupt request entry 91 * 92 * - each cpu has an interrupt request free list formed thru 93 * init_intr_pool(); intr_head[0] and intr_tail[0] are the head 94 * and tail of the free list 95 * 96 * - always get a free intr_req from the intr_head[0] and 97 * return a served intr_req to intr_tail[0] 98 * 99 * - when vec_interrupt() is called, an interrupt request queue is built 100 * according to the pil level, intr_head[pil] points to the first 101 * interrupt request entry and intr_tail[pil] points to the last one 102 * 103 */ 104 struct intr_req { 105 uint_t intr_number; 106 struct intr_req *intr_next; 107 }; 108 109 #endif /* !_ASM */ 110 111 #ifdef __cplusplus 112 } 113 #endif 114 115 #endif /* _SYS_INTR_H */ 116