1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_VAR_H 28 #define _SYS_PX_VAR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Register base definitions. 38 * 39 * The specific numeric values for CSR, XBUS, Configuration, 40 * Interrupt blocks and other register bases. 41 */ 42 typedef enum { 43 PX_REG_BANK0 = 0, 44 PX_REG_BANK1, 45 PX_REG_BANK2, 46 PX_REG_BANK3, 47 PX_REG_BANK4 48 } px_reg_bank_t; 49 50 #ifdef sun4v 51 #define PX_REG_CSR PX_REG_BANK1 52 #define PX_REG_XBC PX_REG_BANK2 53 #define PX_REG_CFG PX_REG_BANK3 54 #define PX_REG_IC PX_REG_BANK4 55 #else 56 #define PX_REG_CSR PX_REG_BANK0 57 #define PX_REG_XBC PX_REG_BANK1 58 #define PX_REG_CFG PX_REG_BANK2 59 #define PX_REG_IC PX_REG_BANK3 60 #endif /* sun4v */ 61 62 enum px_nintr_index { 63 PX_INTR_XBC = 0, /* all not shared */ 64 PX_INTR_PEC = 1 /* all not shared */ 65 }; 66 67 /* 68 * offsets of PCI address spaces from base address: 69 */ 70 #define PX_CONFIG 0x001000000ull 71 #define PX_A_IO 0x002000000ull 72 #define PX_B_IO 0x002010000ull 73 #define PX_A_MEMORY 0x100000000ull 74 #define PX_B_MEMORY 0x180000000ull 75 #define PX_IO_SIZE 0x000010000ull 76 #define PX_MEM_SIZE 0x080000000ull 77 /* 78 * The following typedef is used to represent a 79 * 1275 "bus-range" property of a PCI Bus node. 80 */ 81 typedef struct px_bus_range { 82 uint32_t lo; 83 uint32_t hi; 84 } px_bus_range_t; 85 86 /* 87 * The following typedef is used to represent a 88 * 1275 "reg" property of a PCI nexus. 89 */ 90 typedef struct px_nexus_regspec { 91 uint64_t phys_addr; 92 uint64_t size; 93 } px_nexus_regspec_t; 94 95 /* 96 * The following typedef is used to represent an entry in the "ranges" 97 * property of a device node. 98 */ 99 typedef struct px_ranges { 100 uint32_t child_high; 101 uint32_t child_mid; 102 uint32_t child_low; 103 uint32_t parent_high; 104 uint32_t parent_low; 105 uint32_t size_high; 106 uint32_t size_low; 107 } px_ranges_t; 108 109 typedef enum { PX_NEW, PX_ATTACHED, PX_DETACHED, PX_SUSPENDED } px_state_t; 110 typedef enum { PX_OBJ_INTR_ADD, PX_OBJ_INTR_REMOVE } px_obj_op_t; 111 typedef enum { PX_PEC_OBJ, PX_CB_OBJ } px_obj_t; 112 113 #define PX_ATTACH_RETCODE(obj, op, err) \ 114 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 115 116 #define PX_OTHER_SIDE(side) ((side) ^ 1) 117 118 /* 119 * px soft state structure: 120 * 121 * Each px node has a px soft state structure. 122 */ 123 struct px { 124 /* 125 * State flags and mutex: 126 */ 127 px_state_t px_state; 128 uint_t px_soft_state; 129 uint_t px_open_count; 130 kmutex_t px_mutex; 131 132 /* 133 * Links to other state structures: 134 */ 135 dev_info_t *px_dip; /* devinfo structure */ 136 devhandle_t px_dev_hdl; /* device handle */ 137 px_cb_t *px_cb_p; /* XBC block */ 138 px_ib_t *px_ib_p; /* interrupt block */ 139 px_pec_t *px_pec_p; /* PEC block */ 140 px_mmu_t *px_mmu_p; /* IOMMU block */ 141 142 /* 143 * px device node properties: 144 */ 145 px_bus_range_t px_bus_range; /* "bus-range" */ 146 px_ranges_t *px_ranges_p; /* "ranges" data & length */ 147 int px_ranges_length; 148 devino_t *px_inos; /* inos from "interrupts" prop */ 149 int px_inos_len; /* "interrupts" length */ 150 int pci_numproxy; /* upa interrupt proxies */ 151 int px_thermal_interrupt; /* node has thermal interrupt */ 152 153 /* 154 * register mapping: 155 * XXX - Remove the following fields and move them 156 * to SUN4U library code, after complete virtualization 157 * (after porting MSI and Error handling code). 158 */ 159 caddr_t px_address[4]; 160 ddi_acc_handle_t px_ac[4]; 161 162 /* Interrupt support */ 163 int intr_map_size; 164 struct intr_map *intr_map; 165 struct intr_map_mask *intr_map_mask; 166 167 /* Error handling */ 168 px_fault_t px_fault; 169 px_fault_t px_cb_fault; 170 171 /* FMA */ 172 int px_fm_cap; 173 ddi_iblock_cookie_t px_fm_ibc; 174 175 /* Platform specific information */ 176 void *px_plat_p; 177 178 }; 179 180 /* px soft state flag */ 181 #define PX_SOFT_STATE_OPEN 0x01 182 #define PX_SOFT_STATE_OPEN_EXCL 0x02 183 #define PX_SOFT_STATE_CLOSED 0x04 184 #define PX_BYPASS_DMA_ALLOWED 0x10 185 186 #define DIP_TO_INST(dip) ddi_get_instance(dip) 187 #define INST_TO_STATE(inst) ddi_get_soft_state(px_state_p, inst) 188 #define DIP_TO_STATE(dip) INST_TO_STATE(DIP_TO_INST(dip)) 189 190 #define DEV_TO_SOFTSTATE(dev) ((px_t *)ddi_get_soft_state( \ 191 px_state_p, PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 192 193 extern void *px_state_p; 194 195 /* 196 * function prototypes for bus ops routines: 197 */ 198 extern int 199 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 200 off_t offset, off_t len, caddr_t *addrp); 201 extern int 202 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, 203 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 204 extern int 205 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 206 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 207 extern int 208 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 209 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 210 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 211 extern int 212 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 213 ddi_dma_handle_t handle); 214 extern int 215 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 216 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 217 uint_t cache_flags); 218 extern int 219 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 220 ddi_ctl_enum_t op, void *arg, void *result); 221 extern int 222 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 223 ddi_intr_handle_impl_t *handle, void *result); 224 225 #ifdef __cplusplus 226 } 227 #endif 228 229 #endif /* _SYS_PX_VAR_H */ 230