1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_VAR_H 27 #define _SYS_PX_VAR_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/callb.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* 38 * offsets of PCI address spaces from base address: 39 */ 40 #define PX_CONFIG 0x001000000ull 41 #define PX_A_IO 0x002000000ull 42 #define PX_B_IO 0x002010000ull 43 #define PX_A_MEMORY 0x100000000ull 44 #define PX_B_MEMORY 0x180000000ull 45 #define PX_IO_SIZE 0x000010000ull 46 #define PX_MEM_SIZE 0x080000000ull 47 48 /* 49 * The following typedef is used to represent a 50 * 1275 "bus-range" property of a PCI Bus node. 51 */ 52 typedef struct px_bus_range { 53 uint32_t lo; 54 uint32_t hi; 55 } px_bus_range_t; 56 57 /* 58 * The following typedef is used to represent an entry in the "ranges" 59 * property of a device node. 60 */ 61 typedef struct px_ranges { 62 uint32_t child_high; 63 uint32_t child_mid; 64 uint32_t child_low; 65 uint32_t parent_high; 66 uint32_t parent_low; 67 uint32_t size_high; 68 uint32_t size_low; 69 } px_ranges_t; 70 71 /* 72 * The following typedef is used to represent a 73 * 1275 "reg" property of a PCI nexus. 74 */ 75 typedef struct px_nexus_regspec { 76 uint64_t phys_addr; 77 uint64_t size; 78 } px_nexus_regspec_t; 79 80 typedef enum { 81 PX_ATTACHED = 1, 82 PX_DETACHED, 83 PX_SUSPENDED 84 } px_state_t; 85 86 enum { PX_INTR_XBC, PX_INTR_PEC, PX_INTR_HOTPLUG }; 87 88 #define PX_ATTACH_RETCODE(obj, op, err) \ 89 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 90 91 /* 92 * px soft state structure: 93 * 94 * Each px node has a px soft state structure. 95 */ 96 struct px { 97 /* 98 * State flags and mutex: 99 */ 100 px_state_t px_state; 101 uint_t px_soft_state; 102 uint_t px_open_count; 103 kmutex_t px_mutex; 104 105 /* 106 * Links to other state structures: 107 */ 108 dev_info_t *px_dip; /* devinfo structure */ 109 devhandle_t px_dev_hdl; /* device handle */ 110 px_ib_t *px_ib_p; /* interrupt block */ 111 px_pec_t *px_pec_p; /* PEC block */ 112 px_mmu_t *px_mmu_p; /* IOMMU block */ 113 114 /* 115 * px device node properties: 116 */ 117 px_bus_range_t px_bus_range; /* "bus-range" */ 118 px_ranges_t *px_ranges_p; /* "ranges" data & length */ 119 int px_ranges_length; 120 devino_t *px_inos; /* inos from "interrupts" prop */ 121 int px_inos_len; /* "interrupts" length */ 122 123 /* Error handling */ 124 px_fault_t px_fault; 125 px_fault_t px_cb_fault; 126 127 /* FMA */ 128 int px_fm_cap; 129 kmutex_t px_fm_mutex; 130 ddi_iblock_cookie_t px_fm_ibc; 131 132 uint32_t px_dev_caps; 133 134 /* Platform specific information */ 135 void *px_plat_p; 136 137 /* Power Management fields */ 138 kmutex_t px_l23ready_lock; /* used in PME_To_ACK interrupt */ 139 kcondvar_t px_l23ready_cv; /* used in PME_TO_ACK timeout */ 140 volatile uint32_t px_lup_pending; 141 int px_pm_flags; 142 msiqid_t px_pm_msiq_id; /* EQ id for PCIE_PME_ACK_MSG Message */ 143 uint32_t px_pmetoack_ignored; /* count of PME_To_ACKs ignored */ 144 145 /* CPR callback id */ 146 callb_id_t px_cprcb_id; 147 uint32_t px_dma_sync_opt; /* DMA syncing req. of hw */ 148 149 /* Handle for soft intr */ 150 ddi_softint_handle_t px_dbg_hdl; /* HDL for dbg printing */ 151 152 /* array to keep track of register snapshots during error handling */ 153 int px_dq_tail; /* last valid index in cs array */ 154 pf_data_t *px_dq_p; 155 }; 156 157 /* px soft state flag */ 158 #define PX_SOFT_STATE_OPEN 1 159 #define PX_SOFT_STATE_OPEN_EXCL 2 160 #define PX_SOFT_STATE_CLOSED 4 161 162 /* px_dev_caps definition */ 163 #define PX_BYPASS_DMA_ALLOWED 1 164 #define PX_HOTPLUG_CAPABLE 2 165 #define PX_DMA_SYNC_REQUIRED 4 166 167 /* px_pm_flags definitions used with interrupts and FMA code */ 168 #define PX_PMETOACK_RECVD 0x01 /* With PME_To_ACK interrupt */ 169 #define PX_PME_TURNOFF_PENDING 0x02 /* With PME_To_ACK interrupt */ 170 #define PX_LDN_EXPECTED 0x04 /* With FMA code */ 171 172 #define DIP_TO_INST(dip) ddi_get_instance(dip) 173 #define INST_TO_STATE(inst) ddi_get_soft_state(px_state_p, inst) 174 #define DIP_TO_STATE(dip) INST_TO_STATE(DIP_TO_INST(dip)) 175 176 #define PX_DEV_TO_SOFTSTATE(dev) ((px_t *)ddi_get_soft_state( \ 177 px_state_p, PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 178 179 extern void *px_state_p; 180 181 /* 182 * function prototypes for bus ops routines: 183 */ 184 extern int 185 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 186 off_t offset, off_t len, caddr_t *addrp); 187 extern int 188 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, 189 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 190 extern int 191 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 192 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 193 extern int 194 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 195 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 196 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 197 extern int 198 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 199 ddi_dma_handle_t handle); 200 extern int 201 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 202 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 203 uint_t cache_flags); 204 extern int 205 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 206 ddi_ctl_enum_t op, void *arg, void *result); 207 extern int 208 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 209 ddi_intr_handle_impl_t *handle, void *result); 210 211 #ifdef __cplusplus 212 } 213 #endif 214 215 #endif /* _SYS_PX_VAR_H */ 216