1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * PCI Express nexus driver tunables 28 */ 29 30 #include <sys/types.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/cmn_err.h> 34 #include <sys/time.h> 35 #include <sys/pcie.h> 36 #include "px_obj.h" 37 38 /*LINTLIBRARY*/ 39 40 uint32_t px_spurintr_duration = 60000000; /* One minute */ 41 uint64_t px_spurintr_msgs = PX_SPURINTR_MSG_DEFAULT; 42 43 /* 44 * The following variable enables a workaround for the following obp bug: 45 * 46 * 1234181 - obp should set latency timer registers in pci 47 * configuration header 48 * 49 * Until this bug gets fixed in the obp, the following workaround should 50 * be enabled. 51 */ 52 uint_t px_set_latency_timer_register = 1; 53 54 /* 55 * The following driver parameters are defined as variables to allow 56 * patching for debugging and tuning. Flags that can be set on a per 57 * PBM basis are bit fields where the PBM device instance number maps 58 * to the bit position. 59 */ 60 uint_t px_mmu_error_intr_enable = (uint_t)-1; 61 uint_t px_rerun_disable = 0; 62 63 uint_t px_error_intr_enable = (uint_t)-1; 64 uint_t px_dwsync_disable = 0; 65 uint_t px_intsync_disable = 0; 66 67 uint_t px_intr_retry_intv = 5; /* for interrupt retry reg */ 68 uint8_t px_latency_timer = 0x40; /* for pci latency timer reg */ 69 uint_t px_panic_on_fatal_errors = 1; /* should be 1 at beta */ 70 uint_t px_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 71 uint_t px_buserr_interrupt = 1; /* safari buserr interrupt */ 72 uint_t px_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 73 uint_t px_use_contexts = 1; 74 75 hrtime_t px_intrpend_timeout = 5ull * NANOSEC; /* 5 seconds in nanoseconds */ 76 77 uint64_t px_perr_fatal = -1ull; 78 uint64_t px_serr_fatal = -1ull; 79 uint64_t px_errtrig_pa = 0x0; 80 81 char px_panic_hb_msg[] = " System bus"; 82 char px_panic_rc_msg[] = " PCIe root complex"; 83 char px_panic_rp_msg[] = " PCIe root port"; 84 char px_panic_fab_msg[] = " PCIe fabric"; 85 86 /* 87 * The following flag controls behavior of the ino handler routine 88 * when multiple interrupts are attached to a single ino. Typically 89 * this case would occur for the ino's assigned to the PCI bus slots 90 * with multi-function devices or bus bridges. 91 * 92 * Setting the flag to zero causes the ino handler routine to return 93 * after finding the first interrupt handler to claim the interrupt. 94 * 95 * Setting the flag to non-zero causes the ino handler routine to 96 * return after making one complete pass through the interrupt 97 * handlers. 98 */ 99 uint_t px_check_all_handlers = 1; 100 101 /* 102 * The following value is the number of consecutive unclaimed interrupts that 103 * will be tolerated for a particular ino_p before the interrupt is deemed to 104 * be jabbering and is blocked. 105 */ 106 uint_t px_unclaimed_intr_max = 20; 107 108 /* 109 * The following value will cause the nexus driver to block an ino after 110 * px_unclaimed_intr_max unclaimed interrupts have been seen. Setting this 111 * value to 0 will cause interrupts to never be blocked, no matter how many 112 * unclaimed interrupts are seen on a particular ino. 113 */ 114 uint_t px_unclaimed_intr_block = 1; 115 116 uint_t px_lock_tlb = 0; 117 118 uint64_t px_dvma_debug_on = 0; 119 uint64_t px_dvma_debug_off = 0; 120 uint32_t px_dvma_debug_rec = 512; 121 122 /* 123 * dvma address space allocation cache variables 124 */ 125 uint_t px_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 126 uint_t px_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 127 #ifdef PX_DMA_PROF 128 uint_t px_dvmaft_npages = 0; /* FT fail due npages */ 129 uint_t px_dvmaft_limit = 0; /* FT fail due limits */ 130 uint_t px_dvmaft_free = 0; /* FT free */ 131 uint_t px_dvmaft_success = 0; /* FT success */ 132 uint_t px_dvmaft_exhaust = 0; /* FT vmem fallback */ 133 uint_t px_dvma_vmem_alloc = 0; /* vmem alloc */ 134 uint_t px_dvma_vmem_xalloc = 0; /* vmem xalloc */ 135 uint_t px_dvma_vmem_xfree = 0; /* vmem xfree */ 136 uint_t px_dvma_vmem_free = 0; /* vmem free */ 137 #endif 138 uint_t px_disable_fdvma = 0; 139 uint_t px_mmu_ctx_lock_failure = 0; 140 141 uint_t px_max_msiq_msgs = 4; 142 uint_t px_min_msiq_msgs = 2; 143 144 /* 145 * memory callback list id callback list for kmem_alloc failure clients 146 */ 147 uintptr_t px_kmem_clid = 0; 148 149 /* timeout in micro seconds for receiving PME_To_ACK */ 150 uint64_t px_pme_to_ack_timeout = PX_PME_TO_ACK_TIMEOUT; 151 152 /* timeout in micro seconds for receiving link up interrupt */ 153 uint64_t px_lup_poll_to = PX_LUP_POLL_TO; 154 uint64_t px_lup_poll_interval = PX_LUP_POLL_INTERVAL; 155 156 /* PIL at which PME_To_ACK message interrupt is handled */ 157 uint32_t px_pwr_pil = PX_PWR_PIL; 158 159 uint32_t px_max_l1_tries = PX_MAX_L1_TRIES; 160 161 /* Print and Log tunables. The following variables are booleans */ 162 #ifdef DEBUG 163 uint32_t px_log = PX_PANIC | PX_NO_PANIC | PX_PROTECTED | PX_HW_RESET; 164 #else 165 uint32_t px_log = PX_PANIC; 166 #endif 167 uint32_t px_die = PX_PANIC | PX_PROTECTED | PX_HW_RESET; 168