1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI Express PEC implementation: 30 * initialization 31 * Bus error interrupt handler 32 */ 33 34 #include <sys/types.h> 35 #include <sys/kmem.h> 36 #include <sys/spl.h> 37 #include <sys/sysmacros.h> 38 #include <sys/sunddi.h> 39 #include <sys/machsystm.h> /* ldphysio() */ 40 #include <sys/async.h> 41 #include <sys/ddi_impldefs.h> 42 #include <sys/ontrap.h> 43 #include <sys/membar.h> 44 #include "px_obj.h" 45 46 /*LINTLIBRARY*/ 47 48 extern uint_t px_ranges_phi_mask; 49 50 static uint_t px_pec_error_intr(caddr_t a); 51 static int px_pec_msg_add_intr(px_t *px_p); 52 static void px_pec_msg_rem_intr(px_t *px_p); 53 54 int 55 px_pec_attach(px_t *px_p) 56 { 57 px_pec_t *pec_p; 58 int i, len; 59 int nrange = px_p->px_ranges_length / sizeof (px_ranges_t); 60 dev_info_t *dip = px_p->px_dip; 61 px_ranges_t *rangep = px_p->px_ranges_p; 62 int ret; 63 64 /* 65 * Allocate a state structure for the PEC and cross-link it 66 * to its per px node state structure. 67 */ 68 pec_p = kmem_zalloc(sizeof (px_pec_t), KM_SLEEP); 69 px_p->px_pec_p = pec_p; 70 pec_p->pec_px_p = px_p; 71 72 len = snprintf(pec_p->pec_nameinst_str, 73 sizeof (pec_p->pec_nameinst_str), 74 "%s%d", NAMEINST(dip)); 75 pec_p->pec_nameaddr_str = pec_p->pec_nameinst_str + ++len; 76 (void) snprintf(pec_p->pec_nameaddr_str, 77 sizeof (pec_p->pec_nameinst_str) - len, 78 "%s@%s", NAMEADDR(dip)); 79 80 /* 81 * Add interrupt handlers to process correctable/fatal/non fatal 82 * PCIE messages. 83 */ 84 if ((ret = px_pec_msg_add_intr(px_p)) != DDI_SUCCESS) { 85 px_pec_msg_rem_intr(px_p); 86 return (ret); 87 } 88 89 /* 90 * Get this pec's mem32 and mem64 segments to determine whether 91 * a dma object originates from ths pec. i.e. dev to dev dma 92 */ 93 for (i = 0; i < nrange; i++, rangep++) { 94 uint64_t rng_addr, rng_size, *pfnbp, *pfnlp; 95 uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK; 96 97 switch (rng_type) { 98 case PCI_ADDR_MEM32: 99 pfnbp = &pec_p->pec_base32_pfn; 100 pfnlp = &pec_p->pec_last32_pfn; 101 break; 102 103 case PCI_ADDR_MEM64: 104 pfnbp = &pec_p->pec_base64_pfn; 105 pfnlp = &pec_p->pec_last64_pfn; 106 break; 107 108 case PCI_ADDR_CONFIG: 109 case PCI_ADDR_IO: 110 default: 111 continue; 112 } 113 rng_addr = (uint64_t)(rangep->parent_high & 114 px_ranges_phi_mask) << 32; 115 rng_addr |= (uint64_t)rangep->parent_low; 116 rng_size = (uint64_t)rangep->size_high << 32; 117 rng_size |= (uint64_t)rangep->size_low; 118 119 *pfnbp = mmu_btop(rng_addr); 120 *pfnlp = mmu_btop(rng_addr + rng_size); 121 } 122 123 mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER, 124 (void *)px_p->px_fm_ibc); 125 126 return (DDI_SUCCESS); 127 } 128 129 void 130 px_pec_detach(px_t *px_p) 131 { 132 dev_info_t *dip = px_p->px_dip; 133 px_pec_t *pec_p = px_p->px_pec_p; 134 135 /* 136 * Free the pokefault mutex. 137 */ 138 DBG(DBG_DETACH, dip, "px_pec_detach:\n"); 139 mutex_destroy(&pec_p->pec_pokefault_mutex); 140 141 /* 142 * Remove interrupt handlers to process correctable/fatal/non fatal 143 * PCIE messages. 144 */ 145 px_pec_msg_rem_intr(px_p); 146 147 /* 148 * Free the pec state structure. 149 */ 150 kmem_free(pec_p, sizeof (px_pec_t)); 151 px_p->px_pec_p = NULL; 152 } 153 154 /* 155 * pec_msg_add_intr: 156 * 157 * Add interrupt handlers to process correctable/fatal/non fatal 158 * PCIE messages. 159 */ 160 static int 161 px_pec_msg_add_intr(px_t *px_p) 162 { 163 dev_info_t *dip = px_p->px_dip; 164 px_pec_t *pec_p = px_p->px_pec_p; 165 ddi_intr_handle_impl_t hdl; 166 int ret = DDI_SUCCESS; 167 168 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_add_intr\n"); 169 170 /* Initialize handle */ 171 bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 172 hdl.ih_cb_func = (ddi_intr_handler_t *)px_err_fabric_intr; 173 hdl.ih_ver = DDI_INTR_VERSION; 174 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 175 hdl.ih_dip = dip; 176 177 /* Add correctable error message handler */ 178 hdl.ih_pri = PX_ERR_LOW_PIL; 179 180 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 181 MSG_REC, (msgcode_t)PCIE_CORR_MSG, 182 &pec_p->pec_corr_msg_msiq_id)) != DDI_SUCCESS) { 183 DBG(DBG_MSG, px_p->px_dip, 184 "PCIE_CORR_MSG registration failed\n"); 185 return (DDI_FAILURE); 186 } 187 188 px_lib_msg_setmsiq(dip, PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 189 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_VALID); 190 191 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 192 px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id), 193 PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC, 194 PCIE_CORR_MSG)) != DDI_SUCCESS) { 195 DBG(DBG_MSG, px_p->px_dip, 196 "PCIE_CORR_MSG update interrupt state failed\n"); 197 return (DDI_FAILURE); 198 } 199 200 /* Add non-fatal error message handler */ 201 hdl.ih_pri = PX_ERR_PIL; 202 203 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 204 MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, 205 &pec_p->pec_non_fatal_msg_msiq_id)) != DDI_SUCCESS) { 206 DBG(DBG_MSG, px_p->px_dip, 207 "PCIE_NONFATAL_MSG registration failed\n"); 208 return (DDI_FAILURE); 209 } 210 211 px_lib_msg_setmsiq(dip, PCIE_NONFATAL_MSG, 212 pec_p->pec_non_fatal_msg_msiq_id); 213 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, PCIE_MSG_VALID); 214 215 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 216 px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id), 217 PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC, 218 PCIE_NONFATAL_MSG)) != DDI_SUCCESS) { 219 DBG(DBG_MSG, px_p->px_dip, 220 "PCIE_NONFATAL_MSG update interrupt state failed\n"); 221 return (DDI_FAILURE); 222 } 223 224 /* Add fatal error message handler */ 225 hdl.ih_pri = PX_ERR_PIL; 226 227 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 228 MSG_REC, (msgcode_t)PCIE_FATAL_MSG, 229 &pec_p->pec_fatal_msg_msiq_id)) != DDI_SUCCESS) { 230 DBG(DBG_MSG, px_p->px_dip, 231 "PCIE_FATAL_MSG registration failed\n"); 232 return (DDI_FAILURE); 233 } 234 235 px_lib_msg_setmsiq(dip, PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 236 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_VALID); 237 238 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 239 px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), PX_ERR_PIL, 240 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) { 241 DBG(DBG_MSG, px_p->px_dip, 242 "PCIE_FATAL_MSG update interrupt state failed\n"); 243 return (DDI_FAILURE); 244 } 245 246 return (ret); 247 } 248 249 /* 250 * px_pec_msg_rem_intr: 251 * 252 * Remove interrupt handlers to process correctable/fatal/non fatal 253 * PCIE messages. For now, all these PCIe messages are mapped to 254 * same MSIQ. 255 */ 256 static void 257 px_pec_msg_rem_intr(px_t *px_p) 258 { 259 dev_info_t *dip = px_p->px_dip; 260 px_pec_t *pec_p = px_p->px_pec_p; 261 ddi_intr_handle_impl_t hdl; 262 263 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_rem_intr: dip 0x%p\n", dip); 264 265 /* Initialize handle */ 266 bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 267 hdl.ih_ver = DDI_INTR_VERSION; 268 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 269 hdl.ih_dip = dip; 270 271 if (pec_p->pec_corr_msg_msiq_id >= 0) { 272 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID); 273 274 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 275 PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 276 277 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 278 px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id), 279 PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC, 280 PCIE_CORR_MSG); 281 282 pec_p->pec_corr_msg_msiq_id = (msiqid_t)-1; 283 } 284 285 if (pec_p->pec_non_fatal_msg_msiq_id >= 0) { 286 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, 287 PCIE_MSG_INVALID); 288 289 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 290 PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id); 291 292 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 293 px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id), 294 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, 295 PCIE_NONFATAL_MSG); 296 297 pec_p->pec_non_fatal_msg_msiq_id = (msiqid_t)-1; 298 } 299 300 if (pec_p->pec_fatal_msg_msiq_id >= 0) { 301 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID); 302 303 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 304 PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 305 306 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 307 px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), 308 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG); 309 310 pec_p->pec_fatal_msg_msiq_id = (msiqid_t)-1; 311 } 312 } 313