1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI Express PEC implementation: 31 * initialization 32 * Bus error interrupt handler 33 */ 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/spl.h> 38 #include <sys/sysmacros.h> 39 #include <sys/sunddi.h> 40 #include <sys/machsystm.h> /* ldphysio() */ 41 #include <sys/async.h> 42 #include <sys/ddi_impldefs.h> 43 #include <sys/ontrap.h> 44 #include <sys/membar.h> 45 #include "px_obj.h" 46 47 /*LINTLIBRARY*/ 48 49 extern uint_t px_ranges_phi_mask; 50 51 static int px_pec_msg_add_intr(px_t *px_p); 52 static void px_pec_msg_rem_intr(px_t *px_p); 53 54 static void 55 px_ilu_attach(px_pec_t *pec_p) 56 { 57 /* 58 * Register ilu error interrupt. This will 59 * also program the correct values into the 60 * log enable and interrupt enable registers. 61 */ 62 px_err_add_fh(&pec_p->pec_px_p->px_fault, PX_ERR_ILU, 63 (caddr_t)pec_p->pec_px_p->px_address[PX_REG_CSR]); 64 } 65 66 int 67 px_ilu_intr(dev_info_t *dip, px_fh_t *fh_p) 68 { 69 uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 70 uint64_t stat = fh_p->fh_stat; 71 72 if (stat) 73 LOG(DBG_ERR_INTR, dip, "[%x]=%16llx ilu stat\n", offset, stat); 74 return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 75 } 76 77 static void 78 px_tlu_attach(px_pec_t *pec_p) 79 { 80 caddr_t csr_base = (caddr_t)pec_p->pec_px_p->px_address[PX_REG_CSR]; 81 px_fault_t *px_fault_p = &pec_p->pec_px_p->px_fault; 82 83 px_err_add_fh(px_fault_p, PX_ERR_TLU_UE, csr_base); 84 px_err_add_fh(px_fault_p, PX_ERR_TLU_CE, csr_base); 85 px_err_add_fh(px_fault_p, PX_ERR_TLU_OE, csr_base); 86 } 87 88 static void 89 px_lpu_attach(px_pec_t *pec_p) 90 { 91 caddr_t csr_base = (caddr_t)pec_p->pec_px_p->px_address[PX_REG_CSR]; 92 px_fault_t *px_fault_p = &pec_p->pec_px_p->px_fault; 93 94 px_err_add_fh(px_fault_p, PX_ERR_LPU_LINK, csr_base); 95 px_err_add_fh(px_fault_p, PX_ERR_LPU_PHY, csr_base); 96 px_err_add_fh(px_fault_p, PX_ERR_LPU_REC_PHY, csr_base); 97 px_err_add_fh(px_fault_p, PX_ERR_LPU_TRNS_PHY, csr_base); 98 px_err_add_fh(px_fault_p, PX_ERR_LPU_LTSSM, csr_base); 99 px_err_add_fh(px_fault_p, PX_ERR_LPU_GIGABLZ, csr_base); 100 } 101 102 int 103 px_tlu_ue_intr(dev_info_t *dip, px_fh_t *fh_p) 104 { 105 uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 106 uint64_t stat = fh_p->fh_stat; 107 108 if (stat) 109 LOG(DBG_ERR_INTR, dip, "[%x]=%16llx tlu ue stat\n", offset, 110 stat); 111 return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 112 } 113 114 int 115 px_tlu_ce_intr(dev_info_t *dip, px_fh_t *fh_p) 116 { 117 uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 118 uint64_t stat = fh_p->fh_stat; 119 120 if (stat) 121 LOG(DBG_ERR_INTR, dip, "[%x]=%16llx tlu ce stat\n", offset, 122 stat); 123 return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 124 } 125 126 int 127 px_tlu_oe_intr(dev_info_t *dip, px_fh_t *fh_p) 128 { 129 uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 130 uint64_t stat = fh_p->fh_stat; 131 132 if (stat) 133 LOG(DBG_ERR_INTR, dip, "[%x]=%16llx tlu other stat\n", offset, 134 stat); 135 return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 136 } 137 138 int 139 px_lpu_intr(dev_info_t *dip, px_fh_t *fh_p) 140 { 141 uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 142 uint64_t stat = fh_p->fh_stat; 143 144 if (stat) 145 LOG(DBG_ERR_INTR, dip, "[%x]=%16llx lpu stat\n", offset, stat); 146 return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 147 } 148 149 int 150 px_pec_attach(px_t *px_p) 151 { 152 px_pec_t *pec_p; 153 int i, len; 154 int nrange = px_p->px_ranges_length / sizeof (px_ranges_t); 155 dev_info_t *dip = px_p->px_dip; 156 px_ranges_t *rangep = px_p->px_ranges_p; 157 int ret; 158 159 /* 160 * Allocate a state structure for the PEC and cross-link it 161 * to its per px node state structure. 162 */ 163 pec_p = kmem_zalloc(sizeof (px_pec_t), KM_SLEEP); 164 px_p->px_pec_p = pec_p; 165 pec_p->pec_px_p = px_p; 166 167 len = snprintf(pec_p->pec_nameinst_str, 168 sizeof (pec_p->pec_nameinst_str), 169 "%s%d", NAMEINST(dip)); 170 pec_p->pec_nameaddr_str = pec_p->pec_nameinst_str + ++len; 171 (void) snprintf(pec_p->pec_nameaddr_str, 172 sizeof (pec_p->pec_nameinst_str) - len, 173 "%s@%s", NAMEADDR(dip)); 174 175 /* 176 * Add interrupt handlers to process correctable/fatal/non fatal 177 * PCIE messages. 178 */ 179 if ((ret = px_pec_msg_add_intr(px_p)) != DDI_SUCCESS) { 180 px_pec_msg_rem_intr(px_p); 181 return (ret); 182 } 183 184 /* 185 * Get this pec's mem32 and mem64 segments to determine whether 186 * a dma object originates from ths pec. i.e. dev to dev dma 187 */ 188 for (i = 0; i < nrange; i++, rangep++) { 189 uint64_t rng_addr, rng_size, *pfnbp, *pfnlp; 190 uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK; 191 192 switch (rng_type) { 193 case PCI_ADDR_MEM32: 194 pfnbp = &pec_p->pec_base32_pfn; 195 pfnlp = &pec_p->pec_last32_pfn; 196 break; 197 198 case PCI_ADDR_MEM64: 199 pfnbp = &pec_p->pec_base64_pfn; 200 pfnlp = &pec_p->pec_last64_pfn; 201 break; 202 203 case PCI_ADDR_CONFIG: 204 case PCI_ADDR_IO: 205 default: 206 continue; 207 } 208 rng_addr = (uint64_t)(rangep->parent_high & 209 px_ranges_phi_mask) << 32; 210 rng_addr |= (uint64_t)rangep->parent_low; 211 rng_size = (uint64_t)rangep->size_high << 32; 212 rng_size |= (uint64_t)rangep->size_low; 213 214 *pfnbp = mmu_btop(rng_addr); 215 *pfnlp = mmu_btop(rng_addr + rng_size); 216 } 217 218 /* 219 * configure ILU. 220 */ 221 px_ilu_attach(pec_p); 222 223 /* 224 * configure TLU. 225 */ 226 px_tlu_attach(pec_p); 227 228 /* 229 * configure LPU 230 */ 231 px_lpu_attach(pec_p); 232 233 /* 234 * Register a function to disable pec error interrupts during a panic. 235 * do in px_attach. bus_func_register(BF_TYPE_ERRDIS, 236 * (busfunc_t)pec_disable_pci_errors, pec_p); 237 */ 238 239 mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER, 0); 240 241 return (DDI_SUCCESS); 242 } 243 244 uint_t 245 pec_disable_px_errors(px_pec_t *pec_p) 246 { 247 px_t *px_p = pec_p->pec_px_p; 248 px_ib_t *ib_p = px_p->px_ib_p; 249 250 /* 251 * Disable error interrupts via the interrupt mapping register. 252 */ 253 px_ib_intr_disable(ib_p, px_p->px_inos[PX_INTR_PEC], IB_INTR_NOWAIT); 254 return (BF_NONE); 255 } 256 257 void 258 px_pec_detach(px_t *px_p) 259 { 260 dev_info_t *dip = px_p->px_dip; 261 px_pec_t *pec_p = px_p->px_pec_p; 262 px_ib_t *ib_p = px_p->px_ib_p; 263 devino_t ino = px_p->px_inos[PX_INTR_PEC]; 264 265 /* 266 * Free the pokefault mutex. 267 */ 268 DBG(DBG_DETACH, dip, "px_pec_detach:\n"); 269 mutex_destroy(&pec_p->pec_pokefault_mutex); 270 271 /* 272 * Remove the pci error interrupt handler. 273 */ 274 px_ib_intr_disable(ib_p, ino, IB_INTR_WAIT); 275 ddi_remove_intr(dip, 0, NULL); 276 277 /* 278 * Remove the error disable function. 279 */ 280 bus_func_unregister(BF_TYPE_ERRDIS, 281 (busfunc_t)pec_disable_px_errors, pec_p); 282 283 /* 284 * Remove interrupt handlers to process correctable/fatal/non fatal 285 * PCIE messages. 286 */ 287 px_pec_msg_rem_intr(px_p); 288 289 /* 290 * Free the pec state structure. 291 */ 292 kmem_free(pec_p, sizeof (px_pec_t)); 293 px_p->px_pec_p = NULL; 294 } 295 296 /* 297 * pec_msg_add_intr: 298 * 299 * Add interrupt handlers to process correctable/fatal/non fatal 300 * PCIE messages. 301 */ 302 static int 303 px_pec_msg_add_intr(px_t *px_p) 304 { 305 dev_info_t *dip = px_p->px_dip; 306 px_pec_t *pec_p = px_p->px_pec_p; 307 ddi_intr_handle_impl_t hdl; 308 int ret = DDI_SUCCESS; 309 310 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_add_intr\n"); 311 312 /* Initilize handle */ 313 hdl.ih_ver = DDI_INTR_VERSION; 314 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 315 hdl.ih_dip = dip; 316 hdl.ih_inum = 0; 317 hdl.ih_pri = PX_ERR_PIL; 318 319 /* Add correctable error message handler */ 320 hdl.ih_cb_func = (ddi_intr_handler_t *)px_pec_corr_msg_intr; 321 hdl.ih_cb_arg1 = px_p; 322 hdl.ih_cb_arg2 = NULL; 323 324 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 325 MSG_REC, (msgcode_t)PCIE_CORR_MSG, 326 &pec_p->pec_corr_msg_msiq_id)) != DDI_SUCCESS) { 327 DBG(DBG_MSG, px_p->px_dip, 328 "PCIE_CORR_MSG registration failed\n"); 329 return (DDI_FAILURE); 330 } 331 332 px_lib_msg_setmsiq(dip, PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 333 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_VALID); 334 335 /* Add non-fatal error message handler */ 336 hdl.ih_cb_func = (ddi_intr_handler_t *)px_pec_non_fatal_msg_intr; 337 hdl.ih_cb_arg1 = px_p; 338 hdl.ih_cb_arg2 = NULL; 339 340 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 341 MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, 342 &pec_p->pec_non_fatal_msg_msiq_id)) != DDI_SUCCESS) { 343 DBG(DBG_MSG, px_p->px_dip, 344 "PCIE_NONFATAL_MSG registration failed\n"); 345 return (DDI_FAILURE); 346 } 347 348 px_lib_msg_setmsiq(dip, PCIE_NONFATAL_MSG, 349 pec_p->pec_non_fatal_msg_msiq_id); 350 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, PCIE_MSG_VALID); 351 352 /* Add fatal error message handler */ 353 hdl.ih_cb_func = (ddi_intr_handler_t *)px_pec_fatal_msg_intr; 354 hdl.ih_cb_arg1 = px_p; 355 hdl.ih_cb_arg2 = NULL; 356 357 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 358 MSG_REC, (msgcode_t)PCIE_FATAL_MSG, 359 &pec_p->pec_fatal_msg_msiq_id)) != DDI_SUCCESS) { 360 DBG(DBG_MSG, px_p->px_dip, 361 "PCIE_FATAL_MSG registration failed\n"); 362 return (DDI_FAILURE); 363 } 364 365 px_lib_msg_setmsiq(dip, PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 366 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_VALID); 367 368 return (ret); 369 } 370 371 /* 372 * px_pec_msg_rem_intr: 373 * 374 * Remove interrupt handlers to process correctable/fatal/non fatal 375 * PCIE messages. For now, all these PCIe messages are mapped to 376 * same MSIQ. 377 */ 378 static void 379 px_pec_msg_rem_intr(px_t *px_p) 380 { 381 dev_info_t *dip = px_p->px_dip; 382 px_pec_t *pec_p = px_p->px_pec_p; 383 ddi_intr_handle_impl_t hdl; 384 385 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_rem_intr: dip 0x%p\n", dip); 386 387 /* Initilize handle */ 388 hdl.ih_ver = DDI_INTR_VERSION; 389 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 390 hdl.ih_dip = dip; 391 hdl.ih_inum = 0; 392 393 if (pec_p->pec_corr_msg_msiq_id >= 0) { 394 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID); 395 396 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 397 PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 398 pec_p->pec_corr_msg_msiq_id = -1; 399 } 400 401 if (pec_p->pec_non_fatal_msg_msiq_id >= 0) { 402 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, 403 PCIE_MSG_INVALID); 404 405 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 406 PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id); 407 408 pec_p->pec_non_fatal_msg_msiq_id = -1; 409 } 410 411 if (pec_p->pec_fatal_msg_msiq_id >= 0) { 412 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID); 413 414 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 415 PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 416 417 pec_p->pec_fatal_msg_msiq_id = -1; 418 } 419 } 420 421 /*ARGSUSED*/ 422 uint_t 423 px_pec_corr_msg_intr(caddr_t arg) 424 { 425 px_t *px_p = (px_t *)arg; 426 uint64_t rid = px_p->px_pec_p->pec_msiq_rec_p->msiq_rec_rid; 427 428 DBG(DBG_MSG_INTR, px_p->px_dip, 429 "px_pec_corr_msg_intr: requester id 0x%x\n", rid); 430 431 px_p->px_pec_p->pec_msiq_rec_p = NULL; 432 433 return (DDI_INTR_CLAIMED); 434 } 435 436 /*ARGSUSED*/ 437 uint_t 438 px_pec_non_fatal_msg_intr(caddr_t arg) 439 { 440 px_t *px_p = (px_t *)arg; 441 uint64_t rid = px_p->px_pec_p->pec_msiq_rec_p->msiq_rec_rid; 442 443 DBG(DBG_MSG_INTR, px_p->px_dip, 444 "px_pec_non_fatal_msg_intr: requester id 0x%x\n", rid); 445 446 px_p->px_pec_p->pec_msiq_rec_p = NULL; 447 448 return (DDI_INTR_CLAIMED); 449 } 450 451 /*ARGSUSED*/ 452 uint_t 453 px_pec_fatal_msg_intr(caddr_t arg) 454 { 455 px_t *px_p = (px_t *)arg; 456 uint64_t rid = px_p->px_pec_p->pec_msiq_rec_p->msiq_rec_rid; 457 458 DBG(DBG_MSG_INTR, px_p->px_dip, 459 "px_pec_fatal_msg_intr: requester id 0x%x\n", rid); 460 461 px_p->px_pec_p->pec_msiq_rec_p = NULL; 462 463 return (DDI_INTR_CLAIMED); 464 } 465