1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB_H 27 #define _SYS_PX_LIB_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Include all data structures and definitions in this file that are 37 * required between the common and hardware specific code. 38 */ 39 40 #define DIP_TO_HANDLE(dip) ((px_t *)DIP_TO_STATE(dip))->px_dev_hdl 41 42 /* 43 * The following macros define the mmu page size and related operations. 44 */ 45 #define MMU_PAGE_SHIFT 13 46 #define MMU_PAGE_SIZE (1 << MMU_PAGE_SHIFT) 47 #define MMU_PAGE_MASK ~(MMU_PAGE_SIZE - 1) 48 #define MMU_PAGE_OFFSET (MMU_PAGE_SIZE - 1) 49 #define MMU_PTOB(x) (((uint64_t)(x)) << MMU_PAGE_SHIFT) 50 #define MMU_BTOP(x) ((x) >> MMU_PAGE_SHIFT) 51 #define MMU_BTOPR(x) MMU_BTOP((x) + MMU_PAGE_OFFSET) 52 53 /* MMU map flags */ 54 #define MMU_MAP_PFN 1 55 #define MMU_MAP_BUF 2 56 57 typedef struct px px_t; 58 typedef struct px_msiq px_msiq_t; 59 60 extern int px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl); 61 extern int px_lib_dev_fini(dev_info_t *dip); 62 extern int px_lib_map_vconfig(dev_info_t *dip, ddi_map_req_t *mp, 63 pci_config_offset_t off, pci_regspec_t *rp, caddr_t *addrp); 64 extern void px_lib_map_attr_check(ddi_map_req_t *mp); 65 66 extern int px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 67 sysino_t *sysino); 68 extern int px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 69 intr_valid_state_t *intr_valid_state); 70 extern int px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 71 intr_valid_state_t intr_valid_state); 72 extern int px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 73 intr_state_t *intr_state); 74 extern int px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 75 intr_state_t intr_state); 76 extern int px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, 77 cpuid_t *cpuid); 78 extern int px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, 79 cpuid_t cpuid); 80 extern int px_lib_intr_reset(dev_info_t *dip); 81 82 #ifdef FMA 83 extern void px_fill_rc_status(px_fault_t *px_fault_p, 84 pciex_rc_error_regs_t *rc_status); 85 #endif 86 87 extern int px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 88 io_attributes_t attr, void *addr, size_t pfn_index, int flags); 89 extern int px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages); 90 extern int px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, 91 io_attributes_t *attr_p, r_addr_t *r_addr_p); 92 extern int px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 93 uint64_t *lo_p, uint64_t *hi_p); 94 extern int px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, 95 io_attributes_t attr, io_addr_t *io_addr_p); 96 extern int px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, 97 ddi_dma_handle_t handle, off_t off, size_t len, uint_t cache_flags); 98 99 /* 100 * MSIQ Functions: 101 */ 102 extern int px_lib_msiq_init(dev_info_t *dip); 103 extern int px_lib_msiq_fini(dev_info_t *dip); 104 extern int px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, 105 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 106 extern int px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 107 pci_msiq_valid_state_t *msiq_valid_state); 108 extern int px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 109 pci_msiq_valid_state_t msiq_valid_state); 110 extern int px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 111 pci_msiq_state_t *msiq_state); 112 extern int px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 113 pci_msiq_state_t msiq_state); 114 extern int px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 115 msiqhead_t *msiq_head); 116 extern int px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 117 msiqhead_t msiq_head); 118 extern int px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 119 msiqtail_t *msiq_tail); 120 extern void px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 121 msiq_rec_t *msiq_rec_p); 122 extern void px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p); 123 124 /* 125 * MSI Functions: 126 */ 127 extern int px_lib_msi_init(dev_info_t *dip); 128 extern int px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 129 msiqid_t *msiq_id); 130 extern int px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 131 msiqid_t msiq_id, msi_type_t msitype); 132 extern int px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 133 pci_msi_valid_state_t *msi_valid_state); 134 extern int px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 135 pci_msi_valid_state_t msi_valid_state); 136 extern int px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 137 pci_msi_state_t *msi_state); 138 extern int px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 139 pci_msi_state_t msi_state); 140 141 /* 142 * MSG Functions: 143 */ 144 extern int px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 145 msiqid_t *msiq_id); 146 extern int px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 147 msiqid_t msiq_id); 148 extern int px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 149 pcie_msg_valid_state_t *msg_valid_state); 150 extern int px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 151 pcie_msg_valid_state_t msg_valid_state); 152 153 /* 154 * PM/CPR Functions: 155 */ 156 extern int px_lib_suspend(dev_info_t *dip); 157 extern void px_lib_resume(dev_info_t *dip); 158 extern void px_cpr_add_callb(px_t *); 159 extern void px_cpr_rem_callb(px_t *); 160 extern int px_lib_pmctl(int cmd, px_t *px_p); 161 extern uint_t px_pmeq_intr(caddr_t arg); 162 163 /* 164 * Common range property functions and definitions. 165 */ 166 #define PX_RANGE_PROP_MASK 0x7ff 167 extern uint64_t px_get_rng_parent_hi_mask(px_t *px_p); 168 169 /* 170 * Peek and poke access ddi_ctlops helper functions 171 */ 172 extern int px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 173 peekpoke_ctlops_t *in_args); 174 extern int px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 175 peekpoke_ctlops_t *in_args, void *result); 176 177 /* 178 * Error handling functions 179 */ 180 #define PX_INTR_PAYLOAD_SIZE 8 /* 64 bit words */ 181 typedef struct px_fault { 182 dev_info_t *px_fh_dip; 183 sysino_t px_fh_sysino; 184 uint_t (*px_err_func)(caddr_t px_fault); 185 devino_t px_intr_ino; 186 uint64_t px_intr_payload[PX_INTR_PAYLOAD_SIZE]; 187 } px_fault_t; 188 189 extern int px_err_add_intr(px_fault_t *px_fault_p); 190 extern void px_err_rem_intr(px_fault_t *px_fault_p); 191 extern int px_cb_add_intr(px_fault_t *); 192 extern void px_cb_rem_intr(px_fault_t *); 193 extern uint32_t px_fab_get(px_t *px_p, pcie_req_id_t bdf, 194 uint16_t offset); 195 extern void px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 196 uint32_t val); 197 198 /* 199 * CPR callback 200 */ 201 extern void px_cpr_add_callb(px_t *); 202 extern void px_cpr_rem_callb(px_t *); 203 204 /* 205 * Hotplug functions 206 */ 207 extern int px_lib_hotplug_init(dev_info_t *dip, void *regops); 208 extern void px_lib_hotplug_uninit(dev_info_t *dip); 209 210 extern boolean_t px_lib_is_in_drain_state(px_t *px_p); 211 extern pcie_req_id_t px_lib_get_bdf(px_t *px_p); 212 213 #ifdef __cplusplus 214 } 215 #endif 216 217 #endif /* _SYS_PX_LIB_H */ 218