xref: /titanic_50/usr/src/uts/sun4/io/px/px.c (revision f22acdfff536d452df49dd85c5ecd42092b8fcad)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 /*
30  * PCI Express nexus driver interface
31  */
32 
33 #include <sys/types.h>
34 #include <sys/conf.h>		/* nulldev */
35 #include <sys/stat.h>		/* devctl */
36 #include <sys/kmem.h>
37 #include <sys/sunddi.h>
38 #include <sys/sunndi.h>
39 #include <sys/hotplug/pci/pcihp.h>
40 #include <sys/ontrap.h>
41 #include <sys/ddi_impldefs.h>
42 #include <sys/ddi_subrdefs.h>
43 #include <sys/spl.h>
44 #include <sys/epm.h>
45 #include <sys/iommutsb.h>
46 #include "px_obj.h"
47 #include "pcie_pwr.h"
48 
49 /*LINTLIBRARY*/
50 
51 /*
52  * function prototypes for dev ops routines:
53  */
54 static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
55 static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
56 static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
57 	void *arg, void **result);
58 static int px_pwr_setup(dev_info_t *dip);
59 static void px_pwr_teardown(dev_info_t *dip);
60 
61 /*
62  * bus ops and dev ops structures:
63  */
64 static struct bus_ops px_bus_ops = {
65 	BUSO_REV,
66 	px_map,
67 	0,
68 	0,
69 	0,
70 	i_ddi_map_fault,
71 	px_dma_setup,
72 	px_dma_allochdl,
73 	px_dma_freehdl,
74 	px_dma_bindhdl,
75 	px_dma_unbindhdl,
76 	px_lib_dma_sync,
77 	px_dma_win,
78 	px_dma_ctlops,
79 	px_ctlops,
80 	ddi_bus_prop_op,
81 	ndi_busop_get_eventcookie,
82 	ndi_busop_add_eventcall,
83 	ndi_busop_remove_eventcall,
84 	ndi_post_event,
85 	NULL,
86 	NULL,			/* (*bus_config)(); */
87 	NULL,			/* (*bus_unconfig)(); */
88 	px_fm_init_child,	/* (*bus_fm_init)(); */
89 	NULL,			/* (*bus_fm_fini)(); */
90 	px_bus_enter,		/* (*bus_fm_access_enter)(); */
91 	px_bus_exit,		/* (*bus_fm_access_fini)(); */
92 	pcie_bus_power,		/* (*bus_power)(); */
93 	px_intr_ops		/* (*bus_intr_op)(); */
94 };
95 
96 extern struct cb_ops px_cb_ops;
97 
98 static struct dev_ops px_ops = {
99 	DEVO_REV,
100 	0,
101 	px_info,
102 	nulldev,
103 	0,
104 	px_attach,
105 	px_detach,
106 	nodev,
107 	&px_cb_ops,
108 	&px_bus_ops,
109 	nulldev
110 };
111 
112 /*
113  * module definitions:
114  */
115 #include <sys/modctl.h>
116 extern struct mod_ops mod_driverops;
117 
118 static struct modldrv modldrv = {
119 	&mod_driverops, 		/* Type of module - driver */
120 	"PCI Express nexus driver %I%",	/* Name of module. */
121 	&px_ops,			/* driver ops */
122 };
123 
124 static struct modlinkage modlinkage = {
125 	MODREV_1, (void *)&modldrv, NULL
126 };
127 
128 /* driver soft state */
129 void *px_state_p;
130 
131 int
132 _init(void)
133 {
134 	int e;
135 
136 	/*
137 	 * Initialize per-px bus soft state pointer.
138 	 */
139 	e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1);
140 	if (e != DDI_SUCCESS)
141 		return (e);
142 
143 	/*
144 	 * Install the module.
145 	 */
146 	e = mod_install(&modlinkage);
147 	if (e != DDI_SUCCESS)
148 		ddi_soft_state_fini(&px_state_p);
149 	return (e);
150 }
151 
152 int
153 _fini(void)
154 {
155 	int e;
156 
157 	/*
158 	 * Remove the module.
159 	 */
160 	e = mod_remove(&modlinkage);
161 	if (e != DDI_SUCCESS)
162 		return (e);
163 
164 	/* Free px soft state */
165 	ddi_soft_state_fini(&px_state_p);
166 
167 	return (e);
168 }
169 
170 int
171 _info(struct modinfo *modinfop)
172 {
173 	return (mod_info(&modlinkage, modinfop));
174 }
175 
176 /* ARGSUSED */
177 static int
178 px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
179 {
180 	int	instance = getminor((dev_t)arg);
181 	px_t	*px_p = INST_TO_STATE(instance);
182 
183 #ifdef	HOTPLUG
184 	/*
185 	 * Allow hotplug to deal with ones it manages
186 	 * Hot Plug will be done later.
187 	 */
188 	if (px_p && (px_p->hotplug_capable == B_TRUE))
189 		return (pcihp_info(dip, infocmd, arg, result));
190 #endif	/* HOTPLUG */
191 
192 	/* non-hotplug or not attached */
193 	switch (infocmd) {
194 	case DDI_INFO_DEVT2INSTANCE:
195 		*result = (void *)instance;
196 		return (DDI_SUCCESS);
197 
198 	case DDI_INFO_DEVT2DEVINFO:
199 		if (px_p == NULL)
200 			return (DDI_FAILURE);
201 		*result = (void *)px_p->px_dip;
202 		return (DDI_SUCCESS);
203 
204 	default:
205 		return (DDI_FAILURE);
206 	}
207 }
208 
209 /* device driver entry points */
210 /*
211  * attach entry point:
212  */
213 /*ARGSUSED*/
214 static int
215 px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
216 {
217 	px_t		*px_p;	/* per bus state pointer */
218 	int		instance = DIP_TO_INST(dip);
219 	int		ret = DDI_SUCCESS;
220 	devhandle_t	dev_hdl = NULL;
221 
222 	switch (cmd) {
223 	case DDI_ATTACH:
224 		DBG(DBG_ATTACH, dip, "DDI_ATTACH\n");
225 
226 		/*
227 		 * Allocate and get the per-px soft state structure.
228 		 */
229 		if (ddi_soft_state_zalloc(px_state_p, instance)
230 		    != DDI_SUCCESS) {
231 			cmn_err(CE_WARN, "%s%d: can't allocate px state",
232 				ddi_driver_name(dip), instance);
233 			goto err_bad_px_softstate;
234 		}
235 		px_p = INST_TO_STATE(instance);
236 		px_p->px_dip = dip;
237 		mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL);
238 		px_p->px_soft_state = PX_SOFT_STATE_CLOSED;
239 		px_p->px_open_count = 0;
240 
241 		/*
242 		 * Get key properties of the pci bridge node and
243 		 * determine it's type (psycho, schizo, etc ...).
244 		 */
245 		if (px_get_props(px_p, dip) == DDI_FAILURE)
246 			goto err_bad_px_prop;
247 
248 		if ((px_fm_attach(px_p)) != DDI_SUCCESS)
249 			goto err_bad_fm;
250 
251 		if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS)
252 			goto err_bad_dev_init;
253 
254 		/* Initilize device handle */
255 		px_p->px_dev_hdl = dev_hdl;
256 
257 		/*
258 		 * Initialize interrupt block.  Note that this
259 		 * initialize error handling for the PEC as well.
260 		 */
261 		if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS)
262 			goto err_bad_ib;
263 
264 		if (px_cb_attach(px_p) != DDI_SUCCESS)
265 			goto err_bad_cb;
266 
267 		/*
268 		 * Start creating the modules.
269 		 * Note that attach() routines should
270 		 * register and enable their own interrupts.
271 		 */
272 
273 		if ((px_mmu_attach(px_p)) != DDI_SUCCESS)
274 			goto err_bad_mmu;
275 
276 		if ((px_msiq_attach(px_p)) != DDI_SUCCESS)
277 			goto err_bad_msiq;
278 
279 		if ((px_msi_attach(px_p)) != DDI_SUCCESS)
280 			goto err_bad_msi;
281 
282 		if ((px_pec_attach(px_p)) != DDI_SUCCESS)
283 			goto err_bad_pec;
284 
285 		if ((px_dma_attach(px_p)) != DDI_SUCCESS)
286 			goto err_bad_pec; /* nothing to uninitialize on DMA */
287 
288 		/*
289 		 * All of the error handlers have been registered
290 		 * by now so it's time to activate the interrupt.
291 		 */
292 		if ((ret = px_err_add_intr(&px_p->px_fault)) != DDI_SUCCESS)
293 			goto err_bad_pec_add_intr;
294 
295 		/*
296 		 * Create the "devctl" node for hotplug and pcitool support.
297 		 * For non-hotplug bus, we still need ":devctl" to
298 		 * support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls.
299 		 */
300 		if (ddi_create_minor_node(dip, "devctl", S_IFCHR,
301 		    PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR),
302 		    DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
303 			goto err_bad_devctl_node;
304 		}
305 		/*
306 		 * power management setup. Even if it fails, attach will
307 		 * succeed as this is a optional feature. Since we are
308 		 * always at full power, this is not critical.
309 		 */
310 		if (pwr_common_setup(dip) != DDI_SUCCESS) {
311 			DBG(DBG_PWR, dip, "pwr_common_setup failed\n");
312 		} else if (px_pwr_setup(dip) != DDI_SUCCESS) {
313 			DBG(DBG_PWR, dip, "px_pwr_setup failed \n");
314 			pwr_common_teardown(dip);
315 		}
316 
317 		ddi_report_dev(dip);
318 
319 		px_p->px_state = PX_ATTACHED;
320 		DBG(DBG_ATTACH, dip, "attach success\n");
321 		break;
322 
323 err_bad_devctl_node:
324 		px_err_rem_intr(&px_p->px_fault);
325 err_bad_pec_add_intr:
326 		px_pec_detach(px_p);
327 err_bad_pec:
328 		px_msi_detach(px_p);
329 err_bad_msi:
330 		px_msiq_detach(px_p);
331 err_bad_msiq:
332 		px_mmu_detach(px_p);
333 err_bad_mmu:
334 		px_cb_detach(px_p);
335 err_bad_cb:
336 		px_ib_detach(px_p);
337 err_bad_ib:
338 		(void) px_lib_dev_fini(dip);
339 err_bad_dev_init:
340 		px_fm_detach(px_p);
341 err_bad_fm:
342 		px_free_props(px_p);
343 err_bad_px_prop:
344 		mutex_destroy(&px_p->px_mutex);
345 		ddi_soft_state_free(px_state_p, instance);
346 err_bad_px_softstate:
347 		ret = DDI_FAILURE;
348 		break;
349 
350 	case DDI_RESUME:
351 		DBG(DBG_ATTACH, dip, "DDI_RESUME\n");
352 
353 		px_p = INST_TO_STATE(instance);
354 
355 		mutex_enter(&px_p->px_mutex);
356 
357 		/* suspend might have not succeeded */
358 		if (px_p->px_state != PX_SUSPENDED) {
359 			DBG(DBG_ATTACH, px_p->px_dip,
360 			    "instance NOT suspended\n");
361 			ret = DDI_FAILURE;
362 			break;
363 		}
364 
365 		px_lib_resume(dip);
366 		(void) pcie_pwr_resume(dip);
367 		px_p->px_state = PX_ATTACHED;
368 
369 		mutex_exit(&px_p->px_mutex);
370 
371 		break;
372 	default:
373 		DBG(DBG_ATTACH, dip, "unsupported attach op\n");
374 		ret = DDI_FAILURE;
375 		break;
376 	}
377 
378 	return (ret);
379 }
380 
381 /*
382  * detach entry point:
383  */
384 /*ARGSUSED*/
385 static int
386 px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
387 {
388 	int instance = ddi_get_instance(dip);
389 	px_t *px_p = INST_TO_STATE(instance);
390 	int ret;
391 
392 	/*
393 	 * Make sure we are currently attached
394 	 */
395 	if (px_p->px_state != PX_ATTACHED) {
396 		DBG(DBG_DETACH, dip, "failed - instance not attached\n");
397 		return (DDI_FAILURE);
398 	}
399 
400 	mutex_enter(&px_p->px_mutex);
401 
402 	switch (cmd) {
403 	case DDI_DETACH:
404 		DBG(DBG_DETACH, dip, "DDI_DETACH\n");
405 
406 #ifdef	HOTPLUG
407 		/*
408 		 * Hot plug will be done later.
409 		 */
410 		if (px_p->hotplug_capable == B_TRUE) {
411 			if (pxhp_uninit(dip) == DDI_FAILURE) {
412 				mutex_exit(&px_p->px_mutex);
413 				return (DDI_FAILURE);
414 			}
415 		}
416 #endif	/* HOTPLUG */
417 
418 		/*
419 		 * things which used to be done in obj_destroy
420 		 * are now in-lined here.
421 		 */
422 
423 		px_p->px_state = PX_DETACHED;
424 
425 		ddi_remove_minor_node(dip, "devctl");
426 		px_err_rem_intr(&px_p->px_fault);
427 		px_pec_detach(px_p);
428 		px_msi_detach(px_p);
429 		px_msiq_detach(px_p);
430 		px_mmu_detach(px_p);
431 		px_cb_detach(px_p);
432 		px_ib_detach(px_p);
433 		(void) px_lib_dev_fini(dip);
434 		px_fm_detach(px_p);
435 
436 		/*
437 		 * Free the px soft state structure and the rest of the
438 		 * resources it's using.
439 		 */
440 		px_free_props(px_p);
441 		px_pwr_teardown(dip);
442 		pwr_common_teardown(dip);
443 		mutex_exit(&px_p->px_mutex);
444 		mutex_destroy(&px_p->px_mutex);
445 		ddi_soft_state_free(px_state_p, instance);
446 
447 		/* Free the interrupt-priorities prop if we created it. */ {
448 			int len;
449 
450 			if (ddi_getproplen(DDI_DEV_T_ANY, dip,
451 			    DDI_PROP_NOTPROM | DDI_PROP_DONTPASS,
452 			    "interrupt-priorities", &len) == DDI_PROP_SUCCESS)
453 				(void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
454 				    "interrupt-priorities");
455 		}
456 
457 		px_p->px_dev_hdl = NULL;
458 
459 		return (DDI_SUCCESS);
460 
461 	case DDI_SUSPEND:
462 		if (pcie_pwr_suspend(dip) != DDI_SUCCESS) {
463 			mutex_exit(&px_p->px_mutex);
464 			return (DDI_FAILURE);
465 		}
466 		if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS)
467 			px_p->px_state = PX_SUSPENDED;
468 		mutex_exit(&px_p->px_mutex);
469 
470 		return (ret);
471 
472 	default:
473 		DBG(DBG_DETACH, dip, "unsupported detach op\n");
474 		mutex_exit(&px_p->px_mutex);
475 		return (DDI_FAILURE);
476 	}
477 }
478 
479 /*
480  * power management related initialization specific to px
481  * called by px_attach()
482  */
483 static int
484 px_pwr_setup(dev_info_t *dip)
485 {
486 	pcie_pwr_t *pwr_p;
487 	int instance = ddi_get_instance(dip);
488 	px_t *px_p = INST_TO_STATE(instance);
489 	ddi_intr_handle_impl_t hdl;
490 	ddi_iblock_cookie_t iblk_cookie;
491 
492 	ASSERT(PCIE_PMINFO(dip));
493 	pwr_p = PCIE_NEXUS_PMINFO(dip);
494 	ASSERT(pwr_p);
495 
496 	/*
497 	 * indicate support LDI (Layered Driver Interface)
498 	 * Create the property, if it is not already there
499 	 */
500 	if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
501 	    DDI_KERNEL_IOCTL)) {
502 		if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP,
503 		    DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) {
504 			DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n");
505 			return (DDI_FAILURE);
506 		}
507 	}
508 	/* No support for device PM. We are always at full power */
509 	pwr_p->pwr_func_lvl = PM_LEVEL_D0;
510 
511 	mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER,
512 	    (void *)px_pwr_pil);
513 	cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL);
514 
515 	mutex_init(&px_p->px_lup_lock, NULL, MUTEX_DRIVER,
516 	    (void *)PX_ERR_PIL);
517 	cv_init(&px_p->px_lup_cv, NULL, CV_DRIVER, NULL);
518 
519 	if (ddi_get_soft_iblock_cookie(dip, DDI_SOFTINT_HIGH,
520 	    &iblk_cookie) != DDI_SUCCESS) {
521 		DBG(DBG_PWR, dip, "px_pwr_setup: couldn't get iblock cookie\n");
522 		goto pwr_setup_err1;
523 	}
524 	mutex_init(&px_p->px_lupsoft_lock, NULL, MUTEX_DRIVER,
525 	    (void *)iblk_cookie);
526 	if (ddi_add_softintr(dip, DDI_SOFTINT_HIGH, &px_p->px_lupsoft_id,
527 	    NULL, NULL, px_lup_softintr, (caddr_t)px_p) != DDI_SUCCESS) {
528 		DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add soft intr \n");
529 		goto pwr_setup_err2;
530 	}
531 
532 	/* Initilize handle */
533 	hdl.ih_cb_arg1 = px_p;
534 	hdl.ih_cb_arg2 = NULL;
535 	hdl.ih_ver = DDI_INTR_VERSION;
536 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
537 	hdl.ih_dip = dip;
538 	hdl.ih_inum = 0;
539 	hdl.ih_pri = px_pwr_pil;
540 
541 	/* Add PME_TO_ACK message handler */
542 	hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr;
543 	if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC,
544 	    (msgcode_t)PCIE_PME_ACK_MSG, &px_p->px_pm_msiq_id) != DDI_SUCCESS) {
545 		DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add "
546 		    " PME_TO_ACK intr\n");
547 		goto px_pwrsetup_err;
548 	}
549 	px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id);
550 	px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID);
551 
552 	return (DDI_SUCCESS);
553 
554 px_pwrsetup_err:
555 	ddi_remove_softintr(px_p->px_lupsoft_id);
556 pwr_setup_err2:
557 	mutex_destroy(&px_p->px_lupsoft_lock);
558 pwr_setup_err1:
559 	mutex_destroy(&px_p->px_lup_lock);
560 	cv_destroy(&px_p->px_lup_cv);
561 	mutex_destroy(&px_p->px_l23ready_lock);
562 	cv_destroy(&px_p->px_l23ready_cv);
563 
564 	return (DDI_FAILURE);
565 }
566 
567 /*
568  * undo whatever is done in px_pwr_setup. called by px_detach()
569  */
570 static void
571 px_pwr_teardown(dev_info_t *dip)
572 {
573 	int instance = ddi_get_instance(dip);
574 	px_t *px_p = INST_TO_STATE(instance);
575 	ddi_intr_handle_impl_t	hdl;
576 
577 	if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip))
578 		return;
579 
580 	/* Initilize handle */
581 	hdl.ih_ver = DDI_INTR_VERSION;
582 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
583 	hdl.ih_dip = dip;
584 	hdl.ih_inum = 0;
585 
586 	px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
587 	(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
588 	    px_p->px_pm_msiq_id);
589 
590 	px_p->px_pm_msiq_id = -1;
591 
592 	cv_destroy(&px_p->px_l23ready_cv);
593 	ddi_remove_softintr(px_p->px_lupsoft_id);
594 	mutex_destroy(&px_p->px_lupsoft_lock);
595 	mutex_destroy(&px_p->px_lup_lock);
596 	mutex_destroy(&px_p->px_l23ready_lock);
597 }
598 
599 /* bus driver entry points */
600 
601 /*
602  * bus map entry point:
603  *
604  * 	if map request is for an rnumber
605  *		get the corresponding regspec from device node
606  * 	build a new regspec in our parent's format
607  *	build a new map_req with the new regspec
608  *	call up the tree to complete the mapping
609  */
610 int
611 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
612 	off_t off, off_t len, caddr_t *addrp)
613 {
614 	px_t *px_p = DIP_TO_STATE(dip);
615 	struct regspec p_regspec;
616 	ddi_map_req_t p_mapreq;
617 	int reglen, rval, r_no;
618 	pci_regspec_t reloc_reg, *rp = &reloc_reg;
619 
620 	DBG(DBG_MAP, dip, "rdip=%s%d:",
621 		ddi_driver_name(rdip), ddi_get_instance(rdip));
622 
623 	if (mp->map_flags & DDI_MF_USER_MAPPING)
624 		return (DDI_ME_UNIMPLEMENTED);
625 
626 	switch (mp->map_type) {
627 	case DDI_MT_REGSPEC:
628 		reloc_reg = *(pci_regspec_t *)mp->map_obj.rp;	/* dup whole */
629 		break;
630 
631 	case DDI_MT_RNUMBER:
632 		r_no = mp->map_obj.rnumber;
633 		DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no);
634 
635 		if (ddi_getlongprop(DDI_DEV_T_NONE, rdip, DDI_PROP_DONTPASS,
636 			"reg", (caddr_t)&rp, &reglen) != DDI_SUCCESS)
637 				return (DDI_ME_RNUMBER_RANGE);
638 
639 		if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) {
640 			kmem_free(rp, reglen);
641 			return (DDI_ME_RNUMBER_RANGE);
642 		}
643 		rp += r_no;
644 		break;
645 
646 	default:
647 		return (DDI_ME_INVAL);
648 	}
649 	DBG(DBG_MAP | DBG_CONT, dip, "\n");
650 
651 	if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) {
652 		/*
653 		 * There may be a need to differentiate between PCI
654 		 * and PCI-Ex devices so the following range check is
655 		 * done correctly, depending on the implementation of
656 		 * px_pci bridge nexus driver.
657 		 */
658 		if ((off >= PCIE_CONF_HDR_SIZE) ||
659 				(len > PCIE_CONF_HDR_SIZE) ||
660 				(off + len > PCIE_CONF_HDR_SIZE))
661 			return (DDI_ME_INVAL);
662 		/*
663 		 * the following function returning a DDI_FAILURE assumes
664 		 * that there are no virtual config space access services
665 		 * defined in this layer. Otherwise it is availed right
666 		 * here and we return.
667 		 */
668 		rval = px_lib_map_vconfig(dip, mp, off, rp, addrp);
669 		if (rval == DDI_SUCCESS)
670 			goto done;
671 	}
672 
673 	/*
674 	 * No virtual config space services or we are mapping
675 	 * a region of memory mapped config/IO/memory space, so proceed
676 	 * to the parent.
677 	 */
678 
679 	/* relocate within 64-bit pci space through "assigned-addresses" */
680 	if (rval = px_reloc_reg(dip, rdip, px_p, rp))
681 		goto done;
682 
683 	if (len)	/* adjust regspec according to mapping request */
684 		rp->pci_size_low = len;	/* MIN ? */
685 	rp->pci_phys_low += off;
686 
687 	/* translate relocated pci regspec into parent space through "ranges" */
688 	if (rval = px_xlate_reg(px_p, rp, &p_regspec))
689 		goto done;
690 
691 	p_mapreq = *mp;		/* dup the whole structure */
692 	p_mapreq.map_type = DDI_MT_REGSPEC;
693 	p_mapreq.map_obj.rp = &p_regspec;
694 	rval = ddi_map(dip, &p_mapreq, 0, 0, addrp);
695 
696 	if (rval == DDI_SUCCESS) {
697 		/*
698 		 * Set-up access functions for FM access error capable drivers.
699 		 */
700 		if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)) &&
701 		    mp->map_handlep->ah_acc.devacc_attr_access !=
702 		    DDI_DEFAULT_ACC)
703 			px_fm_acc_setup(mp, rdip);
704 	}
705 
706 done:
707 	if (mp->map_type == DDI_MT_RNUMBER)
708 		kmem_free(rp - r_no, reglen);
709 
710 	return (rval);
711 }
712 
713 /*
714  * bus dma map entry point
715  * return value:
716  *	DDI_DMA_PARTIAL_MAP	 1
717  *	DDI_DMA_MAPOK		 0
718  *	DDI_DMA_MAPPED		 0
719  *	DDI_DMA_NORESOURCES	-1
720  *	DDI_DMA_NOMAPPING	-2
721  *	DDI_DMA_TOOBIG		-3
722  */
723 int
724 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq,
725 	ddi_dma_handle_t *handlep)
726 {
727 	px_t *px_p = DIP_TO_STATE(dip);
728 	px_mmu_t *mmu_p = px_p->px_mmu_p;
729 	ddi_dma_impl_t *mp;
730 	int ret;
731 
732 	DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n",
733 		ddi_driver_name(rdip), ddi_get_instance(rdip),
734 		handlep ? "alloc" : "advisory");
735 
736 	if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq)))
737 		return (DDI_DMA_NORESOURCES);
738 	if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING)
739 		return (DDI_DMA_NOMAPPING);
740 	if (ret = px_dma_type(px_p, dmareq, mp))
741 		goto freehandle;
742 	if (ret = px_dma_pfn(px_p, dmareq, mp))
743 		goto freehandle;
744 
745 	switch (PX_DMA_TYPE(mp)) {
746 	case DMAI_FLAGS_DVMA:	/* LINTED E_EQUALITY_NOT_ASSIGNMENT */
747 		if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep)
748 			goto freehandle;
749 		if (!PX_DMA_CANCACHE(mp)) {	/* try fast track */
750 			if (PX_DMA_CANFAST(mp)) {
751 				if (!px_dvma_map_fast(mmu_p, mp))
752 					break;
753 			/* LINTED E_NOP_ELSE_STMT */
754 			} else {
755 				PX_DVMA_FASTTRAK_PROF(mp);
756 			}
757 		}
758 		if (ret = px_dvma_map(mp, dmareq, mmu_p))
759 			goto freehandle;
760 		break;
761 	case DMAI_FLAGS_PTP:	/* LINTED E_EQUALITY_NOT_ASSIGNMENT */
762 		if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep)
763 			goto freehandle;
764 		break;
765 	case DMAI_FLAGS_BYPASS:
766 	default:
767 		cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x",
768 			ddi_driver_name(rdip), ddi_get_instance(rdip),
769 			PX_DMA_TYPE(mp));
770 		/*NOTREACHED*/
771 	}
772 	*handlep = (ddi_dma_handle_t)mp;
773 	mp->dmai_flags |= DMAI_FLAGS_INUSE;
774 	px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
775 
776 	return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
777 freehandle:
778 	if (ret == DDI_DMA_NORESOURCES)
779 		px_dma_freemp(mp); /* don't run_callback() */
780 	else
781 		(void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
782 	return (ret);
783 }
784 
785 
786 /*
787  * bus dma alloc handle entry point:
788  */
789 int
790 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
791 	int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep)
792 {
793 	px_t *px_p = DIP_TO_STATE(dip);
794 	ddi_dma_impl_t *mp;
795 	int rval;
796 
797 	DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n",
798 		ddi_driver_name(rdip), ddi_get_instance(rdip));
799 
800 	if (attrp->dma_attr_version != DMA_ATTR_V0)
801 		return (DDI_DMA_BADATTR);
802 
803 	if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg)))
804 		return (DDI_DMA_NORESOURCES);
805 
806 	/*
807 	 * Save requestor's information
808 	 */
809 	mp->dmai_attr	= *attrp; /* whole object - augmented later  */
810 	*DEV_ATTR(mp)	= *attrp; /* whole object - device orig attr */
811 	DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp);
812 
813 	/* check and convert dma attributes to handle parameters */
814 	if (rval = px_dma_attr2hdl(px_p, mp)) {
815 		px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
816 		*handlep = NULL;
817 		return (rval);
818 	}
819 	*handlep = (ddi_dma_handle_t)mp;
820 	return (DDI_SUCCESS);
821 }
822 
823 
824 /*
825  * bus dma free handle entry point:
826  */
827 /*ARGSUSED*/
828 int
829 px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
830 {
831 	DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n",
832 		ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
833 	px_dma_freemp((ddi_dma_impl_t *)handle);
834 
835 	if (px_kmem_clid) {
836 		DBG(DBG_DMA_FREEH, dip, "run handle callback\n");
837 		ddi_run_callback(&px_kmem_clid);
838 	}
839 	return (DDI_SUCCESS);
840 }
841 
842 
843 /*
844  * bus dma bind handle entry point:
845  */
846 int
847 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
848 	ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
849 	ddi_dma_cookie_t *cookiep, uint_t *ccountp)
850 {
851 	px_t *px_p = DIP_TO_STATE(dip);
852 	px_mmu_t *mmu_p = px_p->px_mmu_p;
853 	ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
854 	int ret;
855 
856 	DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n",
857 		ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq);
858 
859 	if (mp->dmai_flags & DMAI_FLAGS_INUSE)
860 		return (DDI_DMA_INUSE);
861 
862 	ASSERT((mp->dmai_flags & ~DMAI_FLAGS_PRESERVE) == 0);
863 	mp->dmai_flags |= DMAI_FLAGS_INUSE;
864 
865 	if (ret = px_dma_type(px_p, dmareq, mp))
866 		goto err;
867 	if (ret = px_dma_pfn(px_p, dmareq, mp))
868 		goto err;
869 
870 	switch (PX_DMA_TYPE(mp)) {
871 	case DMAI_FLAGS_DVMA:
872 		if (ret = px_dvma_win(px_p, dmareq, mp))
873 			goto map_err;
874 		if (!PX_DMA_CANCACHE(mp)) {	/* try fast track */
875 			if (PX_DMA_CANFAST(mp)) {
876 				if (!px_dvma_map_fast(mmu_p, mp))
877 					goto mapped; /*LINTED E_NOP_ELSE_STMT*/
878 			} else {
879 				PX_DVMA_FASTTRAK_PROF(mp);
880 			}
881 		}
882 		if (ret = px_dvma_map(mp, dmareq, mmu_p))
883 			goto map_err;
884 mapped:
885 		*ccountp = 1;
886 		MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size);
887 		break;
888 	case DMAI_FLAGS_BYPASS:
889 	case DMAI_FLAGS_PTP:
890 		if (ret = px_dma_physwin(px_p, dmareq, mp))
891 			goto map_err;
892 		*ccountp = WINLST(mp)->win_ncookies;
893 		*cookiep = *(ddi_dma_cookie_t *)(WINLST(mp) + 1); /* wholeobj */
894 		break;
895 	default:
896 		cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type",
897 			ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
898 		/*NOTREACHED*/
899 	}
900 	DBG(DBG_DMA_BINDH, dip, "cookie %llx+%x\n", cookiep->dmac_address,
901 		cookiep->dmac_size);
902 	px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
903 
904 	/* insert dma handle into FMA cache */
905 	if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR)
906 		(void) ndi_fmc_insert(rdip, DMA_HANDLE, mp, NULL);
907 
908 	return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
909 map_err:
910 	px_dma_freepfn(mp);
911 err:
912 	mp->dmai_flags &= DMAI_FLAGS_PRESERVE;
913 	return (ret);
914 }
915 
916 
917 /*
918  * bus dma unbind handle entry point:
919  */
920 /*ARGSUSED*/
921 int
922 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
923 {
924 	ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
925 	px_t *px_p = DIP_TO_STATE(dip);
926 	px_mmu_t *mmu_p = px_p->px_mmu_p;
927 
928 	DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n",
929 		ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
930 	if ((mp->dmai_flags & DMAI_FLAGS_INUSE) == 0) {
931 		DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n");
932 		return (DDI_FAILURE);
933 	}
934 
935 	/* remove dma handle from FMA cache */
936 	if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) {
937 		if (DEVI(rdip)->devi_fmhdl != NULL &&
938 		    DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap)) {
939 			(void) ndi_fmc_remove(rdip, DMA_HANDLE, mp);
940 		}
941 	}
942 
943 	/*
944 	 * Here if the handle is using the iommu.  Unload all the iommu
945 	 * translations.
946 	 */
947 	switch (PX_DMA_TYPE(mp)) {
948 	case DMAI_FLAGS_DVMA:
949 		px_mmu_unmap_window(mmu_p, mp);
950 		px_dvma_unmap(mmu_p, mp);
951 		px_dma_freepfn(mp);
952 		break;
953 	case DMAI_FLAGS_BYPASS:
954 	case DMAI_FLAGS_PTP:
955 		px_dma_freewin(mp);
956 		break;
957 	default:
958 		cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p",
959 			ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
960 		/*NOTREACHED*/
961 	}
962 	if (mmu_p->mmu_dvma_clid != 0) {
963 		DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n");
964 		ddi_run_callback(&mmu_p->mmu_dvma_clid);
965 	}
966 	if (px_kmem_clid) {
967 		DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n");
968 		ddi_run_callback(&px_kmem_clid);
969 	}
970 	mp->dmai_flags &= DMAI_FLAGS_PRESERVE;
971 
972 	return (DDI_SUCCESS);
973 }
974 
975 /*
976  * bus dma win entry point:
977  */
978 int
979 px_dma_win(dev_info_t *dip, dev_info_t *rdip,
980 	ddi_dma_handle_t handle, uint_t win, off_t *offp,
981 	size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp)
982 {
983 	ddi_dma_impl_t	*mp = (ddi_dma_impl_t *)handle;
984 	int		ret;
985 
986 	DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n",
987 		ddi_driver_name(rdip), ddi_get_instance(rdip));
988 
989 	px_dump_dma_handle(DBG_DMA_WIN, dip, mp);
990 	if (win >= mp->dmai_nwin) {
991 		DBG(DBG_DMA_WIN, dip, "%x out of range\n", win);
992 		return (DDI_FAILURE);
993 	}
994 
995 	switch (PX_DMA_TYPE(mp)) {
996 	case DMAI_FLAGS_DVMA:
997 		if (win != PX_DMA_CURWIN(mp)) {
998 			px_t *px_p = DIP_TO_STATE(dip);
999 			px_mmu_t *mmu_p = px_p->px_mmu_p;
1000 			px_mmu_unmap_window(mmu_p, mp);
1001 
1002 			/* map_window sets dmai_mapping/size/offset */
1003 			px_mmu_map_window(mmu_p, mp, win);
1004 			if ((ret = px_mmu_map_window(mmu_p,
1005 			    mp, win)) != DDI_SUCCESS)
1006 				return (ret);
1007 		}
1008 		if (cookiep)
1009 			MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping,
1010 				mp->dmai_size);
1011 		if (ccountp)
1012 			*ccountp = 1;
1013 		break;
1014 	case DMAI_FLAGS_PTP:
1015 	case DMAI_FLAGS_BYPASS: {
1016 		int i;
1017 		ddi_dma_cookie_t *ck_p;
1018 		px_dma_win_t *win_p = mp->dmai_winlst;
1019 
1020 		for (i = 0; i < win; win_p = win_p->win_next, i++);
1021 		ck_p = (ddi_dma_cookie_t *)(win_p + 1);
1022 		*cookiep = *ck_p;
1023 		mp->dmai_offset = win_p->win_offset;
1024 		mp->dmai_size   = win_p->win_size;
1025 		mp->dmai_mapping = ck_p->dmac_laddress;
1026 		mp->dmai_cookie = ck_p + 1;
1027 		win_p->win_curseg = 0;
1028 		if (ccountp)
1029 			*ccountp = win_p->win_ncookies;
1030 		}
1031 		break;
1032 	default:
1033 		cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x",
1034 			ddi_driver_name(rdip), ddi_get_instance(rdip),
1035 			PX_DMA_TYPE(mp));
1036 		return (DDI_FAILURE);
1037 	}
1038 	if (cookiep)
1039 		DBG(DBG_DMA_WIN, dip,
1040 			"cookie - dmac_address=%x dmac_size=%x\n",
1041 			cookiep->dmac_address, cookiep->dmac_size);
1042 	if (offp)
1043 		*offp = (off_t)mp->dmai_offset;
1044 	if (lenp)
1045 		*lenp = mp->dmai_size;
1046 	return (DDI_SUCCESS);
1047 }
1048 
1049 #ifdef	DEBUG
1050 static char *px_dmactl_str[] = {
1051 	"DDI_DMA_FREE",
1052 	"DDI_DMA_SYNC",
1053 	"DDI_DMA_HTOC",
1054 	"DDI_DMA_KVADDR",
1055 	"DDI_DMA_MOVWIN",
1056 	"DDI_DMA_REPWIN",
1057 	"DDI_DMA_GETERR",
1058 	"DDI_DMA_COFF",
1059 	"DDI_DMA_NEXTWIN",
1060 	"DDI_DMA_NEXTSEG",
1061 	"DDI_DMA_SEGTOC",
1062 	"DDI_DMA_RESERVE",
1063 	"DDI_DMA_RELEASE",
1064 	"DDI_DMA_RESETH",
1065 	"DDI_DMA_CKSYNC",
1066 	"DDI_DMA_IOPB_ALLOC",
1067 	"DDI_DMA_IOPB_FREE",
1068 	"DDI_DMA_SMEM_ALLOC",
1069 	"DDI_DMA_SMEM_FREE",
1070 	"DDI_DMA_SET_SBUS64"
1071 };
1072 #endif	/* DEBUG */
1073 
1074 /*
1075  * bus dma control entry point:
1076  */
1077 /*ARGSUSED*/
1078 int
1079 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
1080 	enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
1081 	uint_t cache_flags)
1082 {
1083 	ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
1084 
1085 #ifdef	DEBUG
1086 	DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd],
1087 		ddi_driver_name(rdip), ddi_get_instance(rdip));
1088 #endif	/* DEBUG */
1089 
1090 	switch (cmd) {
1091 	case DDI_DMA_FREE:
1092 		(void) px_dma_unbindhdl(dip, rdip, handle);
1093 		(void) px_dma_freehdl(dip, rdip, handle);
1094 		return (DDI_SUCCESS);
1095 	case DDI_DMA_RESERVE: {
1096 		px_t *px_p = DIP_TO_STATE(dip);
1097 		return (px_fdvma_reserve(dip, rdip, px_p,
1098 			(ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp));
1099 		}
1100 	case DDI_DMA_RELEASE: {
1101 		px_t *px_p = DIP_TO_STATE(dip);
1102 		return (px_fdvma_release(dip, px_p, mp));
1103 		}
1104 	default:
1105 		break;
1106 	}
1107 
1108 	switch (PX_DMA_TYPE(mp)) {
1109 	case DMAI_FLAGS_DVMA:
1110 		return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
1111 			cache_flags));
1112 	case DMAI_FLAGS_PTP:
1113 	case DMAI_FLAGS_BYPASS:
1114 		return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
1115 			cache_flags));
1116 	default:
1117 		cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x",
1118 			ddi_driver_name(rdip), ddi_get_instance(rdip), cmd,
1119 			mp->dmai_flags);
1120 		/*NOTREACHED*/
1121 	}
1122 }
1123 
1124 /*
1125  * control ops entry point:
1126  *
1127  * Requests handled completely:
1128  *	DDI_CTLOPS_INITCHILD	see init_child() for details
1129  *	DDI_CTLOPS_UNINITCHILD
1130  *	DDI_CTLOPS_REPORTDEV	see report_dev() for details
1131  *	DDI_CTLOPS_XLATE_INTRS	nothing to do
1132  *	DDI_CTLOPS_IOMIN	cache line size if streaming otherwise 1
1133  *	DDI_CTLOPS_REGSIZE
1134  *	DDI_CTLOPS_NREGS
1135  *	DDI_CTLOPS_NINTRS
1136  *	DDI_CTLOPS_DVMAPAGESIZE
1137  *	DDI_CTLOPS_POKE
1138  *	DDI_CTLOPS_PEEK
1139  *
1140  * All others passed to parent.
1141  */
1142 int
1143 px_ctlops(dev_info_t *dip, dev_info_t *rdip,
1144 	ddi_ctl_enum_t op, void *arg, void *result)
1145 {
1146 	px_t *px_p = DIP_TO_STATE(dip);
1147 	struct detachspec *ds;
1148 	struct attachspec *as;
1149 
1150 	switch (op) {
1151 	case DDI_CTLOPS_INITCHILD:
1152 		return (px_init_child(px_p, (dev_info_t *)arg));
1153 
1154 	case DDI_CTLOPS_UNINITCHILD:
1155 		return (px_uninit_child(px_p, (dev_info_t *)arg));
1156 
1157 	case DDI_CTLOPS_ATTACH:
1158 		as = (struct attachspec *)arg;
1159 		switch (as->when) {
1160 		case DDI_PRE:
1161 			if (as->cmd == DDI_ATTACH) {
1162 				DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n",
1163 				    ddi_driver_name(rdip),
1164 				    ddi_get_instance(rdip));
1165 				return (pcie_pm_hold(dip));
1166 			}
1167 			return (DDI_SUCCESS);
1168 
1169 		case DDI_POST:
1170 			DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n",
1171 			    ddi_driver_name(rdip), ddi_get_instance(rdip));
1172 			if (as->cmd == DDI_ATTACH && as->result != DDI_SUCCESS)
1173 				pcie_pm_release(dip);
1174 			return (DDI_SUCCESS);
1175 		default:
1176 			break;
1177 		}
1178 		break;
1179 
1180 	case DDI_CTLOPS_DETACH:
1181 		ds = (struct detachspec *)arg;
1182 		switch (ds->when) {
1183 		case DDI_POST:
1184 			if (ds->cmd == DDI_DETACH &&
1185 			    ds->result == DDI_SUCCESS) {
1186 				DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n",
1187 				    ddi_driver_name(rdip),
1188 				    ddi_get_instance(rdip));
1189 				return (pcie_pm_remove_child(dip, rdip));
1190 			}
1191 			return (DDI_SUCCESS);
1192 		default:
1193 			break;
1194 		}
1195 		break;
1196 
1197 	case DDI_CTLOPS_REPORTDEV:
1198 		return (px_report_dev(rdip));
1199 
1200 	case DDI_CTLOPS_IOMIN:
1201 		return (DDI_SUCCESS);
1202 
1203 	case DDI_CTLOPS_REGSIZE:
1204 		*((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg));
1205 		return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS);
1206 
1207 	case DDI_CTLOPS_NREGS:
1208 		*((uint_t *)result) = px_get_nreg_set(rdip);
1209 		return (DDI_SUCCESS);
1210 
1211 	case DDI_CTLOPS_DVMAPAGESIZE:
1212 		*((ulong_t *)result) = MMU_PAGE_SIZE;
1213 		return (DDI_SUCCESS);
1214 
1215 	case DDI_CTLOPS_POKE:	/* platform dependent implementation. */
1216 		return (px_lib_ctlops_poke(dip, rdip,
1217 		    (peekpoke_ctlops_t *)arg));
1218 
1219 	case DDI_CTLOPS_PEEK:	/* platform dependent implementation. */
1220 		return (px_lib_ctlops_peek(dip, rdip,
1221 		    (peekpoke_ctlops_t *)arg, result));
1222 
1223 	case DDI_CTLOPS_POWER:
1224 	default:
1225 		break;
1226 	}
1227 
1228 	/*
1229 	 * Now pass the request up to our parent.
1230 	 */
1231 	DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n",
1232 		ddi_driver_name(rdip), ddi_get_instance(rdip));
1233 	return (ddi_ctlops(dip, rdip, op, arg, result));
1234 }
1235 
1236 /* ARGSUSED */
1237 int
1238 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
1239     ddi_intr_handle_impl_t *hdlp, void *result)
1240 {
1241 	int	intr_types, ret = DDI_SUCCESS;
1242 
1243 	DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n",
1244 	    ddi_driver_name(rdip), ddi_get_instance(rdip));
1245 
1246 	/* Process DDI_INTROP_SUPPORTED_TYPES request here */
1247 	if (intr_op == DDI_INTROP_SUPPORTED_TYPES) {
1248 		px_t		*px_p = DIP_TO_STATE(dip);
1249 		px_msi_state_t	*msi_state_p = &px_p->px_ib_p->ib_msi_state;
1250 
1251 		*(int *)result = i_ddi_get_nintrs(rdip) ?
1252 		    DDI_INTR_TYPE_FIXED : 0;
1253 
1254 		if ((pci_msi_get_supported_type(rdip,
1255 		    &intr_types)) == DDI_SUCCESS) {
1256 			/*
1257 			 * Double check supported interrupt types vs.
1258 			 * what the host bridge supports.
1259 			 */
1260 			*(int *)result |= (intr_types & msi_state_p->msi_type);
1261 		}
1262 
1263 		return (ret);
1264 	}
1265 
1266 	/*
1267 	 * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts.
1268 	 * Return failure if interrupt type is not supported.
1269 	 */
1270 	switch (hdlp->ih_type) {
1271 	case DDI_INTR_TYPE_FIXED:
1272 		ret = px_intx_ops(dip, rdip, intr_op, hdlp, result);
1273 		break;
1274 	case DDI_INTR_TYPE_MSI:
1275 	case DDI_INTR_TYPE_MSIX:
1276 		ret = px_msix_ops(dip, rdip, intr_op, hdlp, result);
1277 		break;
1278 	default:
1279 		ret = DDI_ENOTSUP;
1280 		break;
1281 	}
1282 
1283 	return (ret);
1284 }
1285