xref: /titanic_50/usr/src/uts/sparc/sys/cpu.h (revision 69112edd987c28fa551d4f8d9362a84a45365f17)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_CPU_H
27 #define	_SYS_CPU_H
28 
29 /*
30  * Include generic bustype cookies.
31  */
32 #include <sys/bustypes.h>
33 
34 #if defined(_KERNEL)
35 #if defined(__GNUC__) && defined(_ASM_INLINES)
36 #include <asm/cpu.h>
37 #endif
38 #endif	/* _KERNEL */
39 
40 #ifdef	__cplusplus
41 extern "C" {
42 #endif
43 
44 
45 /*
46  * Global kernel variables of interest
47  */
48 
49 #if defined(_KERNEL) && !defined(_ASM)
50 
51 extern int dvmasize;			/* usable dvma size in pages */
52 
53 /*
54  * Cache defines
55  *
56  * Each bit represents an attribute of the system's caches that
57  * the OS must handle.  For example, VAC caches must have virtual
58  * alias detection, VTAG caches must be flushed on every demap, etc.
59  */
60 #define	CACHE_NONE		0	/* No caches of any type */
61 #define	CACHE_VAC		0x01	/* Virtual addressed cache */
62 #define	CACHE_VTAG		0x02	/* Virtual tagged cache */
63 #define	CACHE_PAC		0x04	/* Physical addressed cache */
64 #define	CACHE_PTAG		0x08	/* Physical tagged cache */
65 #define	CACHE_WRITEBACK		0x10	/* Writeback cache */
66 #define	CACHE_IOCOHERENT	0x20	/* I/O coherent cache */
67 
68 extern int cache;
69 
70 /* set this to zero if no vac */
71 extern int vac;
72 
73 /*
74  * Use to insert cpu-dependent instructions into spin loops
75  */
76 #pragma	weak	cpu_smt_pause
77 extern  void	cpu_smt_pause();
78 #define	SMT_PAUSE()	{ if (&cpu_smt_pause) cpu_smt_pause(); }
79 
80 #endif /* defined(_KERNEL) && !defined(_ASM) */
81 
82 #ifdef	__cplusplus
83 }
84 #endif
85 
86 #endif	/* _SYS_CPU_H */
87