1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_X86_ARCHEXT_H 27 #define _SYS_X86_ARCHEXT_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #if !defined(_ASM) 32 #include <sys/regset.h> 33 #include <sys/processor.h> 34 #include <vm/seg_enum.h> 35 #include <vm/page.h> 36 #endif /* _ASM */ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * cpuid instruction feature flags in %edx (standard function 1) 44 */ 45 46 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 47 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 48 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 49 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 50 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 51 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 52 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 53 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 54 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 55 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 56 /* 0x400 - reserved */ 57 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 58 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 59 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 60 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 61 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 62 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 63 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 64 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 65 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 66 /* 0x100000 - reserved */ 67 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 68 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 69 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 70 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 71 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 72 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 73 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 74 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 75 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 76 /* 0x40000000 - reserved */ 77 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 78 79 #define FMT_CPUID_INTC_EDX \ 80 "\20" \ 81 "\40pbe\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 82 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat"\ 83 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 84 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 85 86 /* 87 * cpuid instruction feature flags in %ecx (standard function 1) 88 */ 89 90 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 91 /* 0x00000002 - reserved */ 92 /* 0x00000004 - reserved */ 93 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 94 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 95 /* 0x00000020 - reserved */ 96 /* 0x00000040 - reserved */ 97 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 98 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 99 /* 0x00000200 - reserved */ 100 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 101 /* 0x00000800 - reserved */ 102 /* 0x00001000 - reserved */ 103 /* 0x00002000 - reserved */ 104 #define CPUID_INTC_ECX_CX16 0x00002000 /* CMPXCHG16B */ 105 #define CPUID_INTC_ECX_XTPR 0x00004000 /* disable task pri messages */ 106 107 #define FMT_CPUID_INTC_ECX \ 108 "\20" \ 109 "\20\17xtpr\16cx16\13cid\11tm2" \ 110 "\10est\5dscpl\4monitor\1sse3" 111 112 /* 113 * cpuid instruction feature flags in %edx (extended function 0x80000001) 114 */ 115 116 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 117 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 118 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 119 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 120 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 121 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 122 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 123 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 124 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 125 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 126 /* 0x00000400 - sysc on K6m6 */ 127 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 128 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 129 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 130 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 131 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 132 #define CPUID_AMD_EDX_PAT 0x00010000 /* page attribute table */ 133 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 134 /* 0x00040000 - reserved */ 135 /* 0x00080000 - reserved */ 136 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 137 /* 0x00200000 - reserved */ 138 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 139 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 140 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 141 /* 0x02000000 - reserved */ 142 /* 0x04000000 - reserved */ 143 /* 0x08000000 - reserved */ 144 /* 0x10000000 - reserved */ 145 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 146 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 147 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 148 149 #define FMT_CPUID_AMD_EDX \ 150 "\20" \ 151 "\40a3d\37a3d+\36lm\31fxsr" \ 152 "\30mmx\27mmxext\25nx\22pse\21pat" \ 153 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 154 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 155 156 #define CPUID_AMD_ECX_CMP_LEGACY 0x00000002 /* AMD: multi-core chip */ 157 158 #define FMT_CPUID_AMD_ECX \ 159 "\20" \ 160 "\1htvalid" 161 162 #define P5_MCHADDR 0x0 163 #define P5_CESR 0x11 164 #define P5_CTR0 0x12 165 #define P5_CTR1 0x13 166 167 #define K5_MCHADDR 0x0 168 #define K5_MCHTYPE 0x01 169 #define K5_TSC 0x10 170 #define K5_TR12 0x12 171 172 #define REG_MTRRCAP 0xfe 173 #define REG_MTRRDEF 0x2ff 174 #define REG_MTRR64K 0x250 175 #define REG_MTRR16K1 0x258 176 #define REG_MTRR16K2 0x259 177 #define REG_MTRR4K1 0x268 178 #define REG_MTRR4K2 0x269 179 #define REG_MTRR4K3 0x26a 180 #define REG_MTRR4K4 0x26b 181 #define REG_MTRR4K5 0x26c 182 #define REG_MTRR4K6 0x26d 183 #define REG_MTRR4K7 0x26e 184 #define REG_MTRR4K8 0x26f 185 #define REG_MTRRPAT 0x277 186 187 #define REG_MTRRPHYSBASE0 0x200 188 #define REG_MTRRPHYSMASK7 0x20f 189 #define REG_MC0_CTL 0x400 190 #define REG_MC5_MISC 0x417 191 #define REG_PERFCTR0 0xc1 192 #define REG_PERFCTR1 0xc2 193 194 #define REG_PERFEVNT0 0x186 195 #define REG_PERFEVNT1 0x187 196 197 #define REG_TSC 0x10 /* timestamp counter */ 198 #define REG_APIC_BASE_MSR 0x1b 199 200 #define MSR_DEBUGCTL 0x1d9 201 202 #define DEBUGCTL_LBR 0x01 203 #define DEBUGCTL_BTF 0x02 204 205 /* Intel P6, AMD */ 206 #define MSR_LBR_FROM 0x1db 207 #define MSR_LBR_TO 0x1dc 208 #define MSR_LEX_FROM 0x1dd 209 #define MSR_LEX_TO 0x1de 210 211 /* Intel P4 (pre-Prescott, non P4 M) */ 212 #define MSR_P4_LBSTK_TOS 0x1da 213 #define MSR_P4_LBSTK_0 0x1db 214 #define MSR_P4_LBSTK_1 0x1dc 215 #define MSR_P4_LBSTK_2 0x1dd 216 #define MSR_P4_LBSTK_3 0x1de 217 218 /* Intel Pentium M */ 219 #define MSR_P6M_LBSTK_TOS 0x1c9 220 #define MSR_P6M_LBSTK_0 0x040 221 #define MSR_P6M_LBSTK_1 0x041 222 #define MSR_P6M_LBSTK_2 0x042 223 #define MSR_P6M_LBSTK_3 0x043 224 #define MSR_P6M_LBSTK_4 0x044 225 #define MSR_P6M_LBSTK_5 0x045 226 #define MSR_P6M_LBSTK_6 0x046 227 #define MSR_P6M_LBSTK_7 0x047 228 229 /* Intel P4 (Prescott) */ 230 #define MSR_PRP4_LBSTK_TOS 0x1da 231 #define MSR_PRP4_LBSTK_FROM_0 0x680 232 #define MSR_PRP4_LBSTK_FROM_1 0x681 233 #define MSR_PRP4_LBSTK_FROM_2 0x682 234 #define MSR_PRP4_LBSTK_FROM_3 0x683 235 #define MSR_PRP4_LBSTK_FROM_4 0x684 236 #define MSR_PRP4_LBSTK_FROM_5 0x685 237 #define MSR_PRP4_LBSTK_FROM_6 0x686 238 #define MSR_PRP4_LBSTK_FROM_7 0x687 239 #define MSR_PRP4_LBSTK_FROM_8 0x688 240 #define MSR_PRP4_LBSTK_FROM_9 0x689 241 #define MSR_PRP4_LBSTK_FROM_10 0x68a 242 #define MSR_PRP4_LBSTK_FROM_11 0x68b 243 #define MSR_PRP4_LBSTK_FROM_12 0x68c 244 #define MSR_PRP4_LBSTK_FROM_13 0x68d 245 #define MSR_PRP4_LBSTK_FROM_14 0x68e 246 #define MSR_PRP4_LBSTK_FROM_15 0x68f 247 #define MSR_PRP4_LBSTK_TO_0 0x6c0 248 #define MSR_PRP4_LBSTK_TO_1 0x6c1 249 #define MSR_PRP4_LBSTK_TO_2 0x6c2 250 #define MSR_PRP4_LBSTK_TO_3 0x6c3 251 #define MSR_PRP4_LBSTK_TO_4 0x6c4 252 #define MSR_PRP4_LBSTK_TO_5 0x6c5 253 #define MSR_PRP4_LBSTK_TO_6 0x6c6 254 #define MSR_PRP4_LBSTK_TO_7 0x6c7 255 #define MSR_PRP4_LBSTK_TO_8 0x6c8 256 #define MSR_PRP4_LBSTK_TO_9 0x6c9 257 #define MSR_PRP4_LBSTK_TO_10 0x6ca 258 #define MSR_PRP4_LBSTK_TO_11 0x6cb 259 #define MSR_PRP4_LBSTK_TO_12 0x6cc 260 #define MSR_PRP4_LBSTK_TO_13 0x6cd 261 #define MSR_PRP4_LBSTK_TO_14 0x6ce 262 #define MSR_PRP4_LBSTK_TO_15 0x6cf 263 264 #define MCI_CTL_VALUE 0xffffffff 265 266 #define MTRRTYPE_MASK 0xff 267 268 269 #define MTRRCAP_FIX 0x100 270 #define MTRRCAP_VCNTMASK 0xff 271 #define MTRRCAP_USWC 0x400 272 273 #define MTRRDEF_E 0x800 274 #define MTRRDEF_FE 0x400 275 276 #define MTRRPHYSMASK_V 0x800 277 278 #define MTRR_TYPE_UC 0 279 #define MTRR_TYPE_WC 1 280 #define MTRR_TYPE_WT 4 281 #define MTRR_TYPE_WP 5 282 #define MTRR_TYPE_WB 6 283 284 /* 285 * Page attribute table is setup in the following way 286 * PAT0 Write-BACK 287 * PAT1 Write-Through 288 * PAT2 Unchacheable 289 * PAT3 Uncacheable 290 * PAT4 Uncacheable 291 * PAT5 Write-Protect 292 * PAT6 Write-Combine 293 * PAT7 Uncacheable 294 */ 295 #define PAT_DEFAULT_ATTRIBUTE \ 296 ((uint64_t)MTRR_TYPE_WC << 48)|((uint64_t)MTRR_TYPE_WP << 40)| \ 297 (MTRR_TYPE_WT << 8)|(MTRR_TYPE_WB) 298 299 300 #define MTRR_SETTYPE(a, t) ((a &= (uint64_t)~0xff),\ 301 (a |= ((t) & 0xff))) 302 #define MTRR_SETVINVALID(a) ((a) &= ~MTRRPHYSMASK_V) 303 304 305 #define MTRR_SETVBASE(a, b, t) ((a) =\ 306 ((((uint64_t)(b)) & 0xffffff000)|\ 307 (((uint32_t)(t)) & 0xff))) 308 309 #define MTRR_SETVMASK(a, s, v) ((a) =\ 310 ((~(((uint64_t)(s)) - 1) & 0xffffff000)|\ 311 (((uint32_t)(v)) << 11))) 312 313 #define MTRR_GETVBASE(a) (((uint64_t)(a)) & 0xffffff000) 314 #define MTRR_GETVTYPE(a) (((uint64_t)(a)) & 0xff) 315 #define MTRR_GETVSIZE(a) ((~((uint64_t)(a)) + 1) & 0xffffff000) 316 317 318 #define MAX_MTRRVAR 8 319 320 #if !defined(_ASM) 321 typedef struct mtrrvar { 322 uint64_t mtrrphys_base; 323 uint64_t mtrrphys_mask; 324 } mtrrvar_t; 325 #endif /* _ASM */ 326 327 #define X86_LARGEPAGE 0x00000001 328 #define X86_TSC 0x00000002 329 #define X86_MSR 0x00000004 330 #define X86_MTRR 0x00000008 331 #define X86_PGE 0x00000010 332 #define X86_CMOV 0x00000040 333 #define X86_MMX 0x00000080 334 #define X86_MCA 0x00000100 335 #define X86_PAE 0x00000200 336 #define X86_CX8 0x00000400 337 #define X86_PAT 0x00000800 338 #define X86_SEP 0x00001000 339 #define X86_SSE 0x00002000 340 #define X86_SSE2 0x00004000 341 #define X86_HTT 0x00008000 342 #define X86_ASYSC 0x00010000 343 #define X86_NX 0x00020000 344 #define X86_SSE3 0x00040000 345 #define X86_CX16 0x00080000 346 #define X86_CMP 0x00100000 347 #define X86_CPUID 0x01000000 348 349 #define FMT_X86_FEATURE \ 350 "\20" \ 351 "\31cpuid" \ 352 "\25cmp\24cx16\23sse3\22nx\21asysc" \ 353 "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 354 "\10mmx\7cmov\5pge\4mtrr\3msr\2tsc\1lgpg" 355 356 /* 357 * x86_type is a legacy concept; this is supplanted 358 * for most purposes by x86_feature; modern CPUs 359 * should be X86_TYPE_OTHER 360 */ 361 #define X86_TYPE_OTHER 0 362 #define X86_TYPE_486 1 363 #define X86_TYPE_P5 2 364 #define X86_TYPE_P6 3 365 #define X86_TYPE_CYRIX_486 4 366 #define X86_TYPE_CYRIX_6x86L 5 367 #define X86_TYPE_CYRIX_6x86 6 368 #define X86_TYPE_CYRIX_GXm 7 369 #define X86_TYPE_CYRIX_6x86MX 8 370 #define X86_TYPE_CYRIX_MediaGX 9 371 #define X86_TYPE_CYRIX_MII 10 372 #define X86_TYPE_VIA_CYRIX_III 11 373 #define X86_TYPE_P4 12 374 375 /* 376 * x86_vendor allows us to select between 377 * implementation features and helps guide 378 * the interpretation of the cpuid instruction. 379 */ 380 #define X86_VENDOR_Intel 0 /* GenuineIntel */ 381 #define X86_VENDOR_IntelClone 1 /* (an Intel clone) */ 382 #define X86_VENDOR_AMD 2 /* AuthenticAMD */ 383 #define X86_VENDOR_Cyrix 3 /* CyrixInstead */ 384 #define X86_VENDOR_UMC 4 /* UMC UMC UMC */ 385 #define X86_VENDOR_NexGen 5 /* NexGenDriven */ 386 #define X86_VENDOR_Centaur 6 /* CentaurHauls */ 387 #define X86_VENDOR_Rise 7 /* RiseRiseRise */ 388 #define X86_VENDOR_SiS 8 /* SiS SiS SiS */ 389 #define X86_VENDOR_TM 9 /* GenuineTMx86 */ 390 #define X86_VENDOR_NSC 10 /* Geode by NSC */ 391 392 #define X86_VENDOR_STRLEN 13 /* vendor string max len + \0 */ 393 394 /* 395 * Some vendor/family/model/stepping ranges are commonly grouped under 396 * a single identifying banner by the vendor. The following encode 397 * that "revision" in a uint32_t with the 8 most significant bits 398 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 399 * family, and the remaining 16 typically forming a bitmask of revisions 400 * within that family with more significant bits indicating "later" revisions. 401 */ 402 403 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 404 #define _X86_CHIPREV_VENDOR_SHIFT 24 405 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 406 #define _X86_CHIPREV_FAMILY_SHIFT 16 407 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 408 409 #define _X86_CHIPREV_VENDOR(x) \ 410 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 411 #define _X86_CHIPREV_FAMILY(x) \ 412 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 413 #define _X86_CHIPREV_REV(x) \ 414 ((x) & _X86_CHIPREV_REV_MASK) 415 416 /* True if x matches in vendor and family and if x matches the given rev mask */ 417 #define X86_CHIPREV_MATCH(x, mask) \ 418 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 419 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 420 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 421 422 /* True if x matches in vendor and family and rev is at least minx */ 423 #define X86_CHIPREV_ATLEAST(x, minx) \ 424 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 425 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 426 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 427 428 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 429 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 430 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 431 432 /* Revision default */ 433 #define X86_CHIPREV_UNKNOWN 0x0 434 435 /* 436 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 437 * sufficiently different that we will distinguish them; in all other 438 * case we will identify the major revision. 439 */ 440 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 441 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 442 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 443 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 444 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 445 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 446 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 447 448 /* 449 * Various socket/package types, extended as the need to distinguish 450 * a new type arises. The top 8 byte identfies the vendor and the 451 * remaining 24 bits describe 24 socket types. 452 */ 453 454 #define _X86_SOCKET_VENDOR_SHIFT 24 455 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 456 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 457 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 458 459 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 460 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 461 462 #define X86_SOCKET_MATCH(s, mask) \ 463 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 464 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 465 466 #define X86_SOCKET_UNKNOWN 0x0 467 /* 468 * AMD socket types 469 */ 470 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 471 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 472 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 473 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 474 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 475 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 476 477 #if !defined(_ASM) 478 479 #if defined(_KERNEL) || defined(_KMEMUSER) 480 481 extern uint_t x86_feature; 482 extern uint_t x86_type; 483 extern uint_t x86_vendor; 484 485 extern ulong_t cr4_value; 486 extern uint_t pentiumpro_bug4046376; 487 extern uint_t pentiumpro_bug4064495; 488 489 extern uint_t enable486; 490 491 extern const char CyrixInstead[]; 492 493 #endif 494 495 #if defined(_KERNEL) 496 497 /* 498 * This structure is used to pass arguments and get return values back 499 * from the CPUID instruction in __cpuid_insn() routine. 500 */ 501 struct cpuid_regs { 502 uint32_t cp_eax; 503 uint32_t cp_ebx; 504 uint32_t cp_ecx; 505 uint32_t cp_edx; 506 }; 507 508 extern uint64_t rdmsr(uint_t); 509 extern void wrmsr(uint_t, const uint64_t); 510 extern uint64_t xrdmsr(uint_t); 511 extern void xwrmsr(uint_t, const uint64_t); 512 extern void invalidate_cache(void); 513 extern ulong_t getcr4(void); 514 extern void setcr4(ulong_t); 515 extern void mtrr_sync(void); 516 517 extern void cpu_fast_syscall_enable(void *); 518 extern void cpu_fast_syscall_disable(void *); 519 520 struct cpu; 521 522 extern int cpuid_checkpass(struct cpu *, int); 523 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 524 extern uint32_t __cpuid_insn(struct cpuid_regs *); 525 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 526 extern int cpuid_getidstr(struct cpu *, char *, size_t); 527 extern const char *cpuid_getvendorstr(struct cpu *); 528 extern uint_t cpuid_getvendor(struct cpu *); 529 extern uint_t cpuid_getfamily(struct cpu *); 530 extern uint_t cpuid_getmodel(struct cpu *); 531 extern uint_t cpuid_getstep(struct cpu *); 532 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 533 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 534 extern int cpuid_is_cmt(struct cpu *); 535 extern int cpuid_syscall32_insn(struct cpu *); 536 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 537 538 extern uint32_t cpuid_getchiprev(struct cpu *); 539 extern const char *cpuid_getchiprevstr(struct cpu *); 540 extern uint32_t cpuid_getsockettype(struct cpu *); 541 542 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 543 544 struct cpuid_info; 545 546 extern void setx86isalist(void); 547 extern uint_t cpuid_pass1(struct cpu *); 548 extern void cpuid_pass2(struct cpu *); 549 extern void cpuid_pass3(struct cpu *); 550 extern uint_t cpuid_pass4(struct cpu *); 551 extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 552 553 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 554 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 555 556 extern uint_t workaround_errata(struct cpu *); 557 558 #if defined(OPTERON_ERRATUM_93) 559 extern int opteron_erratum_93; 560 #endif 561 562 #if defined(OPTERON_ERRATUM_91) 563 extern int opteron_erratum_91; 564 #endif 565 566 #if defined(OPTERON_ERRATUM_100) 567 extern int opteron_erratum_100; 568 #endif 569 570 #if defined(OPTERON_ERRATUM_121) 571 extern int opteron_erratum_121; 572 #endif 573 574 #if defined(OPTERON_WORKAROUND_6323525) 575 extern int opteron_workaround_6323525; 576 extern void patch_workaround_6323525(void); 577 #endif 578 579 #endif /* _KERNEL */ 580 581 #endif 582 583 #ifdef __cplusplus 584 } 585 #endif 586 587 #endif /* _SYS_X86_ARCHEXT_H */ 588