1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MCA_X86_H 27 #define _SYS_MCA_X86_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 /* 32 * Constants for the Memory Check Architecture as implemented on generic x86 33 * CPUs. 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * Intel has defined a number of MSRs as part of the IA32 architecture. The 42 * MCG registers are part of that set, as are the first four banks (0-3) as 43 * implemented by the P4 processor. Bank MSRs were laid out slightly 44 * differently on the P6 family of processors, and thus have their own #defines 45 * following the architecture-generic ones. 46 */ 47 #define IA32_MSR_MCG_CAP 0x179 48 #define IA32_MSR_MCG_STATUS 0x17a 49 #define IA32_MSR_MCG_CTL 0x17b 50 51 #define MCG_CAP_COUNT_MASK 0x000000ffULL 52 #define MCG_CAP_CTL_P 0x00000100ULL 53 #define MCG_CAP_EXT_P 0x00000200ULL 54 #define MCG_CAP_EXT_CNT_MASK 0x00ff0000ULL 55 #define MCG_CAP_EXT_CNT_SHIFT 16 56 57 #define MCG_STATUS_RIPV 0x01 58 #define MCG_STATUS_EIPV 0x02 59 #define MCG_STATUS_MCIP 0x04 60 61 #define IA32_MSR_MC0_CTL 0x400 62 #define IA32_MSR_MC0_STATUS 0x401 63 #define IA32_MSR_MC0_ADDR 0x402 64 #define IA32_MSR_MC0_MISC 0x403 65 66 #define IA32_MSR_MC1_CTL 0x404 67 #define IA32_MSR_MC1_STATUS 0x405 68 #define IA32_MSR_MC1_ADDR 0x406 69 #define IA32_MSR_MC1_MISC 0x407 70 71 #define IA32_MSR_MC2_CTL 0x408 72 #define IA32_MSR_MC2_STATUS 0x409 73 #define IA32_MSR_MC2_ADDR 0x40a 74 #define IA32_MSR_MC2_MISC 0x40b 75 76 #define IA32_MSR_MC3_CTL 0x40c 77 #define IA32_MSR_MC3_STATUS 0x40d 78 #define IA32_MSR_MC3_ADDR 0x40e 79 #define IA32_MSR_MC3_MISC 0x40f 80 81 #define MSR_MC_STATUS_VAL 0x8000000000000000ULL 82 #define MSR_MC_STATUS_O 0x4000000000000000ULL 83 #define MSR_MC_STATUS_UC 0x2000000000000000ULL 84 #define MSR_MC_STATUS_EN 0x1000000000000000ULL 85 #define MSR_MC_STATUS_MISCV 0x0800000000000000ULL 86 #define MSR_MC_STATUS_ADDRV 0x0400000000000000ULL 87 #define MSR_MC_STATUS_PCC 0x0200000000000000ULL 88 #define MSR_MC_STATUS_OTHER_MASK 0x01ffffff00000000ULL 89 #define MSR_MC_STATUS_OTHER_SHIFT 32 90 #define MSR_MC_STATUS_MSERR_MASK 0x00000000ffff0000ULL 91 #define MSR_MC_STATUS_MSERR_SHIFT 16 92 #define MSR_MC_STATUS_MCAERR_MASK 0x000000000000ffffULL 93 94 /* 95 * P6 MCA bank MSRs. Note that the ordering is 0, 1, 2, *4*, 3. Yes, really. 96 */ 97 #define P6_MSR_MC0_CTL 0x400 98 #define P6_MSR_MC0_STATUS 0x401 99 #define P6_MSR_MC0_ADDR 0x402 100 #define P6_MSR_MC0_MISC 0x403 101 102 #define P6_MSR_MC1_CTL 0x404 103 #define P6_MSR_MC1_STATUS 0x405 104 #define P6_MSR_MC1_ADDR 0x406 105 #define P6_MSR_MC1_MISC 0x407 106 107 #define P6_MSR_MC2_CTL 0x408 108 #define P6_MSR_MC2_STATUS 0x409 109 #define P6_MSR_MC2_ADDR 0x40a 110 #define P6_MSR_MC2_MISC 0x40b 111 112 #define P6_MSR_MC4_CTL 0x40c 113 #define P6_MSR_MC4_STATUS 0x40d 114 #define P6_MSR_MC4_ADDR 0x40e 115 #define P6_MSR_MC4_MISC 0x40f 116 117 #define P6_MSR_MC3_CTL 0x410 118 #define P6_MSR_MC3_STATUS 0x411 119 #define P6_MSR_MC3_ADDR 0x412 120 #define P6_MSR_MC3_MISC 0x413 121 122 #ifdef __cplusplus 123 } 124 #endif 125 126 #endif /* _SYS_MCA_X86_H */ 127