xref: /titanic_50/usr/src/uts/intel/sys/fp.h (revision 843e19887f64dde75055cf8842fc4db2171eff45)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
27 /*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
28 /*		All Rights Reserved				*/
29 
30 #ifndef _SYS_FP_H
31 #define	_SYS_FP_H
32 
33 #pragma ident	"%Z%%M%	%I%	%E% SMI"
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /*
40  * 80287/80387 and SSE/SSE2 floating point processor definitions
41  */
42 
43 /*
44  * values that go into fp_kind
45  */
46 #define	FP_NO	0	/* no fp chip, no emulator (no fp support)	*/
47 #define	FP_SW	1	/* no fp chip, using software emulator		*/
48 #define	FP_HW	2	/* chip present bit				*/
49 #define	FP_287	2	/* 80287 chip present				*/
50 #define	FP_387	3	/* 80387 chip present				*/
51 #define	FP_487	6	/* 80487 chip present				*/
52 #define	FP_486	6	/* 80486 chip present				*/
53 #define	__FP_SSE 0x103	/* x87 plus SSE-capable CPU			*/
54 
55 /*
56  * masks for 80387 control word
57  */
58 #define	FPIM	0x00000001	/* invalid operation			*/
59 #define	FPDM	0x00000002	/* denormalized operand			*/
60 #define	FPZM	0x00000004	/* zero divide				*/
61 #define	FPOM	0x00000008	/* overflow				*/
62 #define	FPUM	0x00000010	/* underflow				*/
63 #define	FPPM	0x00000020	/* precision				*/
64 #define	FPPC	0x00000300	/* precision control			*/
65 #define	FPRC	0x00000C00	/* rounding control			*/
66 #define	FPIC	0x00001000	/* infinity control			*/
67 #define	WFPDE	0x00000080	/* data chain exception			*/
68 
69 /*
70  * (Old symbol compatibility)
71  */
72 #define	FPINV	FPIM
73 #define	FPDNO	FPDM
74 #define	FPZDIV	FPZM
75 #define	FPOVR	FPOM
76 #define	FPUNR	FPUM
77 #define	FPPRE	FPPM
78 
79 /*
80  * precision, rounding, and infinity options in control word
81  */
82 #define	FPSIG24 0x00000000	/* 24-bit significand precision (short) */
83 #define	FPSIG53 0x00000200	/* 53-bit significand precision (long)	*/
84 #define	FPSIG64 0x00000300	/* 64-bit significand precision (temp)	*/
85 #define	FPRTN	0x00000000	/* round to nearest or even		*/
86 #define	FPRD	0x00000400	/* round down				*/
87 #define	FPRU	0x00000800	/* round up				*/
88 #define	FPCHOP	0x00000C00	/* chop (truncate toward zero)		*/
89 #define	FPP	0x00000000	/* projective infinity			*/
90 #define	FPA	0x00001000	/* affine infinity			*/
91 #define	WFPB17	0x00020000	/* bit 17				*/
92 #define	WFPB24	0x00040000	/* bit 24				*/
93 
94 /*
95  * masks for 80387 status word
96  */
97 #define	FPS_IE	0x00000001	/* invalid operation			*/
98 #define	FPS_DE	0x00000002	/* denormalized operand			*/
99 #define	FPS_ZE	0x00000004	/* zero divide				*/
100 #define	FPS_OE	0x00000008	/* overflow				*/
101 #define	FPS_UE	0x00000010	/* underflow				*/
102 #define	FPS_PE	0x00000020	/* precision				*/
103 #define	FPS_SF	0x00000040	/* stack fault				*/
104 #define	FPS_ES	0x00000080	/* error summary bit			*/
105 #define	FPS_C0	0x00000100	/* C0 bit				*/
106 #define	FPS_C1	0x00000200	/* C1 bit				*/
107 #define	FPS_C2	0x00000400	/* C2 bit				*/
108 #define	FPS_TOP	0x00003800	/* top of stack pointer			*/
109 #define	FPS_C3	0x00004000	/* C3 bit				*/
110 #define	FPS_B	0x00008000	/* busy bit				*/
111 
112 /*
113  * Exception flags manually cleared during x87 exception handling.
114  */
115 #define	FPS_SW_EFLAGS	\
116 	(FPS_IE|FPS_DE|FPS_ZE|FPS_OE|FPS_UE|FPS_PE|FPS_SF|FPS_ES|FPS_B)
117 
118 /*
119  * Initial value of FPU control word as per 4th ed. ABI document
120  * - affine infinity
121  * - round to nearest or even
122  * - 64-bit double precision
123  * - all exceptions masked
124  */
125 #define	FPU_CW_INIT	0x133f
126 
127 /*
128  * masks and flags for SSE/SSE2 MXCSR
129  */
130 #define	SSE_IE 	0x00000001	/* invalid operation			*/
131 #define	SSE_DE 	0x00000002	/* denormalized operand			*/
132 #define	SSE_ZE	0x00000004	/* zero divide				*/
133 #define	SSE_OE	0x00000008	/* overflow				*/
134 #define	SSE_UE	0x00000010	/* underflow				*/
135 #define	SSE_PE	0x00000020	/* precision				*/
136 #define	SSE_DAZ	0x00000040	/* denormals are zero			*/
137 #define	SSE_IM	0x00000080	/* invalid op exception mask		*/
138 #define	SSE_DM	0x00000100	/* denormalize exception mask		*/
139 #define	SSE_ZM	0x00000200	/* zero-divide exception mask		*/
140 #define	SSE_OM	0x00000400	/* overflow exception mask		*/
141 #define	SSE_UM	0x00000800	/* underflow exception mask		*/
142 #define	SSE_PM	0x00001000	/* precision exception mask		*/
143 #define	SSE_RC	0x00006000	/* rounding control			*/
144 #define	SSE_RD	0x00002000	/* rounding control: round down		*/
145 #define	SSE_RU	0x00004000	/* rounding control: round up		*/
146 #define	SSE_FZ	0x00008000	/* flush to zero for masked underflow 	*/
147 
148 #define	SSE_MXCSR_EFLAGS	\
149 	(SSE_IE|SSE_DE|SSE_ZE|SSE_OE|SSE_UE|SSE_PE)	/* 0x3f */
150 
151 #define	SSE_MXCSR_INIT	\
152 	(SSE_IM|SSE_DM|SSE_ZM|SSE_OM|SSE_UM|SSE_PM)	/* 0x1f80 */
153 
154 #define	SSE_MXCSR_MASK_DEFAULT	\
155 	(0xffff & ~SSE_DAZ)				/* 0xffbf */
156 
157 #define	SSE_FMT_MXCSR	\
158 	"\20\20fz\17ru\16rd\15pm\14um\13om\12zm\11dm"	\
159 	"\10im\7daz\6pe\5ue\4oe\3ze\2de\1ie"
160 
161 extern int fp_kind;		/* kind of fp support			*/
162 extern int fpu_exists;		/* FPU hw exists			*/
163 
164 #ifdef _KERNEL
165 
166 extern int fpu_ignored;
167 extern int fpu_pentium_fdivbug;
168 
169 extern uint32_t sse_mxcsr_mask;
170 
171 extern void fpu_probe(void);
172 extern uint_t fpu_initial_probe(void);
173 extern int fpu_probe_pentium_fdivbug(void);
174 
175 extern void fpnsave_ctxt(void *);
176 extern void fpxsave_ctxt(void *);
177 extern void (*fpsave_ctxt)(void *);
178 
179 struct fnsave_state;
180 struct fxsave_state;
181 extern void fxsave_insn(struct fxsave_state *);
182 extern void fpsave(struct fnsave_state *);
183 extern void fprestore(struct fnsave_state *);
184 extern void fpxsave(struct fxsave_state *);
185 extern void fpxrestore(struct fxsave_state *);
186 
187 extern void fpenable(void);
188 extern void fpdisable(void);
189 extern void fpinit(void);
190 
191 extern uint32_t fperr_reset(void);
192 extern uint32_t fpxerr_reset(void);
193 
194 extern uint32_t fpgetcwsw(void);
195 extern uint32_t fpgetmxcsr(void);
196 
197 struct regs;
198 extern int fpnoextflt(struct regs *);
199 extern int fpextovrflt(struct regs *);
200 extern int fpexterrflt(struct regs *);
201 extern int fpsimderrflt(struct regs *);
202 extern void fpsetcw(uint16_t, uint32_t);
203 
204 #endif	/* _KERNEL */
205 
206 #ifdef __cplusplus
207 }
208 #endif
209 
210 #endif	/* _SYS_FP_H */
211