1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/stat.h> 30 #include <sys/sunndi.h> 31 #include <sys/pci.h> 32 #include <sys/pci_impl.h> 33 #include <sys/pci_cfgspace.h> 34 #include <sys/memlist.h> 35 #include <sys/bootconf.h> 36 #include <io/pci/mps_table.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <sys/apic.h> 42 #include <io/pciex/pcie_nvidia.h> 43 #include <sys/acpi/acpi.h> 44 #include <sys/acpica.h> 45 46 #define pci_getb (*pci_getb_func) 47 #define pci_getw (*pci_getw_func) 48 #define pci_getl (*pci_getl_func) 49 #define pci_putb (*pci_putb_func) 50 #define pci_putw (*pci_putw_func) 51 #define pci_putl (*pci_putl_func) 52 #define dcmn_err if (pci_boot_debug) cmn_err 53 54 #define CONFIG_INFO 0 55 #define CONFIG_UPDATE 1 56 #define CONFIG_NEW 2 57 #define CONFIG_FIX 3 58 #define COMPAT_BUFSIZE 512 59 60 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 61 #define LPC_IO_CONTROL_REG_1 0x40 62 #define AMD8111_ENABLENMI (uint8_t)0x80 63 #define DEVID_AMD8111_LPC 0x7468 64 65 struct pci_fixundo { 66 uint8_t bus; 67 uint8_t dev; 68 uint8_t fn; 69 void (*undofn)(uint8_t, uint8_t, uint8_t); 70 struct pci_fixundo *next; 71 }; 72 73 extern int pci_bios_nbus; 74 static uchar_t max_dev_pci = 32; /* PCI standard */ 75 int pci_boot_debug = 0; 76 extern struct memlist *find_bus_res(int, int); 77 static struct pci_fixundo *undolist = NULL; 78 79 /* 80 * Module prototypes 81 */ 82 static void enumerate_bus_devs(uchar_t bus, int config_op); 83 static void create_root_bus_dip(uchar_t bus); 84 static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 85 ushort_t, int); 86 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 87 ushort_t, ushort_t, uchar_t, uint_t, int); 88 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 89 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 90 static void add_model_prop(dev_info_t *, uint_t); 91 static void add_bus_range_prop(int); 92 static void add_bus_slot_names_prop(int); 93 static void add_ppb_ranges_prop(int); 94 static void add_bus_available_prop(int); 95 static void fix_ppb_res(uchar_t); 96 static void alloc_res_array(); 97 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 98 ushort_t deviceid); 99 100 extern int pci_slot_names_prop(int, char *, int); 101 102 /* set non-zero to force PCI peer-bus renumbering */ 103 int pci_bus_always_renumber = 0; 104 105 /* get the subordinate bus # for a root/peer bus */ 106 static int 107 pci_root_subbus(int bus, uchar_t *subbus) 108 { 109 ACPI_HANDLE hdl; 110 ACPI_BUFFER rb; 111 ACPI_RESOURCE *rp; 112 int rv; 113 114 if (pci_bus_res[bus].dip == NULL) { 115 /* non-used bus # */ 116 return (AE_ERROR); 117 } 118 if (acpica_find_pciobj(pci_bus_res[bus].dip, &hdl) != AE_OK) { 119 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 120 return (AE_ERROR); 121 } 122 123 rb.Length = ACPI_ALLOCATE_BUFFER; 124 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 125 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 126 return (AE_ERROR); 127 } 128 129 rv = AE_ERROR; 130 131 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 132 rp = ACPI_NEXT_RESOURCE(rp)) { 133 134 switch (rp->Type) { 135 case ACPI_RESOURCE_TYPE_ADDRESS16: 136 if (rp->Data.Address.ResourceType != 137 ACPI_BUS_NUMBER_RANGE) 138 continue; 139 *subbus = (uchar_t)rp->Data.Address16.Maximum; 140 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 141 break; 142 case ACPI_RESOURCE_TYPE_ADDRESS32: 143 if (rp->Data.Address.ResourceType != 144 ACPI_BUS_NUMBER_RANGE) 145 continue; 146 *subbus = (uchar_t)rp->Data.Address32.Maximum; 147 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 148 break; 149 case ACPI_RESOURCE_TYPE_ADDRESS64: 150 if (rp->Data.Address.ResourceType != 151 ACPI_BUS_NUMBER_RANGE) 152 continue; 153 *subbus = (uchar_t)rp->Data.Address64.Maximum; 154 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 155 break; 156 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 157 if (rp->Data.Address.ResourceType != 158 ACPI_BUS_NUMBER_RANGE) 159 continue; 160 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 161 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 162 break; 163 default: 164 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 165 continue; 166 } 167 168 /* found the bus-range resource */ 169 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 170 rv = AE_OK; 171 172 /* This breaks out of the resource scanning loop */ 173 break; 174 } 175 176 AcpiOsFree(rb.Pointer); 177 if (rv != AE_OK) 178 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 179 180 return (rv); 181 182 } 183 184 /* 185 * Enumerate all PCI devices 186 */ 187 void 188 pci_setup_tree() 189 { 190 uchar_t i, root_bus_addr = 0; 191 192 alloc_res_array(); 193 for (i = 0; i <= pci_bios_nbus; i++) { 194 pci_bus_res[i].par_bus = (uchar_t)-1; 195 pci_bus_res[i].root_addr = (uchar_t)-1; 196 pci_bus_res[i].sub_bus = i; 197 } 198 199 pci_bus_res[0].root_addr = root_bus_addr++; 200 create_root_bus_dip(0); 201 enumerate_bus_devs(0, CONFIG_INFO); 202 203 /* 204 * Now enumerate peer busses 205 * 206 * We loop till pci_bios_nbus. On most systems, there is 207 * one more bus at the high end, which implements the ISA 208 * compatibility bus. We don't care about that. 209 * 210 * Note: In the old (bootconf) enumeration, the peer bus 211 * address did not use the bus number, and there were 212 * too many peer busses created. The root_bus_addr is 213 * used to maintain the old peer bus address assignment. 214 * However, we stop enumerating phantom peers with no 215 * device below. 216 */ 217 for (i = 1; i <= pci_bios_nbus; i++) { 218 if (pci_bus_res[i].dip == NULL) { 219 pci_bus_res[i].root_addr = root_bus_addr++; 220 } 221 enumerate_bus_devs(i, CONFIG_INFO); 222 223 /* add slot-names property for named pci hot-plug slots */ 224 add_bus_slot_names_prop(i); 225 } 226 227 } 228 229 /* 230 * >0 = present, 0 = not present, <0 = error 231 */ 232 static int 233 pci_bbn_present(int bus) 234 { 235 ACPI_HANDLE hdl; 236 ACPI_BUFFER rb; 237 int rv; 238 239 /* no dip means no _BBN */ 240 if (pci_bus_res[bus].dip == NULL) 241 return (0); 242 243 rv = acpica_find_pciobj(pci_bus_res[bus].dip, &hdl); 244 if (rv != AE_OK) 245 return (-1); 246 247 rb.Length = ACPI_ALLOCATE_BUFFER; 248 249 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 250 251 if (rb.Length > 0) 252 AcpiOsFree(rb.Pointer); 253 254 if (rv == AE_OK) 255 return (1); 256 else if (rv == AE_NOT_FOUND) 257 return (0); 258 else 259 return (-1); 260 } 261 262 /* 263 * Return non-zero if any PCI bus in the system has an associated 264 * _BBN object, 0 otherwise. 265 */ 266 static int 267 pci_roots_have_bbn(void) 268 { 269 int i; 270 271 /* 272 * Scan the PCI busses and look for at least 1 _BBN 273 */ 274 for (i = 0; i <= pci_bios_nbus; i++) { 275 /* skip non-root (peer) PCI busses */ 276 if (pci_bus_res[i].par_bus != (uchar_t)-1) 277 continue; 278 279 if (pci_bbn_present(i) > 0) 280 return (1); 281 } 282 return (0); 283 284 } 285 286 /* 287 * return non-zero if the machine is one on which we renumber 288 * the internal pci unit-addresses 289 */ 290 static int 291 pci_bus_renumber() 292 { 293 ACPI_TABLE_HEADER *fadt; 294 295 if (pci_bus_always_renumber) 296 return (1); 297 298 /* get the FADT */ 299 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 300 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 301 return (0); 302 303 /* compare OEM Table ID to "SUNm31" */ 304 if (strncmp("SUNm31", fadt->OemId, 6)) 305 return (0); 306 else 307 return (1); 308 } 309 310 /* 311 * Initial enumeration of the physical PCI bus hierarchy can 312 * leave 'gaps' in the order of peer PCI bus unit-addresses. 313 * Systems with more than one peer PCI bus *must* have an ACPI 314 * _BBN object associated with each peer bus; use the presence 315 * of this object to remove gaps in the numbering of the peer 316 * PCI bus unit-addresses - only peer busses with an associated 317 * _BBN are counted. 318 */ 319 static void 320 pci_renumber_root_busses(void) 321 { 322 int pci_regs[] = {0, 0, 0}; 323 int i, root_addr = 0; 324 325 /* 326 * Currently, we only enable the re-numbering on specific 327 * Sun machines; this is a work-around for the more complicated 328 * issue of upgrade changing physical device paths 329 */ 330 if (!pci_bus_renumber()) 331 return; 332 333 /* 334 * If we find no _BBN objects at all, we either don't need 335 * to do anything or can't do anything anyway 336 */ 337 if (!pci_roots_have_bbn()) 338 return; 339 340 for (i = 0; i <= pci_bios_nbus; i++) { 341 /* skip non-root (peer) PCI busses */ 342 if (pci_bus_res[i].par_bus != (uchar_t)-1) 343 continue; 344 345 if (pci_bbn_present(i) < 1) { 346 pci_bus_res[i].root_addr = (uchar_t)-1; 347 continue; 348 } 349 350 ASSERT(pci_bus_res[i].dip != NULL); 351 if (pci_bus_res[i].root_addr != root_addr) { 352 /* update reg property for node */ 353 pci_bus_res[i].root_addr = root_addr; 354 pci_regs[0] = pci_bus_res[i].root_addr; 355 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 356 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 357 } 358 root_addr++; 359 } 360 } 361 362 static void 363 remove_resource_range(struct memlist **list, int *ranges, int range_count) 364 { 365 struct range { 366 uint32_t base; 367 uint32_t len; 368 }; 369 int index; 370 371 for (index = 0; index < range_count; index++) { 372 /* all done if list is or has become empty */ 373 if (*list == NULL) 374 break; 375 (void) memlist_remove(list, 376 (uint64_t)((struct range *)ranges)[index].base, 377 (uint64_t)((struct range *)ranges)[index].len); 378 } 379 } 380 381 static void 382 remove_used_resources() 383 { 384 dev_info_t *used; 385 int *narray; 386 uint_t ncount; 387 int status; 388 int bus; 389 390 used = ddi_find_devinfo("used-resources", -1, 0); 391 if (used == NULL) 392 return; 393 394 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 395 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 396 if (status == DDI_PROP_SUCCESS) { 397 for (bus = 0; bus <= pci_bios_nbus; bus++) 398 remove_resource_range(&pci_bus_res[bus].io_ports, 399 narray, ncount / 2); 400 ddi_prop_free(narray); 401 } 402 403 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 404 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 405 if (status == DDI_PROP_SUCCESS) { 406 for (bus = 0; bus <= pci_bios_nbus; bus++) 407 remove_resource_range(&pci_bus_res[bus].mem_space, 408 narray, ncount / 2); 409 ddi_prop_free(narray); 410 } 411 } 412 413 /* 414 * Assign i/o resources to unconfigured hotplug bridges after the first pass. 415 * It must be after the first pass in order to use the ports left over after 416 * accounting for i/o resources of bridges that have been configured by bios. 417 * We are expecting unconfigured bridges to be empty bridges otherwise 418 * this resource assignment needs to be done at an earlier stage. 419 */ 420 static void 421 fix_ppb_res(uchar_t secbus) 422 { 423 uchar_t bus, dev, func; 424 uint_t io_base, io_limit, io_size = 0x1000; 425 uint64_t addr = 0; 426 int *regp = NULL, rv; 427 uint_t reglen; 428 dev_info_t *dip; 429 430 dip = pci_bus_res[secbus].dip; 431 /* some entries may be empty due to discontiguous bus numbering */ 432 if (dip == NULL) 433 return; 434 435 if (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 436 "pci-hotplug-type", INBAND_HPC_NONE) == INBAND_HPC_NONE) 437 return; 438 439 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 440 "reg", ®p, ®len); 441 if (rv != DDI_PROP_SUCCESS || reglen == 0) { 442 /* panic to enforce proper calling order */ 443 cmn_err(CE_PANIC, "reg property unset for bus %d\n", secbus); 444 return; 445 } 446 447 func = (uchar_t)((regp[0] >> 8) & 0x7); 448 dev = (uchar_t)((regp[0] >> 11) & 0x1f); 449 bus = (uchar_t)((regp[0] >> 16) & 0xff); 450 ASSERT(bus == pci_bus_res[secbus].par_bus); 451 452 /* 453 * io_base >= io_limit means that the bridge was not configured 454 * This may have been set by the bios or by add_ppb_props() 455 */ 456 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 457 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 458 ASSERT(io_base != 0xff && io_limit != 0xff); 459 460 io_base = (io_base & 0xf0) << 8; 461 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 462 if (io_base < io_limit && io_base != 0) 463 return; 464 465 if (ddi_get_child(dip) != NULL) { 466 cmn_err(CE_WARN, "detected unsupported configuration: " 467 "non-empty bridge (bus 0x%x, dev 0x%x, func 0x%x) without " 468 "I/O resources assigned by bios for secondary bus 0x%x\n", 469 bus, dev, func, secbus); 470 goto IOFAIL; 471 } 472 473 if (pci_bus_res[bus].io_ports != NULL) 474 addr = memlist_find(&pci_bus_res[bus].io_ports, io_size, 475 0x1000); 476 477 ASSERT(addr <= 0xf000); 478 if (addr == 0) { 479 cmn_err(CE_WARN, "out of I/O resources on bridge: bus 0x%x, " 480 "dev 0x%x, func 0x%x, for secondary bus 0x%x\n", 481 bus, dev, func, secbus); 482 goto IOFAIL; 483 } 484 485 memlist_insert(&pci_bus_res[secbus].io_ports, addr, io_size); 486 io_base = addr; 487 io_limit = addr + io_size - 1; 488 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 489 (uint8_t)((io_base >> 8) & 0xf0)); 490 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 491 (uint8_t)((io_limit >> 8) & 0xf0)); 492 493 add_ppb_ranges_prop(secbus); 494 return; 495 496 /*NOTREACHED*/ 497 IOFAIL: 498 cmn_err(CE_WARN, "devices under bridge bus 0x%x, dev 0x%x, func 0x%x " 499 "will not be assigned I/O ports\n", bus, dev, func); 500 } 501 502 void 503 pci_reprogram(void) 504 { 505 int i, pci_reconfig = 1; 506 char *onoff; 507 508 /* 509 * Excise phantom roots if possible 510 */ 511 pci_renumber_root_busses(); 512 513 /* add bus-range property for root/peer bus nodes */ 514 for (i = 0; i <= pci_bios_nbus; i++) { 515 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 516 uchar_t subbus; 517 if (pci_root_subbus(i, &subbus) == AE_OK) 518 pci_bus_res[i].sub_bus = subbus; 519 add_bus_range_prop(i); 520 } 521 } 522 523 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 524 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 525 if (strcmp(onoff, "off") == 0) { 526 pci_reconfig = 0; 527 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 528 } 529 ddi_prop_free(onoff); 530 } 531 532 /* remove used-resources from PCI resource maps */ 533 remove_used_resources(); 534 535 for (i = 0; i <= pci_bios_nbus; i++) { 536 /* configure devices not configured by bios */ 537 if (pci_reconfig) { 538 fix_ppb_res(i); 539 enumerate_bus_devs(i, CONFIG_NEW); 540 } 541 /* All dev programmed, so we can create available prop */ 542 add_bus_available_prop(i); 543 } 544 } 545 546 /* 547 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 548 */ 549 static void 550 create_root_bus_dip(uchar_t bus) 551 { 552 int pci_regs[] = {0, 0, 0}; 553 dev_info_t *dip; 554 555 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 556 557 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 558 (pnode_t)DEVI_SID_NODEID, &dip); 559 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 560 "#address-cells", 3); 561 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 562 "#size-cells", 2); 563 pci_regs[0] = pci_bus_res[bus].root_addr; 564 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 565 "reg", (int *)pci_regs, 3); 566 567 /* 568 * If system has PCIe bus, then create different properties 569 */ 570 if (create_pcie_root_bus(bus, dip) == B_FALSE) 571 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 572 "device_type", "pci"); 573 574 (void) ndi_devi_bind_driver(dip, 0); 575 pci_bus_res[bus].dip = dip; 576 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 577 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 578 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 579 580 if (bus != 0) 581 return; 582 583 /* 584 * Special treatment of bus 0: 585 * If no resource from MPSPEC/HRT, copy pcimem from boot 586 * and make I/O space the entire range starting at 0x100. There 587 * is no difference between prefetchable memory or not. 588 */ 589 if (pci_bus_res[0].mem_space == NULL) 590 pci_bus_res[0].mem_space = 591 memlist_dup(bootops->boot_mem->pcimem); 592 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 593 if (pci_bus_res[0].io_ports == NULL) 594 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xff00); 595 } 596 597 /* 598 * For any fixed configuration (often compatability) pci devices 599 * and those with their own expansion rom, create device nodes 600 * to hold the already configured device details. 601 */ 602 void 603 enumerate_bus_devs(uchar_t bus, int config_op) 604 { 605 uchar_t dev, func, nfunc, header; 606 ushort_t venid; 607 dev_info_t *dip; 608 struct pci_devfunc { 609 struct pci_devfunc *next; 610 dev_info_t *dip; 611 uchar_t bus; 612 uchar_t dev; 613 uchar_t func; 614 } *devlist = NULL, *entry; 615 616 if (config_op == CONFIG_NEW) { 617 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 618 } else if (config_op == CONFIG_FIX) { 619 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 620 } else 621 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 622 623 for (dev = 0; dev < max_dev_pci; dev++) { 624 nfunc = 1; 625 for (func = 0; func < nfunc; func++) { 626 627 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 628 dev, func); 629 630 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 631 632 if ((venid == 0xffff) || (venid == 0)) { 633 /* no function at this address */ 634 continue; 635 } 636 637 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 638 if (header == 0xff) { 639 continue; /* illegal value */ 640 } 641 642 /* 643 * according to some mail from Microsoft posted 644 * to the pci-drivers alias, their only requirement 645 * for a multifunction device is for the 1st 646 * function to have to PCI_HEADER_MULTI bit set. 647 */ 648 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 649 nfunc = 8; 650 } 651 652 if (config_op == CONFIG_FIX) { 653 /* 654 * If we're processing PCI fixes, no dip 655 * will be returned. 656 */ 657 (void) process_devfunc(bus, dev, func, header, 658 venid, config_op); 659 660 } else if (config_op == CONFIG_INFO) { 661 /* 662 * Create the node, unconditionally, on the 663 * first pass only. It may still need 664 * resource assignment, which will be 665 * done on the second, CONFIG_NEW, pass. 666 */ 667 dip = process_devfunc(bus, dev, func, header, 668 venid, config_op); 669 /* 670 * If dip isn't null, put on a list to 671 * save for reprogramming when config_op 672 * is CONFIG_NEW. 673 */ 674 675 if (dip) { 676 entry = kmem_alloc(sizeof (*entry), 677 KM_SLEEP); 678 entry->dip = dip; 679 entry->dev = dev; 680 entry->func = func; 681 entry->next = devlist; 682 devlist = entry; 683 } 684 } 685 } 686 } 687 688 if (config_op == CONFIG_NEW) { 689 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 690 while (devlist) { 691 entry = devlist; 692 devlist = entry->next; 693 cmn_err(CE_NOTE, 694 "!reprogram pci device [%d/%d/%d] (%s)", 695 bus, entry->dev, entry->func, 696 ddi_driver_name(entry->dip)); 697 (void) add_reg_props(entry->dip, bus, entry->dev, 698 entry->func, CONFIG_UPDATE, 0); 699 kmem_free(entry, sizeof (*entry)); 700 } 701 pci_bus_res[bus].privdata = NULL; 702 } else if (config_op != CONFIG_FIX) { 703 pci_bus_res[bus].privdata = devlist; 704 } 705 } 706 707 static int 708 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 709 ushort_t subvenid, ushort_t subdevid) 710 { 711 static int prop_exist = -1; 712 static char *pciide_str; 713 char compat[32]; 714 715 if (prop_exist == -1) { 716 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 717 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 718 &pciide_str) == DDI_SUCCESS); 719 } 720 721 if (!prop_exist) 722 return (0); 723 724 /* compare property value against various forms of compatible */ 725 if (subvenid) { 726 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 727 venid, devid, subvenid, subdevid, revid); 728 if (strcmp(pciide_str, compat) == 0) 729 return (1); 730 731 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 732 venid, devid, subvenid, subdevid); 733 if (strcmp(pciide_str, compat) == 0) 734 return (1); 735 736 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 737 subvenid, subdevid); 738 if (strcmp(pciide_str, compat) == 0) 739 return (1); 740 } 741 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 742 venid, devid, revid); 743 if (strcmp(pciide_str, compat) == 0) 744 return (1); 745 746 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 747 if (strcmp(pciide_str, compat) == 0) 748 return (1); 749 750 return (0); 751 } 752 753 static int 754 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 755 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 756 { 757 struct ide_table { /* table for PCI_MASS_OTHER */ 758 ushort_t venid; 759 ushort_t devid; 760 } *entry; 761 762 /* XXX SATA devices: need a way to add dynamically */ 763 static struct ide_table ide_other[] = { 764 {0x1095, 0x3112}, 765 {0x1095, 0x3114}, 766 {0x1095, 0x3512}, 767 {0, 0} 768 }; 769 770 if (basecl != PCI_CLASS_MASS) 771 return (0); 772 773 if (subcl == PCI_MASS_IDE) { 774 return (1); 775 } 776 777 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 778 return (0); 779 } 780 781 entry = &ide_other[0]; 782 while (entry->venid) { 783 if (entry->venid == venid && entry->devid == devid) 784 return (1); 785 entry++; 786 } 787 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 788 } 789 790 static int 791 is_display(uint_t classcode) 792 { 793 static uint_t disp_classes[] = { 794 0x000100, 795 0x030000, 796 0x030001 797 }; 798 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 799 800 for (i = 0; i < nclasses; i++) { 801 if (classcode == disp_classes[i]) 802 return (1); 803 } 804 return (0); 805 } 806 807 static void 808 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 809 void (*undofn)(uint8_t, uint8_t, uint8_t)) 810 { 811 struct pci_fixundo *newundo; 812 813 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 814 815 /* 816 * Adding an item to this list means that we must turn its NMIENABLE 817 * bit back on at a later time. 818 */ 819 newundo->bus = bus; 820 newundo->dev = dev; 821 newundo->fn = fn; 822 newundo->undofn = undofn; 823 newundo->next = undolist; 824 825 /* add to the undo list in LIFO order */ 826 undolist = newundo; 827 } 828 829 void 830 add_pci_fixes(void) 831 { 832 int i; 833 834 for (i = 0; i <= pci_bios_nbus; i++) { 835 /* 836 * For each bus, apply needed fixes to the appropriate devices. 837 * This must be done before the main enumeration loop because 838 * some fixes must be applied to devices normally encountered 839 * later in the pci scan (e.g. if a fix to device 7 must be 840 * applied before scanning device 6, applying fixes in the 841 * normal enumeration loop would obviously be too late). 842 */ 843 enumerate_bus_devs(i, CONFIG_FIX); 844 } 845 } 846 847 void 848 undo_pci_fixes(void) 849 { 850 struct pci_fixundo *nextundo; 851 uint8_t bus, dev, fn; 852 853 /* 854 * All fixes in the undo list are performed unconditionally. Future 855 * fixes may require selective undo. 856 */ 857 while (undolist != NULL) { 858 859 bus = undolist->bus; 860 dev = undolist->dev; 861 fn = undolist->fn; 862 863 (*(undolist->undofn))(bus, dev, fn); 864 865 nextundo = undolist->next; 866 kmem_free(undolist, sizeof (struct pci_fixundo)); 867 undolist = nextundo; 868 } 869 } 870 871 static void 872 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 873 { 874 uint8_t val8; 875 876 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 877 /* 878 * The NMIONERR bit is turned back on to allow the SMM BIOS 879 * to handle more critical PCI errors (e.g. PERR#). 880 */ 881 val8 |= AMD8111_ENABLENMI; 882 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 883 } 884 885 static void 886 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 887 { 888 uint8_t val8; 889 890 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 891 892 if ((val8 & AMD8111_ENABLENMI) == 0) 893 return; 894 895 /* 896 * We reset NMIONERR in the LPC because master-abort on the PCI 897 * bridge side of the 8111 will cause NMI, which might cause SMI, 898 * which sometimes prevents all devices from being enumerated. 899 */ 900 val8 &= ~AMD8111_ENABLENMI; 901 902 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 903 904 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 905 } 906 907 static dev_info_t * 908 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 909 ushort_t vendorid, int config_op) 910 { 911 char nodename[32], unitaddr[5]; 912 dev_info_t *dip; 913 uchar_t basecl, subcl, progcl, intr, revid; 914 ushort_t subvenid, subdevid, status; 915 ushort_t slot_num; 916 uint_t classcode, revclass; 917 int reprogram = 0, pciide; 918 int power[2] = {1, 1}; 919 int pciex = 0; 920 ushort_t is_pci_bridge = 0; 921 922 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 923 924 switch (header & PCI_HEADER_TYPE_M) { 925 case PCI_HEADER_ZERO: 926 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 927 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 928 break; 929 case PCI_HEADER_CARDBUS: 930 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 931 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 932 break; 933 default: 934 subvenid = 0; 935 subdevid = 0; 936 break; 937 } 938 939 if (config_op == CONFIG_FIX) { 940 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 941 pci_fix_amd8111(bus, dev, func); 942 } 943 return (NULL); 944 } 945 946 /* XXX should be use generic names? derive from class? */ 947 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 948 classcode = revclass >> 8; 949 revid = revclass & 0xff; 950 951 /* figure out if this is pci-ide */ 952 basecl = classcode >> 16; 953 subcl = (classcode >> 8) & 0xff; 954 progcl = classcode & 0xff; 955 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 956 subvenid, subdevid); 957 958 if (pciide) 959 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 960 else if (is_display(classcode)) 961 (void) snprintf(nodename, sizeof (nodename), "display"); 962 else if (subvenid != 0) 963 (void) snprintf(nodename, sizeof (nodename), 964 "pci%x,%x", subvenid, subdevid); 965 else 966 (void) snprintf(nodename, sizeof (nodename), 967 "pci%x,%x", vendorid, deviceid); 968 969 /* make sure parent bus dip has been created */ 970 if (pci_bus_res[bus].dip == NULL) { 971 create_root_bus_dip(bus); 972 } 973 974 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 975 DEVI_SID_NODEID, &dip); 976 977 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 978 &is_pci_bridge) == B_TRUE) 979 pciex = 1; 980 981 /* add properties */ 982 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 983 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 984 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 985 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 986 "class-code", classcode); 987 if (func == 0) 988 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 989 else 990 (void) snprintf(unitaddr, sizeof (unitaddr), 991 "%x,%x", dev, func); 992 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 993 "unit-address", unitaddr); 994 995 /* add device_type for display nodes */ 996 if (is_display(classcode)) { 997 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 998 "device_type", "display"); 999 } 1000 /* add special stuff for header type */ 1001 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1002 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1003 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1004 1005 if (subvenid != 0) { 1006 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1007 "subsystem-id", subdevid); 1008 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1009 "subsystem-vendor-id", subvenid); 1010 } 1011 if (!pciex) 1012 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1013 "min-grant", mingrant); 1014 if (!pciex) 1015 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1016 "max-latency", maxlatency); 1017 } 1018 1019 /* interrupt, record if not 0 */ 1020 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1021 if (intr != 0) 1022 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1023 "interrupts", intr); 1024 1025 /* 1026 * Add support for 133 mhz pci eventually 1027 */ 1028 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1029 1030 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1031 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1032 if (!pciex && (status & PCI_STAT_FBBC)) 1033 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1034 "fast-back-to-back"); 1035 if (!pciex && (status & PCI_STAT_66MHZ)) 1036 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1037 "66mhz-capable"); 1038 if (status & PCI_STAT_UDF) 1039 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1040 "udf-supported"); 1041 if (pciex && slot_num) 1042 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1043 "physical-slot#", slot_num); 1044 1045 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1046 "power-consumption", power, 2); 1047 1048 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1049 add_ppb_props(dip, bus, dev, func, pciex); 1050 1051 if (config_op == CONFIG_INFO && 1052 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1053 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1054 } 1055 1056 /* check for ck8-04 based PCI ISA bridge only */ 1057 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1058 (func == 0)) 1059 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1060 1061 if (pciex && is_pci_bridge) 1062 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1063 (char *)"PCIe-PCI bridge"); 1064 else 1065 add_model_prop(dip, classcode); 1066 1067 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1068 revid, classcode, pciex); 1069 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1070 (void) ndi_devi_bind_driver(dip, 0); 1071 1072 /* special handling for pci-ide */ 1073 if (pciide) { 1074 dev_info_t *cdip; 1075 1076 /* 1077 * Create properties specified by P1275 Working Group 1078 * Proposal #414 Version 1 1079 */ 1080 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1081 "device_type", "pci-ide"); 1082 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1083 "#address-cells", 1); 1084 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1085 "#size-cells", 0); 1086 1087 /* allocate two child nodes */ 1088 ndi_devi_alloc_sleep(dip, "ide", 1089 (pnode_t)DEVI_SID_NODEID, &cdip); 1090 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1091 "reg", 0); 1092 (void) ndi_devi_bind_driver(cdip, 0); 1093 ndi_devi_alloc_sleep(dip, "ide", 1094 (pnode_t)DEVI_SID_NODEID, &cdip); 1095 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1096 "reg", 1); 1097 (void) ndi_devi_bind_driver(cdip, 0); 1098 1099 reprogram = 0; /* don't reprogram pci-ide bridge */ 1100 } 1101 1102 1103 if (reprogram) 1104 return (dip); 1105 return (NULL); 1106 } 1107 1108 /* 1109 * Set the compatible property to a value compliant with 1110 * rev 2.1 of the IEEE1275 PCI binding. 1111 * (Also used for PCI-Express devices). 1112 * 1113 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1114 * pciVVVV,DDDD.SSSS.ssss (1) 1115 * pciSSSS,ssss (2) 1116 * pciVVVV,DDDD.RR (3) 1117 * pciVVVV,DDDD (4) 1118 * pciclass,CCSSPP (5) 1119 * pciclass,CCSS (6) 1120 * 1121 * The Subsystem (SSSS) forms are not inserted if 1122 * subsystem-vendor-id is 0. 1123 * 1124 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1125 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1126 * 1127 * Set with setprop and \x00 between each 1128 * to generate the encoded string array form. 1129 */ 1130 void 1131 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1132 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1133 int pciex) 1134 { 1135 int i = 0; 1136 int size = COMPAT_BUFSIZE; 1137 char *compat[13]; 1138 char *buf, *curr; 1139 1140 curr = buf = kmem_alloc(size, KM_SLEEP); 1141 1142 if (pciex) { 1143 if (subvenid) { 1144 compat[i++] = curr; /* form 0 */ 1145 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1146 vendorid, deviceid, subvenid, subdevid, revid); 1147 size -= strlen(curr) + 1; 1148 curr += strlen(curr) + 1; 1149 1150 compat[i++] = curr; /* form 1 */ 1151 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1152 vendorid, deviceid, subvenid, subdevid); 1153 size -= strlen(curr) + 1; 1154 curr += strlen(curr) + 1; 1155 1156 } 1157 compat[i++] = curr; /* form 3 */ 1158 (void) snprintf(curr, size, "pciex%x,%x.%x", 1159 vendorid, deviceid, revid); 1160 size -= strlen(curr) + 1; 1161 curr += strlen(curr) + 1; 1162 1163 compat[i++] = curr; /* form 4 */ 1164 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1165 size -= strlen(curr) + 1; 1166 curr += strlen(curr) + 1; 1167 1168 compat[i++] = curr; /* form 5 */ 1169 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1170 size -= strlen(curr) + 1; 1171 curr += strlen(curr) + 1; 1172 1173 compat[i++] = curr; /* form 6 */ 1174 (void) snprintf(curr, size, "pciexclass,%04x", 1175 (classcode >> 8)); 1176 size -= strlen(curr) + 1; 1177 curr += strlen(curr) + 1; 1178 } 1179 1180 if (subvenid) { 1181 compat[i++] = curr; /* form 0 */ 1182 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1183 vendorid, deviceid, subvenid, subdevid, revid); 1184 size -= strlen(curr) + 1; 1185 curr += strlen(curr) + 1; 1186 1187 compat[i++] = curr; /* form 1 */ 1188 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1189 vendorid, deviceid, subvenid, subdevid); 1190 size -= strlen(curr) + 1; 1191 curr += strlen(curr) + 1; 1192 1193 compat[i++] = curr; /* form 2 */ 1194 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1195 size -= strlen(curr) + 1; 1196 curr += strlen(curr) + 1; 1197 } 1198 compat[i++] = curr; /* form 3 */ 1199 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1200 size -= strlen(curr) + 1; 1201 curr += strlen(curr) + 1; 1202 1203 compat[i++] = curr; /* form 4 */ 1204 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1205 size -= strlen(curr) + 1; 1206 curr += strlen(curr) + 1; 1207 1208 compat[i++] = curr; /* form 5 */ 1209 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1210 size -= strlen(curr) + 1; 1211 curr += strlen(curr) + 1; 1212 1213 compat[i++] = curr; /* form 6 */ 1214 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1215 size -= strlen(curr) + 1; 1216 curr += strlen(curr) + 1; 1217 1218 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1219 "compatible", compat, i); 1220 kmem_free(buf, COMPAT_BUFSIZE); 1221 } 1222 1223 /* 1224 * Adjust the reg properties for a dual channel PCI-IDE device. 1225 * 1226 * NOTE: don't do anything that changes the order of the hard-decodes 1227 * and programmed BARs. The kernel driver depends on these values 1228 * being in this order regardless of whether they're for a 'native' 1229 * mode BAR or not. 1230 */ 1231 /* 1232 * config info for pci-ide devices 1233 */ 1234 static struct { 1235 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1236 uchar_t bar_offset; /* offset for alt status register */ 1237 ushort_t addr; /* compatibility mode base address */ 1238 ushort_t length; /* number of ports for this BAR */ 1239 } pciide_bar[] = { 1240 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1241 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1242 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1243 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1244 }; 1245 1246 static int 1247 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1248 { 1249 int hard_decode = 0; 1250 1251 /* 1252 * Adjust the base and len for the BARs of the PCI-IDE 1253 * device's primary and secondary controllers. The first 1254 * two BARs are for the primary controller and the next 1255 * two BARs are for the secondary controller. The fifth 1256 * and sixth bars are never adjusted. 1257 */ 1258 if (index >= 0 && index <= 3) { 1259 *lenp = pciide_bar[index].length; 1260 1261 if (progcl & pciide_bar[index].native_mask) { 1262 *basep += pciide_bar[index].bar_offset; 1263 } else { 1264 *basep = pciide_bar[index].addr; 1265 hard_decode = 1; 1266 } 1267 } 1268 1269 /* 1270 * if either base or len is zero make certain both are zero 1271 */ 1272 if (*basep == 0 || *lenp == 0) { 1273 *basep = 0; 1274 *lenp = 0; 1275 hard_decode = 0; 1276 } 1277 1278 return (hard_decode); 1279 } 1280 1281 1282 /* 1283 * Add the "reg" and "assigned-addresses" property 1284 */ 1285 static int 1286 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1287 int config_op, int pciide) 1288 { 1289 uchar_t baseclass, subclass, progclass, header; 1290 ushort_t bar_sz; 1291 uint_t value = 0, len, devloc; 1292 uint_t base, base_hi, type; 1293 ushort_t offset, end; 1294 int max_basereg, j, reprogram = 0; 1295 uint_t phys_hi; 1296 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1297 uint16_t cmd_reg; 1298 1299 pci_regspec_t regs[16] = {{0}}; 1300 pci_regspec_t assigned[15] = {{0}}; 1301 int nreg, nasgn, enable = 0; 1302 1303 io_res = &pci_bus_res[bus].io_ports; 1304 mem_res = &pci_bus_res[bus].mem_space; 1305 if (bus == 0) /* for bus 0, there is only mem_space */ 1306 pmem_res = mem_res; 1307 else 1308 pmem_res = &pci_bus_res[bus].pmem_space; 1309 1310 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1311 regs[0].pci_phys_hi = devloc; 1312 nreg = 1; /* rest of regs[0] is all zero */ 1313 nasgn = 0; 1314 1315 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1316 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1317 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1318 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1319 1320 switch (header) { 1321 case PCI_HEADER_ZERO: 1322 max_basereg = PCI_BASE_NUM; 1323 break; 1324 case PCI_HEADER_PPB: 1325 max_basereg = PCI_BCNF_BASE_NUM; 1326 break; 1327 case PCI_HEADER_CARDBUS: 1328 max_basereg = PCI_CBUS_BASE_NUM; 1329 break; 1330 default: 1331 max_basereg = 0; 1332 break; 1333 } 1334 1335 /* 1336 * Create the register property by saving the current 1337 * value of the base register. Write 0xffffffff to the 1338 * base register. Read the value back to determine the 1339 * required size of the address space. Restore the base 1340 * register contents. 1341 * 1342 * Do not disable I/O and memory access; this isn't necessary 1343 * since no driver is yet attached to this device, and disabling 1344 * I/O and memory access has the side-effect of disabling PCI-PCI 1345 * bridge mappings, which makes the bridge transparent to secondary- 1346 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1347 * Spec V1.2). 1348 */ 1349 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1350 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1351 j++, offset += bar_sz) { 1352 int hard_decode = 0; 1353 1354 /* determine the size of the address space */ 1355 base = pci_getl(bus, dev, func, offset); 1356 pci_putl(bus, dev, func, offset, 0xffffffff); 1357 value = pci_getl(bus, dev, func, offset); 1358 pci_putl(bus, dev, func, offset, base); 1359 1360 /* construct phys hi,med.lo, size hi, lo */ 1361 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1362 /* i/o space */ 1363 bar_sz = PCI_BAR_SZ_32; 1364 value &= PCI_BASE_IO_ADDR_M; 1365 len = ((value ^ (value-1)) + 1) >> 1; 1366 1367 /* XXX Adjust first 4 IDE registers */ 1368 if (pciide) { 1369 if (subclass != PCI_MASS_IDE) 1370 progclass = (PCI_IDE_IF_NATIVE_PRI | 1371 PCI_IDE_IF_NATIVE_SEC); 1372 hard_decode = pciIdeAdjustBAR(progclass, j, 1373 &base, &len); 1374 } else if (value == 0) { 1375 /* skip base regs with size of 0 */ 1376 continue; 1377 } 1378 1379 regs[nreg].pci_size_low = 1380 assigned[nasgn].pci_size_low = len; 1381 if (!hard_decode) { 1382 regs[nreg].pci_phys_hi = 1383 (PCI_ADDR_IO | devloc) + offset; 1384 } else { 1385 regs[nreg].pci_phys_hi = 1386 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1387 offset; 1388 regs[nreg].pci_phys_low = 1389 base & PCI_BASE_IO_ADDR_M; 1390 } 1391 assigned[nasgn].pci_phys_hi = 1392 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1393 type = base & (~PCI_BASE_IO_ADDR_M); 1394 base &= PCI_BASE_IO_ADDR_M; 1395 1396 /* 1397 * first pass - gather what's there 1398 * update/second pass - adjust/allocate regions 1399 * config - allocate regions 1400 */ 1401 if (config_op == CONFIG_INFO) { /* first pass */ 1402 /* take out of the resource map of the bus */ 1403 if (*io_res && base != 0) 1404 (void) memlist_remove(io_res, 1405 (uint64_t)base, (uint64_t)len); 1406 else if (*io_res) 1407 reprogram = 1; 1408 } else if (*io_res && base == 0) { 1409 base = (uint_t)memlist_find(io_res, 1410 (uint64_t)len, (uint64_t)0x4); 1411 if (base != 0) { 1412 /* XXX need to worry about 64-bit? */ 1413 pci_putl(bus, dev, func, offset, 1414 base | type); 1415 base = pci_getl(bus, dev, func, offset); 1416 base &= PCI_BASE_IO_ADDR_M; 1417 } 1418 if (base == 0) { 1419 cmn_err(CE_WARN, "failed to program" 1420 " IO space [%d/%d/%d] BAR@0x%x" 1421 " length 0x%x", 1422 bus, dev, func, offset, len); 1423 } else 1424 enable |= PCI_COMM_IO; 1425 } 1426 assigned[nasgn].pci_phys_low = base; 1427 nreg++, nasgn++; 1428 1429 } else { 1430 /* memory space */ 1431 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1432 bar_sz = PCI_BAR_SZ_64; 1433 base_hi = pci_getl(bus, dev, func, offset + 4); 1434 phys_hi = PCI_ADDR_MEM64; 1435 } else { 1436 bar_sz = PCI_BAR_SZ_32; 1437 base_hi = 0; 1438 phys_hi = PCI_ADDR_MEM32; 1439 } 1440 1441 /* skip base regs with size of 0 */ 1442 value &= PCI_BASE_M_ADDR_M; 1443 1444 if (value == 0) { 1445 continue; 1446 } 1447 len = ((value ^ (value-1)) + 1) >> 1; 1448 regs[nreg].pci_size_low = 1449 assigned[nasgn].pci_size_low = len; 1450 1451 phys_hi |= (devloc | offset); 1452 if (base & PCI_BASE_PREF_M) { 1453 mres = pmem_res; 1454 phys_hi |= PCI_PREFETCH_B; 1455 } else { 1456 mres = mem_res; 1457 } 1458 regs[nreg].pci_phys_hi = 1459 assigned[nasgn].pci_phys_hi = phys_hi; 1460 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 1461 assigned[nasgn].pci_phys_mid = base_hi; 1462 type = base & ~PCI_BASE_M_ADDR_M; 1463 base &= PCI_BASE_M_ADDR_M; 1464 1465 if (config_op == CONFIG_INFO) { 1466 /* take out of the resource map of the bus */ 1467 if (*mres && base != 0) { 1468 (void) memlist_remove(mres, 1469 (uint64_t)base, (uint64_t)len); 1470 } else if (*mres) 1471 reprogram = 1; 1472 } else if (*mres && base == 0) { 1473 base = (uint_t)memlist_find(mres, 1474 (uint64_t)len, (uint64_t)0x1000); 1475 if (base != NULL) { 1476 pci_putl(bus, dev, func, offset, 1477 base | type); 1478 base = pci_getl(bus, dev, func, offset); 1479 base &= PCI_BASE_M_ADDR_M; 1480 } 1481 1482 if (base == 0) { 1483 cmn_err(CE_WARN, "failed to program " 1484 "mem space [%d/%d/%d] BAR@0x%x" 1485 " length 0x%x", 1486 bus, dev, func, offset, len); 1487 } else 1488 enable |= PCI_COMM_MAE; 1489 } 1490 assigned[nasgn].pci_phys_low = base; 1491 nreg++, nasgn++; 1492 } 1493 } 1494 switch (header) { 1495 case PCI_HEADER_ZERO: 1496 offset = PCI_CONF_ROM; 1497 break; 1498 case PCI_HEADER_PPB: 1499 offset = PCI_BCNF_ROM; 1500 break; 1501 default: /* including PCI_HEADER_CARDBUS */ 1502 goto done; 1503 } 1504 1505 /* 1506 * Add the expansion rom memory space 1507 * Determine the size of the ROM base reg; don't write reserved bits 1508 * ROM isn't in the PCI memory space. 1509 */ 1510 base = pci_getl(bus, dev, func, offset); 1511 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1512 value = pci_getl(bus, dev, func, offset); 1513 pci_putl(bus, dev, func, offset, base); 1514 if (value & PCI_BASE_ROM_ENABLE) 1515 value &= PCI_BASE_ROM_ADDR_M; 1516 else 1517 value = 0; 1518 1519 if (value != 0) { 1520 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1521 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1522 PCI_ADDR_MEM32 | devloc) + offset; 1523 base &= PCI_BASE_ROM_ADDR_M; 1524 assigned[nasgn].pci_phys_low = base; 1525 len = ((value ^ (value-1)) + 1) >> 1; 1526 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1527 nreg++, nasgn++; 1528 /* take it out of the memory resource */ 1529 if (*mem_res && base != 0) 1530 (void) memlist_remove(mem_res, 1531 (uint64_t)base, (uint64_t)len); 1532 } 1533 1534 /* 1535 * The following are ISA resources. There are not part 1536 * of the PCI local bus resources. So don't attempt to 1537 * do resource accounting against PCI. 1538 */ 1539 1540 /* add the three hard-decode, aliased address spaces for VGA */ 1541 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1542 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1543 1544 /* VGA hard decode 0x3b0-0x3bb */ 1545 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1546 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1547 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1548 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1549 nreg++, nasgn++; 1550 1551 /* VGA hard decode 0x3c0-0x3df */ 1552 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1553 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1554 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1555 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1556 nreg++, nasgn++; 1557 1558 /* Video memory */ 1559 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1560 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1561 regs[nreg].pci_phys_low = 1562 assigned[nasgn].pci_phys_low = 0xa0000; 1563 regs[nreg].pci_size_low = 1564 assigned[nasgn].pci_size_low = 0x20000; 1565 nreg++, nasgn++; 1566 } 1567 1568 /* add the hard-decode, aliased address spaces for 8514 */ 1569 if ((baseclass == PCI_CLASS_DISPLAY) && 1570 (subclass == PCI_DISPLAY_VGA) && 1571 (progclass & PCI_DISPLAY_IF_8514)) { 1572 1573 /* hard decode 0x2e8 */ 1574 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1575 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1576 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1577 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1578 nreg++, nasgn++; 1579 1580 /* hard decode 0x2ea-0x2ef */ 1581 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1582 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1583 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1584 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1585 nreg++, nasgn++; 1586 } 1587 1588 done: 1589 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1590 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1591 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1592 "assigned-addresses", 1593 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1594 if (config_op == CONFIG_NEW && enable) { 1595 cmn_err(CE_NOTE, 1596 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1597 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1598 cmd_reg |= (enable | PCI_COMM_ME); 1599 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1600 } 1601 return (reprogram); 1602 } 1603 1604 static void 1605 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1606 int pciex) 1607 { 1608 char *dev_type; 1609 int i; 1610 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1611 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1612 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1613 ASSERT(secbus <= subbus); 1614 1615 /* 1616 * Some BIOSes lie about max pci busses, we allow for 1617 * such mistakes here 1618 */ 1619 if (subbus > pci_bios_nbus) { 1620 pci_bios_nbus = subbus; 1621 alloc_res_array(); 1622 } 1623 1624 ASSERT(pci_bus_res[secbus].dip == NULL); 1625 pci_bus_res[secbus].dip = dip; 1626 pci_bus_res[secbus].par_bus = bus; 1627 1628 dev_type = pciex ? "pciex" : "pci"; 1629 1630 /* setup bus number hierarchy */ 1631 pci_bus_res[secbus].sub_bus = subbus; 1632 /* 1633 * Keep track of the largest subordinate bus number (this is essential 1634 * for peer busses because there is no other way of determining its 1635 * subordinate bus number). 1636 */ 1637 if (subbus > pci_bus_res[bus].sub_bus) 1638 pci_bus_res[bus].sub_bus = subbus; 1639 /* 1640 * Loop through subordinate busses, initializing their parent bus 1641 * field to this bridge's parent. The subordinate busses' parent 1642 * fields may very well be further refined later, as child bridges 1643 * are enumerated. (The value is to note that the subordinate busses 1644 * are not peer busses by changing their par_bus fields to anything 1645 * other than -1.) 1646 */ 1647 for (i = secbus + 1; i <= subbus; i++) 1648 pci_bus_res[i].par_bus = bus; 1649 1650 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1651 "device_type", dev_type); 1652 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1653 "#address-cells", 3); 1654 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1655 "#size-cells", 2); 1656 1657 /* 1658 * According to PPB spec, the base register should be programmed 1659 * with a value bigger than the limit register when there are 1660 * no resources available. This applies to io, memory, and 1661 * prefetchable memory. 1662 */ 1663 1664 /* 1665 * io range 1666 * We determine i/o windows that are left unconfigured by bios 1667 * through its i/o enable bit as Microsoft recommends OEMs to do. 1668 * If it is unset, we disable i/o and mark it for reconfiguration in 1669 * later passes by setting the base > limit 1670 */ 1671 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 1672 if (val & PCI_COMM_IO) { 1673 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1674 io_range[0] = ((val & 0xf0) << 8); 1675 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1676 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1677 } else { 1678 io_range[0] = 0x9fff; 1679 io_range[1] = 0x1000; 1680 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 1681 (uint8_t)((io_range[0] >> 8) & 0xf0)); 1682 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 1683 (uint8_t)((io_range[1] >> 8) & 0xf0)); 1684 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 1685 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 1686 } 1687 1688 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1689 memlist_insert(&pci_bus_res[secbus].io_ports, 1690 (uint64_t)io_range[0], 1691 (uint64_t)(io_range[1] - io_range[0] + 1)); 1692 if (pci_bus_res[bus].io_ports != NULL) { 1693 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1694 (uint64_t)io_range[0], 1695 (uint64_t)(io_range[1] - io_range[0] + 1)); 1696 } 1697 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1698 secbus, io_range[0], io_range[1]); 1699 /* if 32-bit supported, make sure upper bits are not set */ 1700 if ((val & 0xf) == 1 && 1701 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1702 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1703 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1704 } 1705 } 1706 1707 /* mem range */ 1708 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1709 mem_range[0] = ((val & 0xFFF0) << 16); 1710 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1711 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1712 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1713 memlist_insert(&pci_bus_res[secbus].mem_space, 1714 (uint64_t)mem_range[0], 1715 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1716 /* remove from parent resouce list */ 1717 if (pci_bus_res[bus].mem_space != NULL) { 1718 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1719 (uint64_t)mem_range[0], 1720 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1721 } 1722 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1723 secbus, mem_range[0], mem_range[1]); 1724 } 1725 1726 /* prefetchable memory range */ 1727 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1728 pmem_range[0] = ((val & 0xFFF0) << 16); 1729 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1730 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1731 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1732 memlist_insert(&pci_bus_res[secbus].pmem_space, 1733 (uint64_t)pmem_range[0], 1734 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1735 if (pci_bus_res[bus].pmem_space != NULL) { 1736 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1737 (uint64_t)pmem_range[0], 1738 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1739 } 1740 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1741 secbus, pmem_range[0], pmem_range[1]); 1742 /* if 64-bit supported, make sure upper bits are not set */ 1743 if ((val & 0xf) == 1 && 1744 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1745 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1746 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1747 } 1748 } 1749 1750 add_bus_range_prop(secbus); 1751 add_ppb_ranges_prop(secbus); 1752 } 1753 1754 extern const struct pci_class_strings_s class_pci[]; 1755 extern int class_pci_items; 1756 1757 static void 1758 add_model_prop(dev_info_t *dip, uint_t classcode) 1759 { 1760 const char *desc; 1761 int i; 1762 uchar_t baseclass = classcode >> 16; 1763 uchar_t subclass = (classcode >> 8) & 0xff; 1764 uchar_t progclass = classcode & 0xff; 1765 1766 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1767 desc = "IDE controller"; 1768 } else { 1769 for (desc = 0, i = 0; i < class_pci_items; i++) { 1770 if ((baseclass == class_pci[i].base_class) && 1771 (subclass == class_pci[i].sub_class) && 1772 (progclass == class_pci[i].prog_class)) { 1773 desc = class_pci[i].actual_desc; 1774 break; 1775 } 1776 } 1777 if (i == class_pci_items) 1778 desc = "Unknown class of pci/pnpbios device"; 1779 } 1780 1781 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1782 (char *)desc); 1783 } 1784 1785 static void 1786 add_bus_range_prop(int bus) 1787 { 1788 int bus_range[2]; 1789 1790 if (pci_bus_res[bus].dip == NULL) 1791 return; 1792 bus_range[0] = bus; 1793 bus_range[1] = pci_bus_res[bus].sub_bus; 1794 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1795 "bus-range", (int *)bus_range, 2); 1796 } 1797 1798 /* 1799 * Add slot-names property for any named pci hot-plug slots 1800 */ 1801 static void 1802 add_bus_slot_names_prop(int bus) 1803 { 1804 char slotprop[256]; 1805 int len; 1806 1807 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1808 if (len > 0) { 1809 /* 1810 * Only create a peer bus node if this bus may be a peer bus. 1811 * It may be a peer bus if the dip is NULL and if par_bus is 1812 * -1 (par_bus is -1 if this bus was not found to be 1813 * subordinate to any PCI-PCI bridge). 1814 * If it's not a peer bus, then the ACPI BBN-handling code 1815 * will remove it later. 1816 */ 1817 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 1818 pci_bus_res[bus].dip == NULL) { 1819 1820 create_root_bus_dip(bus); 1821 } 1822 if (pci_bus_res[bus].dip != NULL) { 1823 ASSERT((len % sizeof (int)) == 0); 1824 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1825 pci_bus_res[bus].dip, "slot-names", 1826 (int *)slotprop, len / sizeof (int)); 1827 } else { 1828 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 1829 "IRQ routing table; Not adding slot-names " 1830 "property for incorrect bus %d", bus); 1831 } 1832 } 1833 } 1834 1835 static int 1836 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 1837 { 1838 if (entry == NULL) 1839 return (0); 1840 1841 /* assume 32-bit addresses */ 1842 rp->child_high = rp->parent_high = type; 1843 rp->child_mid = rp->parent_mid = 0; 1844 rp->child_low = rp->parent_low = (uint32_t)entry->address; 1845 rp->size_high = 0; 1846 rp->size_low = (uint32_t)entry->size; 1847 return (1); 1848 } 1849 1850 static void 1851 add_ppb_ranges_prop(int bus) 1852 { 1853 int i = 0; 1854 ppb_ranges_t *rp; 1855 1856 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1857 1858 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1859 PCI_ADDR_IO | PCI_REG_REL_M); 1860 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1861 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1862 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1863 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1864 1865 if (i != 0) 1866 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1867 pci_bus_res[bus].dip, "ranges", (int *)rp, 1868 i * sizeof (ppb_ranges_t) / sizeof (int)); 1869 kmem_free(rp, 3 * sizeof (*rp)); 1870 } 1871 1872 static int 1873 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1874 { 1875 int i = 0; 1876 1877 while (list) { 1878 /* assume 32-bit addresses */ 1879 sp->pci_phys_hi = type; 1880 sp->pci_phys_mid = 0; 1881 sp->pci_phys_low = (uint32_t)list->address; 1882 sp->pci_size_hi = 0; 1883 sp->pci_size_low = (uint32_t)list->size; 1884 1885 list = list->next; 1886 sp++, i++; 1887 } 1888 return (i); 1889 } 1890 1891 static void 1892 add_bus_available_prop(int bus) 1893 { 1894 int i, count; 1895 struct pci_phys_spec *sp; 1896 1897 count = memlist_count(pci_bus_res[bus].io_ports) + 1898 memlist_count(pci_bus_res[bus].mem_space) + 1899 memlist_count(pci_bus_res[bus].pmem_space); 1900 1901 if (count == 0) /* nothing available */ 1902 return; 1903 1904 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1905 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1906 PCI_ADDR_IO | PCI_REG_REL_M); 1907 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1908 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1909 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1910 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1911 ASSERT(i == count); 1912 1913 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1914 "available", (int *)sp, 1915 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1916 kmem_free(sp, count * sizeof (*sp)); 1917 } 1918 1919 static void 1920 alloc_res_array(void) 1921 { 1922 static int array_max = 0; 1923 int old_max; 1924 void *old_res; 1925 1926 if (array_max > pci_bios_nbus + 1) 1927 return; /* array is big enough */ 1928 1929 old_max = array_max; 1930 old_res = pci_bus_res; 1931 1932 if (array_max == 0) 1933 array_max = 16; /* start with a reasonable number */ 1934 1935 while (array_max < pci_bios_nbus + 1) 1936 array_max <<= 1; 1937 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1938 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1939 1940 if (old_res) { /* copy content and free old array */ 1941 bcopy(old_res, pci_bus_res, 1942 old_max * sizeof (struct pci_bus_resource)); 1943 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1944 } 1945 } 1946 1947 static void 1948 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 1949 ushort_t deviceid) 1950 { 1951 static dev_info_t *ioapicsnode = NULL; 1952 static int numioapics = 0; 1953 dev_info_t *ioapic_node; 1954 uint64_t physaddr; 1955 uint32_t lobase, hibase = 0; 1956 1957 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 1958 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 1959 1960 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 1961 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 1962 return; 1963 1964 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 1965 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 1966 1967 lobase &= PCI_BASE_M_ADDR_M; 1968 1969 physaddr = (((uint64_t)hibase) << 32) | lobase; 1970 1971 /* 1972 * Create a nexus node for all IOAPICs under the root node. 1973 */ 1974 if (ioapicsnode == NULL) { 1975 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 1976 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 1977 return; 1978 } 1979 (void) ndi_devi_online(ioapicsnode, 0); 1980 } 1981 1982 /* 1983 * Create a child node for this IOAPIC 1984 */ 1985 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 1986 DEVI_SID_NODEID, numioapics++); 1987 if (ioapic_node == NULL) { 1988 return; 1989 } 1990 1991 /* Vendor and Device ID */ 1992 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1993 IOAPICS_PROP_VENID, vendorid); 1994 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1995 IOAPICS_PROP_DEVID, deviceid); 1996 1997 /* device_type */ 1998 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 1999 "device_type", IOAPICS_DEV_TYPE); 2000 2001 /* reg */ 2002 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2003 "reg", physaddr); 2004 } 2005