xref: /titanic_50/usr/src/uts/intel/io/pci/pci_boot.c (revision 73a9f52fa0e4b5d00dc5f3a6314e6837e47f88cf)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include <sys/types.h>
27 #include <sys/stat.h>
28 #include <sys/sunndi.h>
29 #include <sys/pci.h>
30 #include <sys/pci_impl.h>
31 #include <sys/pci_cfgspace.h>
32 #include <sys/memlist.h>
33 #include <sys/bootconf.h>
34 #include <io/pci/mps_table.h>
35 #include <sys/pci_cfgspace.h>
36 #include <sys/pci_cfgspace_impl.h>
37 #include <sys/psw.h>
38 #include "../../../../common/pci/pci_strings.h"
39 #include <sys/apic.h>
40 #include <io/pciex/pcie_nvidia.h>
41 #include <io/hotplug/pciehpc/pciehpc_acpi.h>
42 #include <sys/acpi/acpi.h>
43 #include <sys/acpica.h>
44 #include <sys/intel_iommu.h>
45 
46 #define	pci_getb	(*pci_getb_func)
47 #define	pci_getw	(*pci_getw_func)
48 #define	pci_getl	(*pci_getl_func)
49 #define	pci_putb	(*pci_putb_func)
50 #define	pci_putw	(*pci_putw_func)
51 #define	pci_putl	(*pci_putl_func)
52 #define	dcmn_err	if (pci_boot_debug) cmn_err
53 
54 #define	CONFIG_INFO	0
55 #define	CONFIG_UPDATE	1
56 #define	CONFIG_NEW	2
57 #define	CONFIG_FIX	3
58 #define	COMPAT_BUFSIZE	512
59 
60 #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
61 #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
62 
63 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
64 #define	LPC_IO_CONTROL_REG_1	0x40
65 #define	AMD8111_ENABLENMI	(uint8_t)0x80
66 #define	DEVID_AMD8111_LPC	0x7468
67 
68 struct pci_fixundo {
69 	uint8_t			bus;
70 	uint8_t			dev;
71 	uint8_t			fn;
72 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
73 	struct pci_fixundo	*next;
74 };
75 
76 struct pci_devfunc {
77 	struct pci_devfunc *next;
78 	dev_info_t *dip;
79 	uchar_t dev;
80 	uchar_t func;
81 	boolean_t reprogram;	/* this device needs to be reprogrammed */
82 };
83 
84 extern int pci_bios_nbus;
85 static uchar_t max_dev_pci = 32;	/* PCI standard */
86 int pci_boot_debug = 0;
87 extern struct memlist *find_bus_res(int, int);
88 static struct pci_fixundo *undolist = NULL;
89 static int num_root_bus = 0;	/* count of root buses */
90 
91 /*
92  * Module prototypes
93  */
94 static void enumerate_bus_devs(uchar_t bus, int config_op);
95 static void create_root_bus_dip(uchar_t bus);
96 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
97     ushort_t, int);
98 static void add_compatible(dev_info_t *, ushort_t, ushort_t,
99     ushort_t, ushort_t, uchar_t, uint_t, int);
100 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
101 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int);
102 static void add_model_prop(dev_info_t *, uint_t);
103 static void add_bus_range_prop(int);
104 static void add_bus_slot_names_prop(int);
105 static void add_ppb_ranges_prop(int);
106 static void add_bus_available_prop(int);
107 static void fix_ppb_res(uchar_t, boolean_t);
108 static void alloc_res_array();
109 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
110     ushort_t deviceid);
111 static void pciex_slot_names_prop(dev_info_t *, ushort_t);
112 
113 extern int pci_slot_names_prop(int, char *, int);
114 
115 /* set non-zero to force PCI peer-bus renumbering */
116 int pci_bus_always_renumber = 0;
117 
118 /* get the subordinate bus # for a root/peer bus */
119 static int
120 pci_root_subbus(int bus, uchar_t *subbus)
121 {
122 	ACPI_HANDLE	hdl;
123 	ACPI_BUFFER	rb;
124 	ACPI_RESOURCE	*rp;
125 	int	rv;
126 
127 	if (pci_bus_res[bus].dip == NULL) {
128 		/* non-used bus # */
129 		return (AE_ERROR);
130 	}
131 	if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) {
132 		cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus);
133 		return (AE_ERROR);
134 	}
135 
136 	rb.Length = ACPI_ALLOCATE_BUFFER;
137 	if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) {
138 		cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus);
139 		return (AE_ERROR);
140 	}
141 
142 	rv = AE_ERROR;
143 
144 	for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG;
145 	    rp = ACPI_NEXT_RESOURCE(rp)) {
146 
147 		switch (rp->Type) {
148 		case ACPI_RESOURCE_TYPE_ADDRESS16:
149 			if (rp->Data.Address.ResourceType !=
150 			    ACPI_BUS_NUMBER_RANGE)
151 				continue;
152 			*subbus = (uchar_t)rp->Data.Address16.Maximum;
153 			dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus);
154 			break;
155 		case ACPI_RESOURCE_TYPE_ADDRESS32:
156 			if (rp->Data.Address.ResourceType !=
157 			    ACPI_BUS_NUMBER_RANGE)
158 				continue;
159 			*subbus = (uchar_t)rp->Data.Address32.Maximum;
160 			dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus);
161 			break;
162 		case ACPI_RESOURCE_TYPE_ADDRESS64:
163 			if (rp->Data.Address.ResourceType !=
164 			    ACPI_BUS_NUMBER_RANGE)
165 				continue;
166 			*subbus = (uchar_t)rp->Data.Address64.Maximum;
167 			dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus);
168 			break;
169 		case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64:
170 			if (rp->Data.Address.ResourceType !=
171 			    ACPI_BUS_NUMBER_RANGE)
172 				continue;
173 			*subbus = (uchar_t)rp->Data.ExtAddress64.Maximum;
174 			dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus);
175 			break;
176 		default:
177 			dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type);
178 			continue;
179 		}
180 
181 		/* found the bus-range resource */
182 		dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus);
183 		rv = AE_OK;
184 
185 		/* This breaks out of the resource scanning loop */
186 		break;
187 	}
188 
189 	AcpiOsFree(rb.Pointer);
190 	if (rv != AE_OK)
191 		cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus);
192 
193 	return (rv);
194 
195 }
196 
197 /*
198  * Enumerate all PCI devices
199  */
200 void
201 pci_setup_tree()
202 {
203 	uchar_t i, root_bus_addr = 0;
204 
205 	alloc_res_array();
206 	for (i = 0; i <= pci_bios_nbus; i++) {
207 		pci_bus_res[i].par_bus = (uchar_t)-1;
208 		pci_bus_res[i].root_addr = (uchar_t)-1;
209 		pci_bus_res[i].sub_bus = i;
210 	}
211 
212 	pci_bus_res[0].root_addr = root_bus_addr++;
213 	create_root_bus_dip(0);
214 	enumerate_bus_devs(0, CONFIG_INFO);
215 
216 	/*
217 	 * Now enumerate peer busses
218 	 *
219 	 * We loop till pci_bios_nbus. On most systems, there is
220 	 * one more bus at the high end, which implements the ISA
221 	 * compatibility bus. We don't care about that.
222 	 *
223 	 * Note: In the old (bootconf) enumeration, the peer bus
224 	 *	address did not use the bus number, and there were
225 	 *	too many peer busses created. The root_bus_addr is
226 	 *	used to maintain the old peer bus address assignment.
227 	 *	However, we stop enumerating phantom peers with no
228 	 *	device below.
229 	 */
230 	for (i = 1; i <= pci_bios_nbus; i++) {
231 		if (pci_bus_res[i].dip == NULL) {
232 			pci_bus_res[i].root_addr = root_bus_addr++;
233 		}
234 		enumerate_bus_devs(i, CONFIG_INFO);
235 
236 		/* add slot-names property for named pci hot-plug slots */
237 		add_bus_slot_names_prop(i);
238 	}
239 
240 }
241 
242 /*
243  * >0 = present, 0 = not present, <0 = error
244  */
245 static int
246 pci_bbn_present(int bus)
247 {
248 	ACPI_HANDLE	hdl;
249 	int	rv;
250 
251 	/* no dip means no _BBN */
252 	if (pci_bus_res[bus].dip == NULL)
253 		return (0);
254 
255 	rv = -1;	/* default return value in case of error below */
256 	if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) {
257 		switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) {
258 		case AE_OK:
259 			rv = 1;
260 			break;
261 		case AE_NOT_FOUND:
262 			rv = 0;
263 			break;
264 		default:
265 			break;
266 		}
267 	}
268 
269 	return (rv);
270 }
271 
272 /*
273  * Return non-zero if any PCI bus in the system has an associated
274  * _BBN object, 0 otherwise.
275  */
276 static int
277 pci_roots_have_bbn(void)
278 {
279 	int	i;
280 
281 	/*
282 	 * Scan the PCI busses and look for at least 1 _BBN
283 	 */
284 	for (i = 0; i <= pci_bios_nbus; i++) {
285 		/* skip non-root (peer) PCI busses */
286 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
287 			continue;
288 
289 		if (pci_bbn_present(i) > 0)
290 			return (1);
291 	}
292 	return (0);
293 
294 }
295 
296 /*
297  * return non-zero if the machine is one on which we renumber
298  * the internal pci unit-addresses
299  */
300 static int
301 pci_bus_renumber()
302 {
303 	ACPI_TABLE_HEADER *fadt;
304 
305 	if (pci_bus_always_renumber)
306 		return (1);
307 
308 	/* get the FADT */
309 	if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) !=
310 	    AE_OK)
311 		return (0);
312 
313 	/* compare OEM Table ID to "SUNm31" */
314 	if (strncmp("SUNm31", fadt->OemId, 6))
315 		return (0);
316 	else
317 		return (1);
318 }
319 
320 /*
321  * Initial enumeration of the physical PCI bus hierarchy can
322  * leave 'gaps' in the order of peer PCI bus unit-addresses.
323  * Systems with more than one peer PCI bus *must* have an ACPI
324  * _BBN object associated with each peer bus; use the presence
325  * of this object to remove gaps in the numbering of the peer
326  * PCI bus unit-addresses - only peer busses with an associated
327  * _BBN are counted.
328  */
329 static void
330 pci_renumber_root_busses(void)
331 {
332 	int pci_regs[] = {0, 0, 0};
333 	int	i, root_addr = 0;
334 
335 	/*
336 	 * Currently, we only enable the re-numbering on specific
337 	 * Sun machines; this is a work-around for the more complicated
338 	 * issue of upgrade changing physical device paths
339 	 */
340 	if (!pci_bus_renumber())
341 		return;
342 
343 	/*
344 	 * If we find no _BBN objects at all, we either don't need
345 	 * to do anything or can't do anything anyway
346 	 */
347 	if (!pci_roots_have_bbn())
348 		return;
349 
350 	for (i = 0; i <= pci_bios_nbus; i++) {
351 		/* skip non-root (peer) PCI busses */
352 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
353 			continue;
354 
355 		if (pci_bbn_present(i) < 1) {
356 			pci_bus_res[i].root_addr = (uchar_t)-1;
357 			continue;
358 		}
359 
360 		ASSERT(pci_bus_res[i].dip != NULL);
361 		if (pci_bus_res[i].root_addr != root_addr) {
362 			/* update reg property for node */
363 			pci_bus_res[i].root_addr = root_addr;
364 			pci_regs[0] = pci_bus_res[i].root_addr;
365 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
366 			    pci_bus_res[i].dip, "reg", (int *)pci_regs, 3);
367 		}
368 		root_addr++;
369 	}
370 }
371 
372 static void
373 remove_resource_range(struct memlist **list, int *ranges, int range_count)
374 {
375 	struct range {
376 		uint32_t base;
377 		uint32_t len;
378 	};
379 	int index;
380 
381 	for (index = 0; index < range_count; index++) {
382 		/* all done if list is or has become empty */
383 		if (*list == NULL)
384 			break;
385 		(void) memlist_remove(list,
386 		    (uint64_t)((struct range *)ranges)[index].base,
387 		    (uint64_t)((struct range *)ranges)[index].len);
388 	}
389 }
390 
391 static void
392 remove_used_resources()
393 {
394 	dev_info_t *used;
395 	int	*narray;
396 	uint_t	ncount;
397 	int	status;
398 	int	bus;
399 
400 	used = ddi_find_devinfo("used-resources", -1, 0);
401 	if (used == NULL)
402 		return;
403 
404 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
405 	    DDI_PROP_DONTPASS, "io-space", &narray, &ncount);
406 	if (status == DDI_PROP_SUCCESS) {
407 		for (bus = 0; bus <= pci_bios_nbus; bus++)
408 			remove_resource_range(&pci_bus_res[bus].io_ports,
409 			    narray, ncount / 2);
410 		ddi_prop_free(narray);
411 	}
412 
413 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
414 	    DDI_PROP_DONTPASS, "device-memory", &narray, &ncount);
415 	if (status == DDI_PROP_SUCCESS) {
416 		for (bus = 0; bus <= pci_bios_nbus; bus++)
417 			remove_resource_range(&pci_bus_res[bus].mem_space,
418 			    narray, ncount / 2);
419 		ddi_prop_free(narray);
420 	}
421 }
422 
423 /*
424  * Remove the resources which are already used by devices under a subtractive
425  * bridge from the bus's resources lists, because they're not available, and
426  * shouldn't be allocated to other buses.  This is necessary because tracking
427  * resources for subtractive bridges is not complete.  (Subtractive bridges only
428  * track some of their claimed resources, not "the rest of the address space" as
429  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
430  * need a fully-capable global resource allocator).
431  */
432 static void
433 remove_subtractive_res()
434 {
435 	int i, j;
436 	struct memlist *list;
437 
438 	for (i = 0; i <= pci_bios_nbus; i++) {
439 		if (pci_bus_res[i].subtractive) {
440 			/* remove used io ports */
441 			list = pci_bus_res[i].io_ports_used;
442 			while (list) {
443 				for (j = 0; j <= pci_bios_nbus; j++) {
444 					if (pci_bus_res[j].io_ports)
445 						(void) memlist_remove(
446 						    &pci_bus_res[j].io_ports,
447 						    list->address, list->size);
448 				}
449 				list = list->next;
450 			}
451 			/* remove used mem resource */
452 			list = pci_bus_res[i].mem_space_used;
453 			while (list) {
454 				for (j = 0; j <= pci_bios_nbus; j++) {
455 					if (pci_bus_res[j].mem_space)
456 						(void) memlist_remove(
457 						    &pci_bus_res[j].mem_space,
458 						    list->address, list->size);
459 				}
460 				list = list->next;
461 			}
462 			/* remove used prefetchable mem resource */
463 			list = pci_bus_res[i].pmem_space_used;
464 			while (list) {
465 				for (j = 0; j <= pci_bios_nbus; j++) {
466 					if (pci_bus_res[j].pmem_space)
467 						(void) memlist_remove(
468 						    &pci_bus_res[j].pmem_space,
469 						    list->address, list->size);
470 				}
471 				list = list->next;
472 			}
473 		}
474 	}
475 }
476 
477 /* Set up this bus's "bus_space" resource list */
478 static void
479 setup_bus_res(int bus)
480 {
481 	uchar_t par_bus;
482 	uchar_t sub_bus;
483 
484 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
485 		return;
486 
487 	sub_bus = pci_bus_res[bus].sub_bus;
488 	ASSERT(sub_bus >= bus);
489 	ASSERT(pci_bus_res[bus].bus_space == NULL);
490 	if (sub_bus > bus) {
491 		/*
492 		 * Keep the remaining available bus range in bus_space.
493 		 * ('bus' is already allocated)
494 		 */
495 		memlist_insert(&pci_bus_res[bus].bus_space, bus + 1,
496 		    sub_bus - bus);
497 	}
498 
499 	/*
500 	 * Remove resources from parent bus node if this is not a
501 	 * root bus.
502 	 */
503 	par_bus = pci_bus_res[bus].par_bus;
504 	if (par_bus != (uchar_t)-1) {
505 		ASSERT(pci_bus_res[par_bus].bus_space != NULL);
506 		(void) memlist_remove(&pci_bus_res[par_bus].bus_space,
507 		    bus, sub_bus - bus + 1);
508 	}
509 }
510 
511 static uint64_t
512 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
513 {
514 	uint64_t addr = 0;
515 	uchar_t res_bus;
516 
517 	/*
518 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
519 	 * the initial resources set on each root bus might not be correctly
520 	 * accounted for.  (We need to read resources from ACPI as well as
521 	 * the MP tables and hotplug tables.)
522 	 */
523 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
524 	    (num_root_bus > 1))
525 		return (0);
526 
527 	res_bus = parbus;
528 	while (pci_bus_res[res_bus].subtractive) {
529 		if (pci_bus_res[res_bus].io_ports)
530 			break;
531 		res_bus = pci_bus_res[res_bus].par_bus;
532 		if (res_bus == (uchar_t)-1)
533 			break; /* root bus already */
534 	}
535 
536 	if (pci_bus_res[res_bus].io_ports) {
537 		addr = memlist_find(&pci_bus_res[res_bus].io_ports,
538 		    size, align);
539 		if (addr) {
540 			memlist_insert(&pci_bus_res[res_bus].io_ports_used,
541 			    addr, size);
542 			/* free the old resource */
543 			memlist_free_all(&pci_bus_res[bus].io_ports);
544 			/* add the new resource */
545 			memlist_insert(&pci_bus_res[bus].io_ports, addr, size);
546 		}
547 	}
548 
549 	return (addr);
550 }
551 
552 static uint64_t
553 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
554 {
555 	uint64_t addr = 0;
556 	uchar_t res_bus;
557 
558 	/*
559 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
560 	 * the initial resources set on each root bus might not be correctly
561 	 * accounted for.  (We need to read resources from ACPI as well as
562 	 * the MP tables and hotplug tables.)
563 	 */
564 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
565 	    (num_root_bus > 1))
566 		return (0);
567 
568 	res_bus = parbus;
569 	while (pci_bus_res[res_bus].subtractive) {
570 		if (pci_bus_res[res_bus].mem_space)
571 			break;
572 		res_bus = pci_bus_res[res_bus].par_bus;
573 		if (res_bus == (uchar_t)-1)
574 			break; /* root bus already */
575 	}
576 
577 	if (pci_bus_res[res_bus].mem_space) {
578 		addr = memlist_find(&pci_bus_res[res_bus].mem_space,
579 		    size, align);
580 		if (addr) {
581 			memlist_insert(&pci_bus_res[res_bus].mem_space_used,
582 			    addr, size);
583 			/* free the old resource */
584 			memlist_free_all(&pci_bus_res[bus].mem_space);
585 			/* add the new resource */
586 			memlist_insert(&pci_bus_res[bus].mem_space, addr, size);
587 		}
588 	}
589 
590 	return (addr);
591 }
592 
593 /*
594  * Assign valid resources to unconfigured pci(e) bridges. We are trying
595  * to reprogram the bridge when its
596  * 		i)   SECBUS == SUBBUS	||
597  * 		ii)  IOBASE > IOLIM	||
598  * 		iii) MEMBASE > MEMLIM
599  * This must be done after one full pass through the PCI tree to collect
600  * all BIOS-configured resources, so that we know what resources are
601  * free and available to assign to the unconfigured PPBs.
602  */
603 static void
604 fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
605 {
606 	uchar_t bus, dev, func;
607 	uchar_t parbus, subbus;
608 	uint_t io_base, io_limit, mem_base, mem_limit;
609 	uint_t io_size, mem_size;
610 	uint64_t addr = 0;
611 	int *regp = NULL;
612 	uint_t reglen;
613 	int rv, cap_ptr, physhi;
614 	dev_info_t *dip;
615 	uint16_t cmd_reg;
616 	struct memlist *list;
617 
618 	/* skip root (peer) PCI busses */
619 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
620 		return;
621 
622 	/* skip subtractive PPB when prog_sub is not TRUE */
623 	if (pci_bus_res[secbus].subtractive && !prog_sub)
624 		return;
625 
626 	/* some entries may be empty due to discontiguous bus numbering */
627 	dip = pci_bus_res[secbus].dip;
628 	if (dip == NULL)
629 		return;
630 
631 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
632 	    "reg", &regp, &reglen);
633 	ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0);
634 	physhi = regp[0];
635 	ddi_prop_free(regp);
636 
637 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
638 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
639 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
640 
641 	/*
642 	 * If pcie bridge, check to see if link is enabled
643 	 */
644 	cap_ptr = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
645 	    "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL);
646 	if (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
647 		cmd_reg = pci_getw(bus, dev, func,
648 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
649 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
650 			dcmn_err(CE_NOTE,
651 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
652 			    bus, dev, func);
653 			return;
654 		}
655 	}
656 
657 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
658 	parbus = pci_bus_res[secbus].par_bus;
659 	ASSERT(parbus == bus);
660 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
661 
662 	/*
663 	 * If we have a Cardbus bridge, but no bus space
664 	 */
665 	if (pci_bus_res[secbus].num_cbb != 0 &&
666 	    pci_bus_res[secbus].bus_space == NULL) {
667 		uchar_t range;
668 
669 		/* normally there are 2 buses under a cardbus bridge */
670 		range = pci_bus_res[secbus].num_cbb * 2;
671 
672 		/*
673 		 * Try to find and allocate a bus-range starting at subbus+1
674 		 * from the parent of the PPB.
675 		 */
676 		for (; range != 0; range--) {
677 			if (memlist_find_with_startaddr(
678 			    &pci_bus_res[parbus].bus_space,
679 			    subbus + 1, range, 1) != NULL)
680 				break; /* find bus range resource at parent */
681 		}
682 		if (range != 0) {
683 			memlist_insert(&pci_bus_res[secbus].bus_space,
684 			    subbus + 1, range);
685 			subbus = subbus + range;
686 			pci_bus_res[secbus].sub_bus = subbus;
687 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
688 			add_bus_range_prop(secbus);
689 
690 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
691 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
692 			    secbus, subbus);
693 		}
694 	}
695 
696 	/*
697 	 * Calculate required IO size
698 	 * We are going to assign 512 bytes per bus. The size needs to be
699 	 * 4K aligned and the maximum size is 16K.
700 	 */
701 	io_size = (subbus - secbus + 1) * 0x200;
702 	io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1));
703 	if (io_size > 0x4 * PPB_IO_ALIGNMENT)
704 		io_size = 0x4 * PPB_IO_ALIGNMENT;
705 	/*
706 	 * Calculate required MEM size
707 	 * We are going to assign 1M bytes per bus. The size needs to be
708 	 * 1M aligned and the maximum size is 8M.
709 	 */
710 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
711 	if (mem_size > 0x8 * PPB_MEM_ALIGNMENT)
712 		mem_size = 0x8 * PPB_MEM_ALIGNMENT;
713 
714 	/* Subtractive bridge */
715 	if (pci_bus_res[secbus].subtractive && prog_sub) {
716 		/*
717 		 * We program an arbitrary amount of I/O and memory resource
718 		 * for the subtractive bridge so that child dynamic-resource-
719 		 * allocating devices (such as Cardbus bridges) have a chance
720 		 * of success.  Until we have full-tree resource rebalancing,
721 		 * dynamic resource allocation (thru busra) only looks at the
722 		 * parent bridge, so all PPBs must have some allocatable
723 		 * resource.  For non-subtractive bridges, the resources come
724 		 * from the base/limit register "windows", but subtractive
725 		 * bridges often don't program those (since they don't need to).
726 		 * If we put all the remaining resources on the subtractive
727 		 * bridge, then peer non-subtractive bridges can't allocate
728 		 * more space (even though this is probably most correct).
729 		 * If we put the resources only on the parent, then allocations
730 		 * from children of subtractive bridges will fail without
731 		 * special-case code for bypassing the subtractive bridge.
732 		 * This solution is the middle-ground temporary solution until
733 		 * we have fully-capable resource allocation.
734 		 */
735 
736 		/*
737 		 * Add an arbitrary I/O resource to the subtractive PPB
738 		 */
739 		if (pci_bus_res[secbus].io_ports == NULL) {
740 			addr = get_parbus_io_res(parbus, secbus, io_size,
741 			    PPB_IO_ALIGNMENT);
742 			if (addr) {
743 				add_ppb_ranges_prop(secbus);
744 				pci_bus_res[secbus].io_reprogram =
745 				    pci_bus_res[parbus].io_reprogram;
746 
747 				cmn_err(CE_NOTE, "!add io-range on subtractive"
748 				    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
749 				    bus, dev, func, (uint32_t)addr,
750 				    (uint32_t)addr + io_size - 1);
751 			}
752 		}
753 		/*
754 		 * Add an arbitrary memory resource to the subtractive PPB
755 		 */
756 		if (pci_bus_res[secbus].mem_space == NULL) {
757 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
758 			    PPB_MEM_ALIGNMENT);
759 			if (addr) {
760 				add_ppb_ranges_prop(secbus);
761 				pci_bus_res[secbus].mem_reprogram =
762 				    pci_bus_res[parbus].mem_reprogram;
763 
764 				cmn_err(CE_NOTE, "!add mem-range on "
765 				    "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
766 				    bus, dev, func, (uint32_t)addr,
767 				    (uint32_t)addr + mem_size - 1);
768 			}
769 		}
770 
771 		goto cmd_enable;
772 	}
773 
774 	/*
775 	 * Check to see if we need to reprogram I/O space, either because the
776 	 * parent bus needed reprogramming and so do we, or because I/O space is
777 	 * disabled in base/limit or command register.
778 	 */
779 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
780 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
781 	io_base = (io_base & 0xf0) << 8;
782 	io_limit = ((io_limit & 0xf0) << 8) | 0xfff;
783 
784 	if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) ||
785 	    (!(cmd_reg & PCI_COMM_IO))) {
786 		if (pci_bus_res[secbus].io_ports_used) {
787 			memlist_merge(&pci_bus_res[secbus].io_ports_used,
788 			    &pci_bus_res[secbus].io_ports);
789 		}
790 		if (pci_bus_res[secbus].io_ports &&
791 		    (!pci_bus_res[parbus].io_reprogram) &&
792 		    (!pci_bus_res[parbus].subtractive)) {
793 			/* rechoose old io ports info */
794 			list = pci_bus_res[secbus].io_ports;
795 			io_base = (uint_t)list->address;
796 			/* 4K aligned */
797 			io_base = io_base & (~(PPB_IO_ALIGNMENT - 1));
798 			io_limit = (uint_t)(list->address + list->size);
799 			while (list->next) {
800 				list = list->next;
801 				if ((list->address + list->size) > io_limit)
802 					io_limit = (uint_t)
803 					    (list->address + list->size);
804 			}
805 			io_limit = io_limit - 1;
806 			/* 4K aligned */
807 			io_limit = (io_limit + PPB_IO_ALIGNMENT) &
808 			    (~(PPB_IO_ALIGNMENT - 1));
809 			io_size = io_limit - io_base;
810 			io_limit = io_limit - 1;
811 			ASSERT(io_base <= io_limit);
812 			memlist_free_all(&pci_bus_res[secbus].io_ports);
813 			memlist_insert(&pci_bus_res[secbus].io_ports,
814 			    io_base, io_size);
815 			memlist_insert(&pci_bus_res[parbus].io_ports_used,
816 			    io_base, io_size);
817 			if (pci_bus_res[parbus].io_ports)
818 				(void) memlist_remove(
819 				    &pci_bus_res[parbus].io_ports,
820 				    io_base, io_size);
821 			pci_bus_res[secbus].io_reprogram = B_TRUE;
822 		} else {
823 			/* get new io ports from parent bus */
824 			addr = get_parbus_io_res(parbus, secbus, io_size,
825 			    PPB_IO_ALIGNMENT);
826 			if (addr) {
827 				io_base = addr;
828 				io_limit = addr + io_size - 1;
829 				pci_bus_res[secbus].io_reprogram = B_TRUE;
830 			}
831 		}
832 		if (pci_bus_res[secbus].io_reprogram) {
833 			/* reprogram PPB regs */
834 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
835 			    (uchar_t)((io_base>>8) & 0xf0));
836 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
837 			    (uchar_t)((io_limit>>8) & 0xf0));
838 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
839 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
840 			add_ppb_ranges_prop(secbus);
841 
842 			cmn_err(CE_NOTE, "!reprogram io-range on"
843 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
844 			    bus, dev, func, io_base, io_limit);
845 		}
846 	}
847 
848 	/*
849 	 * Check memory space as we did I/O space.
850 	 */
851 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
852 	mem_base = (mem_base & 0xfff0) << 16;
853 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
854 	mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff;
855 
856 	if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) ||
857 	    (!(cmd_reg & PCI_COMM_MAE))) {
858 		if (pci_bus_res[secbus].mem_space_used) {
859 			memlist_merge(&pci_bus_res[secbus].mem_space_used,
860 			    &pci_bus_res[secbus].mem_space);
861 		}
862 		if (pci_bus_res[secbus].mem_space &&
863 		    (!pci_bus_res[parbus].mem_reprogram) &&
864 		    (!pci_bus_res[parbus].subtractive)) {
865 			/* rechoose old mem resource */
866 			list = pci_bus_res[secbus].mem_space;
867 			mem_base = (uint_t)list->address;
868 			/* 1M aligned */
869 			mem_base = mem_base & (~0xfffff);
870 			mem_limit = (uint_t)(list->address + list->size);
871 			while (list->next) {
872 				list = list->next;
873 				if ((list->address + list->size) > mem_limit)
874 					mem_limit = (uint_t)
875 					    (list->address + list->size);
876 			}
877 			mem_limit = mem_limit - 1;
878 			/* 1M aligned */
879 			mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) &
880 			    (~(PPB_MEM_ALIGNMENT - 1));
881 			mem_size = mem_limit - mem_base;
882 			mem_limit = mem_limit - 1;
883 			ASSERT(mem_base <= mem_limit);
884 			memlist_free_all(&pci_bus_res[secbus].mem_space);
885 			memlist_insert(&pci_bus_res[secbus].mem_space,
886 			    mem_base, mem_size);
887 			memlist_insert(&pci_bus_res[parbus].mem_space_used,
888 			    mem_base, mem_size);
889 			if (pci_bus_res[parbus].mem_space)
890 				(void) memlist_remove(
891 				    &pci_bus_res[parbus].mem_space,
892 				    mem_base, mem_size);
893 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
894 		} else {
895 			/* get new mem resource from parent bus */
896 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
897 			    PPB_MEM_ALIGNMENT);
898 			if (addr) {
899 				mem_base = addr;
900 				mem_limit = addr + mem_size - 1;
901 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
902 			}
903 		}
904 
905 		if (pci_bus_res[secbus].mem_reprogram) {
906 			/* reprogram PPB regs */
907 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
908 			    (uint16_t)((mem_base>>16) & 0xfff0));
909 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
910 			    (uint16_t)((mem_limit>>16) & 0xfff0));
911 			add_ppb_ranges_prop(secbus);
912 
913 			cmn_err(CE_NOTE, "!reprogram mem-range on"
914 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
915 			    bus, dev, func, mem_base, mem_limit);
916 		}
917 	}
918 
919 cmd_enable:
920 	if (pci_bus_res[secbus].io_ports)
921 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
922 	if (pci_bus_res[secbus].mem_space)
923 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
924 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
925 }
926 
927 void
928 pci_reprogram(void)
929 {
930 	int i, pci_reconfig = 1;
931 	char *onoff;
932 
933 	/*
934 	 * Excise phantom roots if possible
935 	 */
936 	pci_renumber_root_busses();
937 
938 	/* add bus-range property for root/peer bus nodes */
939 	for (i = 0; i <= pci_bios_nbus; i++) {
940 		if (pci_bus_res[i].par_bus == (uchar_t)-1) {
941 			uchar_t subbus;
942 			if (pci_root_subbus(i, &subbus) == AE_OK)
943 				pci_bus_res[i].sub_bus = subbus;
944 			add_bus_range_prop(i);
945 		}
946 		/* setup bus range resource on each bus */
947 		setup_bus_res(i);
948 	}
949 
950 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
951 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
952 		if (strcmp(onoff, "off") == 0) {
953 			pci_reconfig = 0;
954 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
955 		}
956 		ddi_prop_free(onoff);
957 	}
958 
959 	/* remove used-resources from PCI resource maps */
960 	remove_used_resources();
961 	remove_subtractive_res();
962 
963 	/* reprogram the non-subtractive PPB */
964 	if (pci_reconfig)
965 		for (i = 0; i <= pci_bios_nbus; i++)
966 			fix_ppb_res(i, B_FALSE);
967 
968 	for (i = 0; i <= pci_bios_nbus; i++) {
969 		/* configure devices not configured by BIOS */
970 		if (pci_reconfig) {
971 			/*
972 			 * Reprogram the subtractive PPB. At this time, all its
973 			 * siblings should have got their resources already.
974 			 */
975 			if (pci_bus_res[i].subtractive)
976 				fix_ppb_res(i, B_TRUE);
977 			enumerate_bus_devs(i, CONFIG_NEW);
978 		}
979 		/* All dev programmed, so we can create available prop */
980 		add_bus_available_prop(i);
981 	}
982 }
983 
984 /*
985  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
986  */
987 static void
988 create_root_bus_dip(uchar_t bus)
989 {
990 	int pci_regs[] = {0, 0, 0};
991 	dev_info_t *dip;
992 
993 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
994 
995 	num_root_bus++;
996 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
997 	    (pnode_t)DEVI_SID_NODEID, &dip);
998 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
999 	    "#address-cells", 3);
1000 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1001 	    "#size-cells", 2);
1002 	pci_regs[0] = pci_bus_res[bus].root_addr;
1003 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1004 	    "reg", (int *)pci_regs, 3);
1005 
1006 	/*
1007 	 * If system has PCIe bus, then create different properties
1008 	 */
1009 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
1010 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1011 		    "device_type", "pci");
1012 
1013 	(void) ndi_devi_bind_driver(dip, 0);
1014 	pci_bus_res[bus].dip = dip;
1015 	pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE);
1016 	pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE);
1017 	pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE);
1018 
1019 	if (bus != 0)
1020 		return;
1021 
1022 	/*
1023 	 * Special treatment of bus 0:
1024 	 * If no resource from MPSPEC/HRT, copy pcimem from boot
1025 	 * and make I/O space the entire range starting at 0x100. There
1026 	 * is no difference between prefetchable memory or not.
1027 	 */
1028 	if (pci_bus_res[0].mem_space == NULL)
1029 		pci_bus_res[0].mem_space =
1030 		    memlist_dup(bootops->boot_mem->pcimem);
1031 	/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
1032 	if (pci_bus_res[0].io_ports == NULL)
1033 		memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff);
1034 }
1035 
1036 /*
1037  * For any fixed configuration (often compatability) pci devices
1038  * and those with their own expansion rom, create device nodes
1039  * to hold the already configured device details.
1040  */
1041 void
1042 enumerate_bus_devs(uchar_t bus, int config_op)
1043 {
1044 	uchar_t dev, func, nfunc, header;
1045 	ushort_t venid;
1046 	struct pci_devfunc *devlist = NULL, *entry;
1047 
1048 	if (config_op == CONFIG_NEW) {
1049 		dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1050 	} else if (config_op == CONFIG_FIX) {
1051 		dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
1052 	} else
1053 		dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1054 
1055 	for (dev = 0; dev < max_dev_pci; dev++) {
1056 		nfunc = 1;
1057 		for (func = 0; func < nfunc; func++) {
1058 
1059 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
1060 			    dev, func);
1061 
1062 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1063 
1064 			if ((venid == 0xffff) || (venid == 0)) {
1065 				/* no function at this address */
1066 				continue;
1067 			}
1068 
1069 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1070 			if (header == 0xff) {
1071 				continue; /* illegal value */
1072 			}
1073 
1074 			/*
1075 			 * according to some mail from Microsoft posted
1076 			 * to the pci-drivers alias, their only requirement
1077 			 * for a multifunction device is for the 1st
1078 			 * function to have to PCI_HEADER_MULTI bit set.
1079 			 */
1080 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
1081 				nfunc = 8;
1082 			}
1083 
1084 			if (config_op == CONFIG_FIX ||
1085 			    config_op == CONFIG_INFO) {
1086 				/*
1087 				 * Create the node, unconditionally, on the
1088 				 * first pass only.  It may still need
1089 				 * resource assignment, which will be
1090 				 * done on the second, CONFIG_NEW, pass.
1091 				 */
1092 				process_devfunc(bus, dev, func, header,
1093 				    venid, config_op);
1094 
1095 			}
1096 		}
1097 	}
1098 
1099 	if (config_op == CONFIG_NEW) {
1100 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1101 		while (devlist) {
1102 			entry = devlist;
1103 			devlist = entry->next;
1104 			if (entry->reprogram ||
1105 			    pci_bus_res[bus].io_reprogram ||
1106 			    pci_bus_res[bus].mem_reprogram) {
1107 				/* reprogram device(s) */
1108 				(void) add_reg_props(entry->dip, bus,
1109 				    entry->dev, entry->func, CONFIG_NEW, 0);
1110 			}
1111 			kmem_free(entry, sizeof (*entry));
1112 		}
1113 		pci_bus_res[bus].privdata = NULL;
1114 	}
1115 }
1116 
1117 static int
1118 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
1119     ushort_t subvenid, ushort_t subdevid)
1120 {
1121 	static int prop_exist = -1;
1122 	static char *pciide_str;
1123 	char compat[32];
1124 
1125 	if (prop_exist == -1) {
1126 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
1127 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
1128 		    &pciide_str) == DDI_SUCCESS);
1129 	}
1130 
1131 	if (!prop_exist)
1132 		return (0);
1133 
1134 	/* compare property value against various forms of compatible */
1135 	if (subvenid) {
1136 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
1137 		    venid, devid, subvenid, subdevid, revid);
1138 		if (strcmp(pciide_str, compat) == 0)
1139 			return (1);
1140 
1141 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
1142 		    venid, devid, subvenid, subdevid);
1143 		if (strcmp(pciide_str, compat) == 0)
1144 			return (1);
1145 
1146 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
1147 		    subvenid, subdevid);
1148 		if (strcmp(pciide_str, compat) == 0)
1149 			return (1);
1150 	}
1151 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
1152 	    venid, devid, revid);
1153 	if (strcmp(pciide_str, compat) == 0)
1154 		return (1);
1155 
1156 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
1157 	if (strcmp(pciide_str, compat) == 0)
1158 		return (1);
1159 
1160 	return (0);
1161 }
1162 
1163 static int
1164 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
1165     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
1166 {
1167 	struct ide_table {	/* table for PCI_MASS_OTHER */
1168 		ushort_t venid;
1169 		ushort_t devid;
1170 	} *entry;
1171 
1172 	/* XXX SATA and other devices: need a way to add dynamically */
1173 	static struct ide_table ide_other[] = {
1174 		{0x1095, 0x3112},
1175 		{0x1095, 0x3114},
1176 		{0x1095, 0x3512},
1177 		{0x1095, 0x680},	/* Sil0680 */
1178 		{0x1283, 0x8211},	/* ITE 8211F is subcl PCI_MASS_OTHER */
1179 		{0, 0}
1180 	};
1181 
1182 	if (basecl != PCI_CLASS_MASS)
1183 		return (0);
1184 
1185 	if (subcl == PCI_MASS_IDE) {
1186 		return (1);
1187 	}
1188 
1189 	if (check_pciide_prop(revid, venid, devid, subvenid, subdevid))
1190 		return (1);
1191 
1192 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
1193 		return (0);
1194 	}
1195 
1196 	entry = &ide_other[0];
1197 	while (entry->venid) {
1198 		if (entry->venid == venid && entry->devid == devid)
1199 			return (1);
1200 		entry++;
1201 	}
1202 	return (0);
1203 }
1204 
1205 static int
1206 is_display(uint_t classcode)
1207 {
1208 	static uint_t disp_classes[] = {
1209 		0x000100,
1210 		0x030000,
1211 		0x030001
1212 	};
1213 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
1214 
1215 	for (i = 0; i < nclasses; i++) {
1216 		if (classcode == disp_classes[i])
1217 			return (1);
1218 	}
1219 	return (0);
1220 }
1221 
1222 static void
1223 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1224     void (*undofn)(uint8_t, uint8_t, uint8_t))
1225 {
1226 	struct pci_fixundo *newundo;
1227 
1228 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1229 
1230 	/*
1231 	 * Adding an item to this list means that we must turn its NMIENABLE
1232 	 * bit back on at a later time.
1233 	 */
1234 	newundo->bus = bus;
1235 	newundo->dev = dev;
1236 	newundo->fn = fn;
1237 	newundo->undofn = undofn;
1238 	newundo->next = undolist;
1239 
1240 	/* add to the undo list in LIFO order */
1241 	undolist = newundo;
1242 }
1243 
1244 void
1245 add_pci_fixes(void)
1246 {
1247 	int i;
1248 
1249 	for (i = 0; i <= pci_bios_nbus; i++) {
1250 		/*
1251 		 * For each bus, apply needed fixes to the appropriate devices.
1252 		 * This must be done before the main enumeration loop because
1253 		 * some fixes must be applied to devices normally encountered
1254 		 * later in the pci scan (e.g. if a fix to device 7 must be
1255 		 * applied before scanning device 6, applying fixes in the
1256 		 * normal enumeration loop would obviously be too late).
1257 		 */
1258 		enumerate_bus_devs(i, CONFIG_FIX);
1259 	}
1260 }
1261 
1262 void
1263 undo_pci_fixes(void)
1264 {
1265 	struct pci_fixundo *nextundo;
1266 	uint8_t bus, dev, fn;
1267 
1268 	/*
1269 	 * All fixes in the undo list are performed unconditionally.  Future
1270 	 * fixes may require selective undo.
1271 	 */
1272 	while (undolist != NULL) {
1273 
1274 		bus = undolist->bus;
1275 		dev = undolist->dev;
1276 		fn = undolist->fn;
1277 
1278 		(*(undolist->undofn))(bus, dev, fn);
1279 
1280 		nextundo = undolist->next;
1281 		kmem_free(undolist, sizeof (struct pci_fixundo));
1282 		undolist = nextundo;
1283 	}
1284 }
1285 
1286 static void
1287 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1288 {
1289 	uint8_t val8;
1290 
1291 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1292 	/*
1293 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1294 	 * to handle more critical PCI errors (e.g. PERR#).
1295 	 */
1296 	val8 |= AMD8111_ENABLENMI;
1297 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1298 }
1299 
1300 static void
1301 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1302 {
1303 	uint8_t val8;
1304 
1305 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1306 
1307 	if ((val8 & AMD8111_ENABLENMI) == 0)
1308 		return;
1309 
1310 	/*
1311 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1312 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1313 	 * which sometimes prevents all devices from being enumerated.
1314 	 */
1315 	val8 &= ~AMD8111_ENABLENMI;
1316 
1317 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1318 
1319 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1320 }
1321 
1322 static void
1323 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1324 {
1325 	uint16_t status;
1326 	uint8_t header;
1327 	uint8_t cap_ptr;
1328 	uint8_t cap_id;
1329 	uint16_t pmcsr;
1330 
1331 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1332 	if (!(status & PCI_STAT_CAP))
1333 		return;	/* No capabilities list */
1334 
1335 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1336 	if (header == PCI_HEADER_CARDBUS)
1337 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1);
1338 	else
1339 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1340 	/*
1341 	 * Walk the capabilities list searching for a PM entry.
1342 	 */
1343 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1344 		cap_ptr &= PCI_CAP_PTR_MASK;
1345 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1346 		if (cap_id == PCI_CAP_ID_PM) {
1347 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1348 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1349 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1350 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1351 			break;
1352 		}
1353 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1354 	}
1355 
1356 }
1357 
1358 static void
1359 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1360     ushort_t vendorid, int config_op)
1361 {
1362 	char nodename[32], unitaddr[5];
1363 	dev_info_t *dip;
1364 	uchar_t basecl, subcl, progcl, intr, revid;
1365 	ushort_t subvenid, subdevid, status;
1366 	ushort_t slot_num;
1367 	uint_t classcode, revclass;
1368 	int reprogram = 0, pciide = 0;
1369 	int power[2] = {1, 1};
1370 	int pciex = 0;
1371 	ushort_t is_pci_bridge = 0;
1372 	struct pci_devfunc *devlist = NULL, *entry = NULL;
1373 	iommu_private_t *private;
1374 
1375 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1376 
1377 	switch (header & PCI_HEADER_TYPE_M) {
1378 	case PCI_HEADER_ZERO:
1379 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1380 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1381 		break;
1382 	case PCI_HEADER_CARDBUS:
1383 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1384 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1385 		/* Record the # of cardbus bridges found on the bus */
1386 		if (config_op == CONFIG_INFO)
1387 			pci_bus_res[bus].num_cbb++;
1388 		break;
1389 	default:
1390 		subvenid = 0;
1391 		subdevid = 0;
1392 		break;
1393 	}
1394 
1395 	if (config_op == CONFIG_FIX) {
1396 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
1397 			pci_fix_amd8111(bus, dev, func);
1398 		}
1399 		return;
1400 	}
1401 
1402 	/* XXX should be use generic names? derive from class? */
1403 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1404 	classcode = revclass >> 8;
1405 	revid = revclass & 0xff;
1406 
1407 	/* figure out if this is pci-ide */
1408 	basecl = classcode >> 16;
1409 	subcl = (classcode >> 8) & 0xff;
1410 	progcl = classcode & 0xff;
1411 
1412 
1413 	if (is_display(classcode))
1414 		(void) snprintf(nodename, sizeof (nodename), "display");
1415 	else if (subvenid != 0)
1416 		(void) snprintf(nodename, sizeof (nodename),
1417 		    "pci%x,%x", subvenid, subdevid);
1418 	else
1419 		(void) snprintf(nodename, sizeof (nodename),
1420 		    "pci%x,%x", vendorid, deviceid);
1421 
1422 	/* make sure parent bus dip has been created */
1423 	if (pci_bus_res[bus].dip == NULL) {
1424 		create_root_bus_dip(bus);
1425 	}
1426 
1427 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
1428 	    DEVI_SID_NODEID, &dip);
1429 
1430 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num,
1431 	    &is_pci_bridge) == B_TRUE)
1432 		pciex = 1;
1433 
1434 	/* add properties */
1435 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
1436 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
1437 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
1438 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1439 	    "class-code", classcode);
1440 	if (func == 0)
1441 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
1442 	else
1443 		(void) snprintf(unitaddr, sizeof (unitaddr),
1444 		    "%x,%x", dev, func);
1445 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1446 	    "unit-address", unitaddr);
1447 
1448 	/* add device_type for display nodes */
1449 	if (is_display(classcode)) {
1450 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1451 		    "device_type", "display");
1452 	}
1453 	/* add special stuff for header type */
1454 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
1455 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1456 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
1457 
1458 		if (subvenid != 0) {
1459 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1460 			    "subsystem-id", subdevid);
1461 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1462 			    "subsystem-vendor-id", subvenid);
1463 		}
1464 		if (!pciex)
1465 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1466 			    "min-grant", mingrant);
1467 		if (!pciex)
1468 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1469 			    "max-latency", maxlatency);
1470 	}
1471 
1472 	/* interrupt, record if not 0 */
1473 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
1474 	if (intr != 0)
1475 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1476 		    "interrupts", intr);
1477 
1478 	/*
1479 	 * Add support for 133 mhz pci eventually
1480 	 */
1481 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1482 
1483 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1484 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
1485 	if (!pciex && (status & PCI_STAT_FBBC))
1486 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1487 		    "fast-back-to-back");
1488 	if (!pciex && (status & PCI_STAT_66MHZ))
1489 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1490 		    "66mhz-capable");
1491 	if (status & PCI_STAT_UDF)
1492 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1493 		    "udf-supported");
1494 	if (pciex && slot_num) {
1495 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1496 		    "physical-slot#", slot_num);
1497 		if (!is_pci_bridge)
1498 			pciex_slot_names_prop(dip, slot_num);
1499 	}
1500 
1501 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1502 	    "power-consumption", power, 2);
1503 
1504 	/* Set the device PM state to D0 */
1505 	set_devpm_d0(bus, dev, func);
1506 
1507 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
1508 		add_ppb_props(dip, bus, dev, func, pciex);
1509 	else {
1510 		/*
1511 		 * Record the non-PPB devices on the bus for possible
1512 		 * reprogramming at 2nd bus enumeration.
1513 		 * Note: PPB reprogramming is done in fix_ppb_res()
1514 		 */
1515 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1516 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
1517 		entry->dip = dip;
1518 		entry->dev = dev;
1519 		entry->func = func;
1520 		entry->next = devlist;
1521 		pci_bus_res[bus].privdata = entry;
1522 	}
1523 
1524 	if (config_op == CONFIG_INFO &&
1525 	    IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
1526 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
1527 	}
1528 
1529 	/* check for ck8-04 based PCI ISA bridge only */
1530 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
1531 	    (func == 0))
1532 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
1533 
1534 	if (pciex && is_pci_bridge)
1535 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
1536 		    (char *)"PCIe-PCI bridge");
1537 	else
1538 		add_model_prop(dip, classcode);
1539 
1540 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
1541 	    revid, classcode, pciex);
1542 
1543 	/*
1544 	 * See if this device is a controller that advertises
1545 	 * itself to be a standard ATA task file controller, or one that
1546 	 * has been hard coded.
1547 	 *
1548 	 * If it is, check if any other higher precedence driver listed in
1549 	 * driver_aliases will claim the node by calling
1550 	 * ddi_compatibile_driver_major.  If so, clear pciide and do not
1551 	 * create a pci-ide node or any other special handling.
1552 	 *
1553 	 * If another driver does not bind, set the node name to pci-ide
1554 	 * and then let the special pci-ide handling for registers and
1555 	 * child pci-ide nodes proceed below.
1556 	 */
1557 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
1558 	    subvenid, subdevid) == 1) {
1559 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
1560 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
1561 			pciide = 1;
1562 		}
1563 	}
1564 
1565 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
1566 	(void) ndi_devi_bind_driver(dip, 0);
1567 
1568 	/* special handling for pci-ide */
1569 	if (pciide) {
1570 		dev_info_t *cdip;
1571 
1572 		/*
1573 		 * Create properties specified by P1275 Working Group
1574 		 * Proposal #414 Version 1
1575 		 */
1576 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1577 		    "device_type", "pci-ide");
1578 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1579 		    "#address-cells", 1);
1580 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1581 		    "#size-cells", 0);
1582 
1583 		/* allocate two child nodes */
1584 		ndi_devi_alloc_sleep(dip, "ide",
1585 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1586 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1587 		    "reg", 0);
1588 		(void) ndi_devi_bind_driver(cdip, 0);
1589 		ndi_devi_alloc_sleep(dip, "ide",
1590 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1591 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1592 		    "reg", 1);
1593 		(void) ndi_devi_bind_driver(cdip, 0);
1594 
1595 		reprogram = 0;	/* don't reprogram pci-ide bridge */
1596 	}
1597 
1598 	/* allocate and set up iommu private */
1599 	private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP);
1600 	private->idp_seg = 0;
1601 	private->idp_bus = bus;
1602 	private->idp_devfn = (dev << 3) | func;
1603 	private->idp_sec = 0;
1604 	private->idp_sub = 0;
1605 	private->idp_bbp_type = IOMMU_PPB_NONE;
1606 	/* record the bridge */
1607 	private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) &&
1608 	    (subcl == PCI_BRIDGE_PCI));
1609 	if (private->idp_is_bridge) {
1610 		private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
1611 		private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
1612 		if (pciex && is_pci_bridge)
1613 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCI;
1614 		else if (pciex)
1615 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE;
1616 		else
1617 			private->idp_bbp_type = IOMMU_PPB_PCI_PCI;
1618 	}
1619 	/* record the special devices */
1620 	private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE);
1621 	private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) &&
1622 	    (subcl == PCI_BRIDGE_ISA));
1623 	private->idp_domain = NULL;
1624 	/* hook the private to dip */
1625 	DEVI(dip)->devi_iommu_private = private;
1626 
1627 	if (reprogram && (entry != NULL))
1628 		entry->reprogram = B_TRUE;
1629 }
1630 
1631 /*
1632  * Set the compatible property to a value compliant with
1633  * rev 2.1 of the IEEE1275 PCI binding.
1634  * (Also used for PCI-Express devices).
1635  *
1636  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
1637  *   pciVVVV,DDDD.SSSS.ssss	(1)
1638  *   pciSSSS,ssss		(2)
1639  *   pciVVVV,DDDD.RR		(3)
1640  *   pciVVVV,DDDD		(4)
1641  *   pciclass,CCSSPP		(5)
1642  *   pciclass,CCSS		(6)
1643  *
1644  * The Subsystem (SSSS) forms are not inserted if
1645  * subsystem-vendor-id is 0.
1646  *
1647  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
1648  * property 2 is not created as per "1275 bindings for PCI Express Interconnect"
1649  *
1650  * Set with setprop and \x00 between each
1651  * to generate the encoded string array form.
1652  */
1653 void
1654 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
1655     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
1656     int pciex)
1657 {
1658 	int i = 0;
1659 	int size = COMPAT_BUFSIZE;
1660 	char *compat[13];
1661 	char *buf, *curr;
1662 
1663 	curr = buf = kmem_alloc(size, KM_SLEEP);
1664 
1665 	if (pciex) {
1666 		if (subvenid) {
1667 			compat[i++] = curr;	/* form 0 */
1668 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
1669 			    vendorid, deviceid, subvenid, subdevid, revid);
1670 			size -= strlen(curr) + 1;
1671 			curr += strlen(curr) + 1;
1672 
1673 			compat[i++] = curr;	/* form 1 */
1674 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
1675 			    vendorid, deviceid, subvenid, subdevid);
1676 			size -= strlen(curr) + 1;
1677 			curr += strlen(curr) + 1;
1678 
1679 		}
1680 		compat[i++] = curr;	/* form 3 */
1681 		(void) snprintf(curr, size, "pciex%x,%x.%x",
1682 		    vendorid, deviceid, revid);
1683 		size -= strlen(curr) + 1;
1684 		curr += strlen(curr) + 1;
1685 
1686 		compat[i++] = curr;	/* form 4 */
1687 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
1688 		size -= strlen(curr) + 1;
1689 		curr += strlen(curr) + 1;
1690 
1691 		compat[i++] = curr;	/* form 5 */
1692 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
1693 		size -= strlen(curr) + 1;
1694 		curr += strlen(curr) + 1;
1695 
1696 		compat[i++] = curr;	/* form 6 */
1697 		(void) snprintf(curr, size, "pciexclass,%04x",
1698 		    (classcode >> 8));
1699 		size -= strlen(curr) + 1;
1700 		curr += strlen(curr) + 1;
1701 	}
1702 
1703 	if (subvenid) {
1704 		compat[i++] = curr;	/* form 0 */
1705 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
1706 		    vendorid, deviceid, subvenid, subdevid, revid);
1707 		size -= strlen(curr) + 1;
1708 		curr += strlen(curr) + 1;
1709 
1710 		compat[i++] = curr;	/* form 1 */
1711 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
1712 		    vendorid, deviceid, subvenid, subdevid);
1713 		size -= strlen(curr) + 1;
1714 		curr += strlen(curr) + 1;
1715 
1716 		compat[i++] = curr;	/* form 2 */
1717 		(void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid);
1718 		size -= strlen(curr) + 1;
1719 		curr += strlen(curr) + 1;
1720 	}
1721 	compat[i++] = curr;	/* form 3 */
1722 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
1723 	size -= strlen(curr) + 1;
1724 	curr += strlen(curr) + 1;
1725 
1726 	compat[i++] = curr;	/* form 4 */
1727 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
1728 	size -= strlen(curr) + 1;
1729 	curr += strlen(curr) + 1;
1730 
1731 	compat[i++] = curr;	/* form 5 */
1732 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
1733 	size -= strlen(curr) + 1;
1734 	curr += strlen(curr) + 1;
1735 
1736 	compat[i++] = curr;	/* form 6 */
1737 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
1738 	size -= strlen(curr) + 1;
1739 	curr += strlen(curr) + 1;
1740 
1741 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
1742 	    "compatible", compat, i);
1743 	kmem_free(buf, COMPAT_BUFSIZE);
1744 }
1745 
1746 /*
1747  * Adjust the reg properties for a dual channel PCI-IDE device.
1748  *
1749  * NOTE: don't do anything that changes the order of the hard-decodes
1750  * and programmed BARs. The kernel driver depends on these values
1751  * being in this order regardless of whether they're for a 'native'
1752  * mode BAR or not.
1753  */
1754 /*
1755  * config info for pci-ide devices
1756  */
1757 static struct {
1758 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
1759 	uchar_t  bar_offset;	/* offset for alt status register */
1760 	ushort_t addr;		/* compatibility mode base address */
1761 	ushort_t length;	/* number of ports for this BAR */
1762 } pciide_bar[] = {
1763 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
1764 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
1765 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
1766 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
1767 };
1768 
1769 static int
1770 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
1771 {
1772 	int hard_decode = 0;
1773 
1774 	/*
1775 	 * Adjust the base and len for the BARs of the PCI-IDE
1776 	 * device's primary and secondary controllers. The first
1777 	 * two BARs are for the primary controller and the next
1778 	 * two BARs are for the secondary controller. The fifth
1779 	 * and sixth bars are never adjusted.
1780 	 */
1781 	if (index >= 0 && index <= 3) {
1782 		*lenp = pciide_bar[index].length;
1783 
1784 		if (progcl & pciide_bar[index].native_mask) {
1785 			*basep += pciide_bar[index].bar_offset;
1786 		} else {
1787 			*basep = pciide_bar[index].addr;
1788 			hard_decode = 1;
1789 		}
1790 	}
1791 
1792 	/*
1793 	 * if either base or len is zero make certain both are zero
1794 	 */
1795 	if (*basep == 0 || *lenp == 0) {
1796 		*basep = 0;
1797 		*lenp = 0;
1798 		hard_decode = 0;
1799 	}
1800 
1801 	return (hard_decode);
1802 }
1803 
1804 
1805 /*
1806  * Add the "reg" and "assigned-addresses" property
1807  */
1808 static int
1809 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
1810     int config_op, int pciide)
1811 {
1812 	uchar_t baseclass, subclass, progclass, header;
1813 	ushort_t bar_sz;
1814 	uint_t value = 0, len, devloc;
1815 	uint_t base, base_hi, type;
1816 	ushort_t offset, end;
1817 	int max_basereg, j, reprogram = 0;
1818 	uint_t phys_hi;
1819 	struct memlist **io_res, **mres, **mem_res, **pmem_res;
1820 	struct memlist **io_res_used, **mres_used;
1821 	struct memlist **mem_res_used, **pmem_res_used;
1822 	uchar_t res_bus;
1823 
1824 	pci_regspec_t regs[16] = {{0}};
1825 	pci_regspec_t assigned[15] = {{0}};
1826 	int nreg, nasgn;
1827 
1828 	io_res = &pci_bus_res[bus].io_ports;
1829 	io_res_used = &pci_bus_res[bus].io_ports_used;
1830 	mem_res = &pci_bus_res[bus].mem_space;
1831 	mem_res_used = &pci_bus_res[bus].mem_space_used;
1832 	if (bus == 0) {	/* for bus 0, there is only mem_space */
1833 		pmem_res = mem_res;
1834 		pmem_res_used = mem_res_used;
1835 	} else {
1836 		pmem_res = &pci_bus_res[bus].pmem_space;
1837 		pmem_res_used = &pci_bus_res[bus].pmem_space_used;
1838 	}
1839 
1840 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
1841 	regs[0].pci_phys_hi = devloc;
1842 	nreg = 1;	/* rest of regs[0] is all zero */
1843 	nasgn = 0;
1844 
1845 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
1846 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
1847 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
1848 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1849 
1850 	switch (header) {
1851 	case PCI_HEADER_ZERO:
1852 		max_basereg = PCI_BASE_NUM;
1853 		break;
1854 	case PCI_HEADER_PPB:
1855 		max_basereg = PCI_BCNF_BASE_NUM;
1856 		break;
1857 	case PCI_HEADER_CARDBUS:
1858 		max_basereg = PCI_CBUS_BASE_NUM;
1859 		break;
1860 	default:
1861 		max_basereg = 0;
1862 		break;
1863 	}
1864 
1865 	/*
1866 	 * Create the register property by saving the current
1867 	 * value of the base register. Write 0xffffffff to the
1868 	 * base register.  Read the value back to determine the
1869 	 * required size of the address space.  Restore the base
1870 	 * register contents.
1871 	 *
1872 	 * Do not disable I/O and memory access; this isn't necessary
1873 	 * since no driver is yet attached to this device, and disabling
1874 	 * I/O and memory access has the side-effect of disabling PCI-PCI
1875 	 * bridge mappings, which makes the bridge transparent to secondary-
1876 	 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge
1877 	 * Spec V1.2).
1878 	 */
1879 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
1880 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
1881 	    j++, offset += bar_sz) {
1882 		int hard_decode = 0;
1883 
1884 		/* determine the size of the address space */
1885 		base = pci_getl(bus, dev, func, offset);
1886 		pci_putl(bus, dev, func, offset, 0xffffffff);
1887 		value = pci_getl(bus, dev, func, offset);
1888 		pci_putl(bus, dev, func, offset, base);
1889 
1890 		/* construct phys hi,med.lo, size hi, lo */
1891 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
1892 			/* i/o space */
1893 			bar_sz = PCI_BAR_SZ_32;
1894 			value &= PCI_BASE_IO_ADDR_M;
1895 			len = ((value ^ (value-1)) + 1) >> 1;
1896 
1897 			/* XXX Adjust first 4 IDE registers */
1898 			if (pciide) {
1899 				if (subclass != PCI_MASS_IDE)
1900 					progclass = (PCI_IDE_IF_NATIVE_PRI |
1901 					    PCI_IDE_IF_NATIVE_SEC);
1902 				hard_decode = pciIdeAdjustBAR(progclass, j,
1903 				    &base, &len);
1904 			} else if (value == 0) {
1905 				/* skip base regs with size of 0 */
1906 				continue;
1907 			}
1908 
1909 			regs[nreg].pci_size_low =
1910 			    assigned[nasgn].pci_size_low = len;
1911 			if (!hard_decode) {
1912 				regs[nreg].pci_phys_hi =
1913 				    (PCI_ADDR_IO | devloc) + offset;
1914 			} else {
1915 				regs[nreg].pci_phys_hi =
1916 				    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) +
1917 				    offset;
1918 				regs[nreg].pci_phys_low =
1919 				    base & PCI_BASE_IO_ADDR_M;
1920 			}
1921 			assigned[nasgn].pci_phys_hi =
1922 			    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset;
1923 			type = base & (~PCI_BASE_IO_ADDR_M);
1924 			base &= PCI_BASE_IO_ADDR_M;
1925 			/*
1926 			 * A device under a subtractive PPB can allocate
1927 			 * resources from its parent bus if there is no resource
1928 			 * available on its own bus.
1929 			 */
1930 			if ((config_op == CONFIG_NEW) && (*io_res == NULL)) {
1931 				res_bus = bus;
1932 				while (pci_bus_res[res_bus].subtractive) {
1933 					res_bus = pci_bus_res[res_bus].par_bus;
1934 					if (res_bus == (uchar_t)-1)
1935 						break; /* root bus already */
1936 					if (pci_bus_res[res_bus].io_ports) {
1937 						io_res = &pci_bus_res
1938 						    [res_bus].io_ports;
1939 						break;
1940 					}
1941 				}
1942 			}
1943 
1944 			/*
1945 			 * first pass - gather what's there
1946 			 * update/second pass - adjust/allocate regions
1947 			 *	config - allocate regions
1948 			 */
1949 			if (config_op == CONFIG_INFO) {	/* first pass */
1950 				/* take out of the resource map of the bus */
1951 				if (base != 0) {
1952 					if (*io_res)
1953 						(void) memlist_remove(io_res,
1954 						    base, len);
1955 					memlist_insert(io_res_used, base, len);
1956 				} else
1957 					reprogram = 1;
1958 			} else if ((*io_res && base == 0) ||
1959 			    pci_bus_res[bus].io_reprogram) {
1960 				base = (uint_t)memlist_find(io_res, len, len);
1961 				if (base != 0) {
1962 					memlist_insert(io_res_used, base, len);
1963 					/* XXX need to worry about 64-bit? */
1964 					pci_putl(bus, dev, func, offset,
1965 					    base | type);
1966 					base = pci_getl(bus, dev, func, offset);
1967 					base &= PCI_BASE_IO_ADDR_M;
1968 				}
1969 				if (base == 0) {
1970 					cmn_err(CE_WARN, "failed to program"
1971 					    " IO space [%d/%d/%d] BAR@0x%x"
1972 					    " length 0x%x",
1973 					    bus, dev, func, offset, len);
1974 				}
1975 			}
1976 			assigned[nasgn].pci_phys_low = base;
1977 			nreg++, nasgn++;
1978 
1979 		} else {
1980 			/* memory space */
1981 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
1982 				bar_sz = PCI_BAR_SZ_64;
1983 				base_hi = pci_getl(bus, dev, func, offset + 4);
1984 				phys_hi = PCI_ADDR_MEM64;
1985 			} else {
1986 				bar_sz = PCI_BAR_SZ_32;
1987 				base_hi = 0;
1988 				phys_hi = PCI_ADDR_MEM32;
1989 			}
1990 
1991 			/* skip base regs with size of 0 */
1992 			value &= PCI_BASE_M_ADDR_M;
1993 
1994 			if (value == 0) {
1995 				continue;
1996 			}
1997 			len = ((value ^ (value-1)) + 1) >> 1;
1998 			regs[nreg].pci_size_low =
1999 			    assigned[nasgn].pci_size_low = len;
2000 
2001 			phys_hi |= (devloc | offset);
2002 			if (base & PCI_BASE_PREF_M) {
2003 				mres = pmem_res;
2004 				mres_used = pmem_res_used;
2005 				phys_hi |= PCI_PREFETCH_B;
2006 			} else {
2007 				mres = mem_res;
2008 				mres_used = mem_res_used;
2009 			}
2010 			/*
2011 			 * A device under a subtractive PPB can allocate
2012 			 * resources from its parent bus if there is no resource
2013 			 * available on its own bus.
2014 			 */
2015 			if ((config_op == CONFIG_NEW) && (*mres == NULL)) {
2016 				res_bus = bus;
2017 				while (pci_bus_res[res_bus].subtractive) {
2018 					res_bus = pci_bus_res[res_bus].par_bus;
2019 					if (res_bus == (uchar_t)-1)
2020 						break; /* root bus already */
2021 					if ((phys_hi & PCI_PREFETCH_B) &&
2022 					    (res_bus != 0))
2023 						mres = &pci_bus_res
2024 						    [res_bus].pmem_space;
2025 					else
2026 						mres = &pci_bus_res
2027 						    [res_bus].mem_space;
2028 					if (*mres)
2029 						break;
2030 				}
2031 			}
2032 
2033 			regs[nreg].pci_phys_hi =
2034 			    assigned[nasgn].pci_phys_hi = phys_hi;
2035 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2036 			assigned[nasgn].pci_phys_mid = base_hi;
2037 			type = base & ~PCI_BASE_M_ADDR_M;
2038 			base &= PCI_BASE_M_ADDR_M;
2039 
2040 			if (config_op == CONFIG_INFO) {
2041 				/* take out of the resource map of the bus */
2042 				if (base != 0) {
2043 					if (*mres)
2044 						(void) memlist_remove(mres,
2045 						    base, len);
2046 					memlist_insert(mres_used, base, len);
2047 				} else
2048 					reprogram = 1;
2049 			} else if ((*mres && base == 0) ||
2050 			    pci_bus_res[bus].mem_reprogram) {
2051 				base = (uint_t)memlist_find(mres, len, len);
2052 				if (base != NULL) {
2053 					memlist_insert(mres_used, base, len);
2054 					pci_putl(bus, dev, func, offset,
2055 					    base | type);
2056 					base = pci_getl(bus, dev, func, offset);
2057 					base &= PCI_BASE_M_ADDR_M;
2058 				}
2059 
2060 				if (base == 0) {
2061 					cmn_err(CE_WARN, "failed to program "
2062 					    "mem space [%d/%d/%d] BAR@0x%x"
2063 					    " length 0x%x",
2064 					    bus, dev, func, offset, len);
2065 				}
2066 			}
2067 			assigned[nasgn].pci_phys_low = base;
2068 			nreg++, nasgn++;
2069 		}
2070 	}
2071 	switch (header) {
2072 	case PCI_HEADER_ZERO:
2073 		offset = PCI_CONF_ROM;
2074 		break;
2075 	case PCI_HEADER_PPB:
2076 		offset = PCI_BCNF_ROM;
2077 		break;
2078 	default: /* including PCI_HEADER_CARDBUS */
2079 		goto done;
2080 	}
2081 
2082 	/*
2083 	 * Add the expansion rom memory space
2084 	 * Determine the size of the ROM base reg; don't write reserved bits
2085 	 * ROM isn't in the PCI memory space.
2086 	 */
2087 	base = pci_getl(bus, dev, func, offset);
2088 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2089 	value = pci_getl(bus, dev, func, offset);
2090 	pci_putl(bus, dev, func, offset, base);
2091 	if (value & PCI_BASE_ROM_ENABLE)
2092 		value &= PCI_BASE_ROM_ADDR_M;
2093 	else
2094 		value = 0;
2095 
2096 	if (value != 0) {
2097 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2098 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2099 		    PCI_ADDR_MEM32 | devloc) + offset;
2100 		base &= PCI_BASE_ROM_ADDR_M;
2101 		assigned[nasgn].pci_phys_low = base;
2102 		len = ((value ^ (value-1)) + 1) >> 1;
2103 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
2104 		nreg++, nasgn++;
2105 		/* take it out of the memory resource */
2106 		if (*mem_res && base != 0)
2107 			(void) memlist_remove(mem_res, base, len);
2108 		if (base != 0)
2109 			memlist_insert(mem_res, base, len);
2110 	}
2111 
2112 	/*
2113 	 * The following are ISA resources. There are not part
2114 	 * of the PCI local bus resources. So don't attempt to
2115 	 * do resource accounting against PCI.
2116 	 */
2117 
2118 	/* add the three hard-decode, aliased address spaces for VGA */
2119 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
2120 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
2121 
2122 		/* VGA hard decode 0x3b0-0x3bb */
2123 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2124 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2125 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
2126 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
2127 		nreg++, nasgn++;
2128 
2129 		/* VGA hard decode 0x3c0-0x3df */
2130 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2131 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2132 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
2133 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
2134 		nreg++, nasgn++;
2135 
2136 		/* Video memory */
2137 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2138 		    (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc);
2139 		regs[nreg].pci_phys_low =
2140 		    assigned[nasgn].pci_phys_low = 0xa0000;
2141 		regs[nreg].pci_size_low =
2142 		    assigned[nasgn].pci_size_low = 0x20000;
2143 		nreg++, nasgn++;
2144 	}
2145 
2146 	/* add the hard-decode, aliased address spaces for 8514 */
2147 	if ((baseclass == PCI_CLASS_DISPLAY) &&
2148 	    (subclass == PCI_DISPLAY_VGA) &&
2149 	    (progclass & PCI_DISPLAY_IF_8514)) {
2150 
2151 		/* hard decode 0x2e8 */
2152 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2153 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2154 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
2155 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
2156 		nreg++, nasgn++;
2157 
2158 		/* hard decode 0x2ea-0x2ef */
2159 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2160 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2161 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
2162 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
2163 		nreg++, nasgn++;
2164 	}
2165 
2166 done:
2167 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
2168 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
2169 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2170 	    "assigned-addresses",
2171 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
2172 
2173 	return (reprogram);
2174 }
2175 
2176 static void
2177 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2178     int pciex)
2179 {
2180 	char *dev_type;
2181 	int i;
2182 	uint_t val, io_range[2], mem_range[2], pmem_range[2];
2183 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2184 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2185 	uchar_t progclass;
2186 
2187 	ASSERT(secbus <= subbus);
2188 
2189 	/*
2190 	 * Check if it's a subtractive PPB.
2191 	 */
2192 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2193 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
2194 		pci_bus_res[secbus].subtractive = B_TRUE;
2195 
2196 	/*
2197 	 * Some BIOSes lie about max pci busses, we allow for
2198 	 * such mistakes here
2199 	 */
2200 	if (subbus > pci_bios_nbus) {
2201 		pci_bios_nbus = subbus;
2202 		alloc_res_array();
2203 	}
2204 
2205 	ASSERT(pci_bus_res[secbus].dip == NULL);
2206 	pci_bus_res[secbus].dip = dip;
2207 	pci_bus_res[secbus].par_bus = bus;
2208 
2209 	dev_type = pciex ? "pciex" : "pci";
2210 
2211 	/* setup bus number hierarchy */
2212 	pci_bus_res[secbus].sub_bus = subbus;
2213 	/*
2214 	 * Keep track of the largest subordinate bus number (this is essential
2215 	 * for peer busses because there is no other way of determining its
2216 	 * subordinate bus number).
2217 	 */
2218 	if (subbus > pci_bus_res[bus].sub_bus)
2219 		pci_bus_res[bus].sub_bus = subbus;
2220 	/*
2221 	 * Loop through subordinate busses, initializing their parent bus
2222 	 * field to this bridge's parent.  The subordinate busses' parent
2223 	 * fields may very well be further refined later, as child bridges
2224 	 * are enumerated.  (The value is to note that the subordinate busses
2225 	 * are not peer busses by changing their par_bus fields to anything
2226 	 * other than -1.)
2227 	 */
2228 	for (i = secbus + 1; i <= subbus; i++)
2229 		pci_bus_res[i].par_bus = bus;
2230 
2231 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2232 	    "device_type", dev_type);
2233 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2234 	    "#address-cells", 3);
2235 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2236 	    "#size-cells", 2);
2237 
2238 	/*
2239 	 * According to PPB spec, the base register should be programmed
2240 	 * with a value bigger than the limit register when there are
2241 	 * no resources available. This applies to io, memory, and
2242 	 * prefetchable memory.
2243 	 */
2244 
2245 	/*
2246 	 * io range
2247 	 * We determine i/o windows that are left unconfigured by BIOS
2248 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
2249 	 * If it is unset, we disable i/o and mark it for reconfiguration in
2250 	 * later passes by setting the base > limit
2251 	 */
2252 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2253 	if (val & PCI_COMM_IO) {
2254 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2255 		io_range[0] = ((val & 0xf0) << 8);
2256 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2257 		io_range[1]  = ((val & 0xf0) << 8) | 0xFFF;
2258 	} else {
2259 		io_range[0] = 0x9fff;
2260 		io_range[1] = 0x1000;
2261 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2262 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
2263 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2264 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
2265 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2266 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2267 	}
2268 
2269 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
2270 		memlist_insert(&pci_bus_res[secbus].io_ports,
2271 		    (uint64_t)io_range[0],
2272 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2273 		memlist_insert(&pci_bus_res[bus].io_ports_used,
2274 		    (uint64_t)io_range[0],
2275 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2276 		if (pci_bus_res[bus].io_ports != NULL) {
2277 			(void) memlist_remove(&pci_bus_res[bus].io_ports,
2278 			    (uint64_t)io_range[0],
2279 			    (uint64_t)(io_range[1] - io_range[0] + 1));
2280 		}
2281 		dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x",
2282 		    secbus, io_range[0], io_range[1]);
2283 		/* if 32-bit supported, make sure upper bits are not set */
2284 		if ((val & 0xf) == 1 &&
2285 		    pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
2286 			cmn_err(CE_NOTE, "unsupported 32-bit IO address on"
2287 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2288 		}
2289 	}
2290 
2291 	/* mem range */
2292 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2293 	mem_range[0] = ((val & 0xFFF0) << 16);
2294 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2295 	mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2296 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
2297 		memlist_insert(&pci_bus_res[secbus].mem_space,
2298 		    (uint64_t)mem_range[0],
2299 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2300 		memlist_insert(&pci_bus_res[bus].mem_space_used,
2301 		    (uint64_t)mem_range[0],
2302 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2303 		/* remove from parent resouce list */
2304 		if (pci_bus_res[bus].mem_space != NULL) {
2305 			(void) memlist_remove(&pci_bus_res[bus].mem_space,
2306 			    (uint64_t)mem_range[0],
2307 			    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2308 		}
2309 		dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x",
2310 		    secbus, mem_range[0], mem_range[1]);
2311 	}
2312 
2313 	/* prefetchable memory range */
2314 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2315 	pmem_range[0] = ((val & 0xFFF0) << 16);
2316 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2317 	pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2318 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
2319 		memlist_insert(&pci_bus_res[secbus].pmem_space,
2320 		    (uint64_t)pmem_range[0],
2321 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2322 		memlist_insert(&pci_bus_res[bus].pmem_space_used,
2323 		    (uint64_t)pmem_range[0],
2324 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2325 		if (pci_bus_res[bus].pmem_space != NULL) {
2326 			(void) memlist_remove(&pci_bus_res[bus].pmem_space,
2327 			    (uint64_t)pmem_range[0],
2328 			    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2329 		}
2330 		dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x",
2331 		    secbus, pmem_range[0], pmem_range[1]);
2332 		/* if 64-bit supported, make sure upper bits are not set */
2333 		if ((val & 0xf) == 1 &&
2334 		    pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
2335 			cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on"
2336 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2337 		}
2338 	}
2339 
2340 	add_bus_range_prop(secbus);
2341 	add_ppb_ranges_prop(secbus);
2342 }
2343 
2344 extern const struct pci_class_strings_s class_pci[];
2345 extern int class_pci_items;
2346 
2347 static void
2348 add_model_prop(dev_info_t *dip, uint_t classcode)
2349 {
2350 	const char *desc;
2351 	int i;
2352 	uchar_t baseclass = classcode >> 16;
2353 	uchar_t subclass = (classcode >> 8) & 0xff;
2354 	uchar_t progclass = classcode & 0xff;
2355 
2356 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
2357 		desc = "IDE controller";
2358 	} else {
2359 		for (desc = 0, i = 0; i < class_pci_items; i++) {
2360 			if ((baseclass == class_pci[i].base_class) &&
2361 			    (subclass == class_pci[i].sub_class) &&
2362 			    (progclass == class_pci[i].prog_class)) {
2363 				desc = class_pci[i].actual_desc;
2364 				break;
2365 			}
2366 		}
2367 		if (i == class_pci_items)
2368 			desc = "Unknown class of pci/pnpbios device";
2369 	}
2370 
2371 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2372 	    (char *)desc);
2373 }
2374 
2375 static void
2376 add_bus_range_prop(int bus)
2377 {
2378 	int bus_range[2];
2379 
2380 	if (pci_bus_res[bus].dip == NULL)
2381 		return;
2382 	bus_range[0] = bus;
2383 	bus_range[1] = pci_bus_res[bus].sub_bus;
2384 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2385 	    "bus-range", (int *)bus_range, 2);
2386 }
2387 
2388 /*
2389  * Add slot-names property for any named pci hot-plug slots
2390  */
2391 static void
2392 add_bus_slot_names_prop(int bus)
2393 {
2394 	char slotprop[256];
2395 	int len;
2396 
2397 	if (pci_bus_res[bus].dip != NULL) {
2398 		/* simply return if the property is already defined */
2399 		if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
2400 		    DDI_PROP_DONTPASS, "slot-names"))
2401 			return;
2402 	}
2403 
2404 	len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
2405 	if (len > 0) {
2406 		/*
2407 		 * Only create a peer bus node if this bus may be a peer bus.
2408 		 * It may be a peer bus if the dip is NULL and if par_bus is
2409 		 * -1 (par_bus is -1 if this bus was not found to be
2410 		 * subordinate to any PCI-PCI bridge).
2411 		 * If it's not a peer bus, then the ACPI BBN-handling code
2412 		 * will remove it later.
2413 		 */
2414 		if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
2415 		    pci_bus_res[bus].dip == NULL) {
2416 
2417 			create_root_bus_dip(bus);
2418 		}
2419 		if (pci_bus_res[bus].dip != NULL) {
2420 			ASSERT((len % sizeof (int)) == 0);
2421 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
2422 			    pci_bus_res[bus].dip, "slot-names",
2423 			    (int *)slotprop, len / sizeof (int));
2424 		} else {
2425 			cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
2426 			    "IRQ routing table; Not adding slot-names "
2427 			    "property for incorrect bus %d", bus);
2428 		}
2429 	}
2430 }
2431 
2432 static int
2433 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type)
2434 {
2435 	if (entry == NULL)
2436 		return (0);
2437 
2438 	/* assume 32-bit addresses */
2439 	rp->child_high = rp->parent_high = type;
2440 	rp->child_mid = rp->parent_mid = 0;
2441 	rp->child_low = rp->parent_low = (uint32_t)entry->address;
2442 	rp->size_high = 0;
2443 	rp->size_low = (uint32_t)entry->size;
2444 	return (1);
2445 }
2446 
2447 static void
2448 add_ppb_ranges_prop(int bus)
2449 {
2450 	int i = 0;
2451 	ppb_ranges_t *rp;
2452 
2453 	rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP);
2454 
2455 	i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports,
2456 	    PCI_ADDR_IO | PCI_REG_REL_M);
2457 	i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space,
2458 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
2459 	i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space,
2460 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
2461 
2462 	if (i != 0)
2463 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
2464 		    pci_bus_res[bus].dip, "ranges", (int *)rp,
2465 		    i * sizeof (ppb_ranges_t) / sizeof (int));
2466 	kmem_free(rp, 3 * sizeof (*rp));
2467 }
2468 
2469 static int
2470 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type)
2471 {
2472 	int i = 0;
2473 
2474 	while (list) {
2475 		/* assume 32-bit addresses */
2476 		sp->pci_phys_hi = type;
2477 		sp->pci_phys_mid = 0;
2478 		sp->pci_phys_low = (uint32_t)list->address;
2479 		sp->pci_size_hi = 0;
2480 		sp->pci_size_low = (uint32_t)list->size;
2481 
2482 		list = list->next;
2483 		sp++, i++;
2484 	}
2485 	return (i);
2486 }
2487 
2488 static void
2489 add_bus_available_prop(int bus)
2490 {
2491 	int i, count;
2492 	struct pci_phys_spec *sp;
2493 
2494 	count = memlist_count(pci_bus_res[bus].io_ports) +
2495 	    memlist_count(pci_bus_res[bus].mem_space) +
2496 	    memlist_count(pci_bus_res[bus].pmem_space);
2497 
2498 	if (count == 0)		/* nothing available */
2499 		return;
2500 
2501 	sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP);
2502 	i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports,
2503 	    PCI_ADDR_IO | PCI_REG_REL_M);
2504 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space,
2505 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
2506 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space,
2507 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
2508 	ASSERT(i == count);
2509 
2510 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2511 	    "available", (int *)sp,
2512 	    i * sizeof (struct pci_phys_spec) / sizeof (int));
2513 	kmem_free(sp, count * sizeof (*sp));
2514 }
2515 
2516 static void
2517 alloc_res_array(void)
2518 {
2519 	static int array_max = 0;
2520 	int old_max;
2521 	void *old_res;
2522 
2523 	if (array_max > pci_bios_nbus + 1)
2524 		return;	/* array is big enough */
2525 
2526 	old_max = array_max;
2527 	old_res = pci_bus_res;
2528 
2529 	if (array_max == 0)
2530 		array_max = 16;	/* start with a reasonable number */
2531 
2532 	while (array_max < pci_bios_nbus + 1)
2533 		array_max <<= 1;
2534 	pci_bus_res = (struct pci_bus_resource *)kmem_zalloc(
2535 	    array_max * sizeof (struct pci_bus_resource), KM_SLEEP);
2536 
2537 	if (old_res) {	/* copy content and free old array */
2538 		bcopy(old_res, pci_bus_res,
2539 		    old_max * sizeof (struct pci_bus_resource));
2540 		kmem_free(old_res, old_max * sizeof (struct pci_bus_resource));
2541 	}
2542 }
2543 
2544 static void
2545 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
2546     ushort_t deviceid)
2547 {
2548 	static dev_info_t *ioapicsnode = NULL;
2549 	static int numioapics = 0;
2550 	dev_info_t *ioapic_node;
2551 	uint64_t physaddr;
2552 	uint32_t lobase, hibase = 0;
2553 
2554 	/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
2555 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
2556 
2557 	/* We (and the rest of the world) only support memory-mapped IOAPICs */
2558 	if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM)
2559 		return;
2560 
2561 	if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL)
2562 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
2563 
2564 	lobase &= PCI_BASE_M_ADDR_M;
2565 
2566 	physaddr = (((uint64_t)hibase) << 32) | lobase;
2567 
2568 	/*
2569 	 * Create a nexus node for all IOAPICs under the root node.
2570 	 */
2571 	if (ioapicsnode == NULL) {
2572 		if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME,
2573 		    (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) {
2574 			return;
2575 		}
2576 		(void) ndi_devi_online(ioapicsnode, 0);
2577 	}
2578 
2579 	/*
2580 	 * Create a child node for this IOAPIC
2581 	 */
2582 	ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME,
2583 	    DEVI_SID_NODEID, numioapics++);
2584 	if (ioapic_node == NULL) {
2585 		return;
2586 	}
2587 
2588 	/* Vendor and Device ID */
2589 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2590 	    IOAPICS_PROP_VENID, vendorid);
2591 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2592 	    IOAPICS_PROP_DEVID, deviceid);
2593 
2594 	/* device_type */
2595 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node,
2596 	    "device_type", IOAPICS_DEV_TYPE);
2597 
2598 	/* reg */
2599 	(void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node,
2600 	    "reg", physaddr);
2601 }
2602 
2603 /*
2604  * NOTE: For PCIe slots, the name is generated from the slot number
2605  * information obtained from Slot Capabilities register.
2606  * For non-PCIe slots, it is generated based on the slot number
2607  * information in the PCI IRQ table.
2608  */
2609 static void
2610 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num)
2611 {
2612 	char slotprop[256];
2613 	int len;
2614 
2615 	bzero(slotprop, sizeof (slotprop));
2616 
2617 	/* set mask to 1 as there is only one slot (i.e dev 0) */
2618 	*(uint32_t *)slotprop = 1;
2619 	len = 4;
2620 	(void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d",
2621 	    slot_num);
2622 	len += strlen(slotprop + len) + 1;
2623 	len += len % 4;
2624 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names",
2625 	    (int *)slotprop, len / sizeof (int));
2626 }
2627