1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sysmacros.h> 29 #include <sys/sunndi.h> 30 #include <sys/pci.h> 31 #include <sys/pci_impl.h> 32 #include <sys/pci_cfgspace.h> 33 #include <sys/memlist.h> 34 #include <sys/bootconf.h> 35 #include <io/pci/mps_table.h> 36 #include <sys/pci_cfgspace.h> 37 #include <sys/pci_cfgspace_impl.h> 38 #include <sys/psw.h> 39 #include "../../../../common/pci/pci_strings.h" 40 #include <sys/apic.h> 41 #include <io/pciex/pcie_nvidia.h> 42 #include <sys/hotplug/pci/pciehpc_acpi.h> 43 #include <sys/acpi/acpi.h> 44 #include <sys/acpica.h> 45 #include <sys/intel_iommu.h> 46 #include <sys/iommulib.h> 47 #include <sys/devcache.h> 48 49 #define pci_getb (*pci_getb_func) 50 #define pci_getw (*pci_getw_func) 51 #define pci_getl (*pci_getl_func) 52 #define pci_putb (*pci_putb_func) 53 #define pci_putw (*pci_putw_func) 54 #define pci_putl (*pci_putl_func) 55 #define dcmn_err if (pci_boot_debug) cmn_err 56 57 #define CONFIG_INFO 0 58 #define CONFIG_UPDATE 1 59 #define CONFIG_NEW 2 60 #define CONFIG_FIX 3 61 #define COMPAT_BUFSIZE 512 62 63 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 64 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 65 /* round down to nearest power of two */ 66 #define P2LE(align) \ 67 { \ 68 int i = 0; \ 69 while (align >>= 1) \ 70 i ++; \ 71 align = 1 << i; \ 72 } \ 73 74 /* for is_vga and list_is_vga_only */ 75 76 enum io_mem { 77 IO, 78 MEM 79 }; 80 81 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 82 #define LPC_IO_CONTROL_REG_1 0x40 83 #define AMD8111_ENABLENMI (uint8_t)0x80 84 #define DEVID_AMD8111_LPC 0x7468 85 86 struct pci_fixundo { 87 uint8_t bus; 88 uint8_t dev; 89 uint8_t fn; 90 void (*undofn)(uint8_t, uint8_t, uint8_t); 91 struct pci_fixundo *next; 92 }; 93 94 struct pci_devfunc { 95 struct pci_devfunc *next; 96 dev_info_t *dip; 97 uchar_t dev; 98 uchar_t func; 99 boolean_t reprogram; /* this device needs to be reprogrammed */ 100 }; 101 102 extern int pseudo_isa; 103 extern int pci_bios_maxbus; 104 static uchar_t max_dev_pci = 32; /* PCI standard */ 105 int pci_boot_debug = 0; 106 extern struct memlist *find_bus_res(int, int); 107 static struct pci_fixundo *undolist = NULL; 108 static int num_root_bus = 0; /* count of root buses */ 109 extern volatile int acpi_resource_discovery; 110 111 /* 112 * Module prototypes 113 */ 114 static void enumerate_bus_devs(uchar_t bus, int config_op); 115 static void create_root_bus_dip(uchar_t bus); 116 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 117 ushort_t, int); 118 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 119 ushort_t, ushort_t, uchar_t, uint_t, int); 120 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 121 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 122 ushort_t); 123 static void add_model_prop(dev_info_t *, uint_t); 124 static void add_bus_range_prop(int); 125 static void add_bus_slot_names_prop(int); 126 static void add_ranges_prop(int, int); 127 static void add_bus_available_prop(int); 128 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 129 static void fix_ppb_res(uchar_t, boolean_t); 130 static void alloc_res_array(); 131 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 132 ushort_t deviceid); 133 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 134 static void populate_bus_res(uchar_t bus); 135 static void memlist_remove_list(struct memlist **list, 136 struct memlist *remove_list); 137 138 static void pci_scan_bbn(void); 139 static int pci_unitaddr_cache_valid(void); 140 static int pci_bus_unitaddr(int); 141 static void pci_unitaddr_cache_create(void); 142 143 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); 144 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); 145 static void pci_cache_free_list(nvf_handle_t); 146 147 extern int pci_slot_names_prop(int, char *, int); 148 149 /* set non-zero to force PCI peer-bus renumbering */ 150 int pci_bus_always_renumber = 0; 151 152 /* 153 * used to register ISA resource usage which must not be made 154 * "available" from other PCI node' resource maps 155 */ 156 static struct { 157 struct memlist *io_used; 158 struct memlist *mem_used; 159 } isa_res; 160 161 /* 162 * PCI unit-address cache management 163 */ 164 static nvf_ops_t pci_unitaddr_cache_ops = { 165 "/etc/devices/pci_unitaddr_persistent", /* path to cache */ 166 pci_cache_unpack_nvlist, /* read in nvlist form */ 167 pci_cache_pack_nvlist, /* convert to nvlist form */ 168 pci_cache_free_list, /* free data list */ 169 NULL /* write complete callback */ 170 }; 171 172 typedef struct { 173 list_node_t pua_nodes; 174 int pua_index; 175 int pua_addr; 176 } pua_node_t; 177 178 nvf_handle_t puafd_handle; 179 int pua_cache_valid = 0; 180 181 182 /*ARGSUSED*/ 183 static ACPI_STATUS 184 pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv) 185 { 186 ACPI_BUFFER rb; 187 ACPI_OBJECT ro; 188 ACPI_DEVICE_INFO *adi; 189 190 /* 191 * Use AcpiGetObjectInfo() to find the device _HID 192 * If not a PCI root-bus, ignore this device and continue 193 * the walk 194 */ 195 196 rb.Length = ACPI_ALLOCATE_BUFFER; 197 if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &rb))) 198 return (AE_OK); 199 200 adi = rb.Pointer; 201 if (!(adi->Valid & ACPI_VALID_HID)) { 202 AcpiOsFree(adi); 203 return (AE_OK); 204 } 205 206 if (strncmp(adi->HardwareId.Value, PCI_ROOT_HID_STRING, 207 sizeof (PCI_ROOT_HID_STRING)) && 208 strncmp(adi->HardwareId.Value, PCI_EXPRESS_ROOT_HID_STRING, 209 sizeof (PCI_EXPRESS_ROOT_HID_STRING))) { 210 AcpiOsFree(adi); 211 return (AE_OK); 212 } 213 214 AcpiOsFree(adi); 215 216 /* 217 * XXX: ancient Big Bear broken _BBN will result in two 218 * bus 0 _BBNs being found, so we need to handle duplicate 219 * bus 0 gracefully. However, broken _BBN does not 220 * hide a childless root-bridge so no need to work-around it 221 * here 222 */ 223 rb.Pointer = &ro; 224 rb.Length = sizeof (ro); 225 if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN", 226 NULL, &rb, ACPI_TYPE_INTEGER))) { 227 /* PCI with _BBN, process it, go no deeper */ 228 if (pci_bus_res[ro.Integer.Value].par_bus == (uchar_t)-1 && 229 pci_bus_res[ro.Integer.Value].dip == NULL) 230 create_root_bus_dip((uchar_t)ro.Integer.Value); 231 return (AE_CTRL_DEPTH); 232 } 233 234 /* PCI and no _BBN, continue walk */ 235 return (AE_OK); 236 } 237 238 /* 239 * Scan the ACPI namespace for all top-level instances of _BBN 240 * in order to discover childless root-bridges (which enumeration 241 * may not find; root-bridges are inferred by the existence of 242 * children). This scan should find all root-bridges that have 243 * been enumerated, and any childless root-bridges not enumerated. 244 * Root-bridge for bus 0 may not have a _BBN object. 245 */ 246 static void 247 pci_scan_bbn() 248 { 249 void *rv; 250 251 (void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv); 252 } 253 254 static void 255 pci_unitaddr_cache_init(void) 256 { 257 258 puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); 259 ASSERT(puafd_handle); 260 261 list_create(nvf_list(puafd_handle), sizeof (pua_node_t), 262 offsetof(pua_node_t, pua_nodes)); 263 264 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 265 (void) nvf_read_file(puafd_handle); 266 rw_exit(nvf_lock(puafd_handle)); 267 } 268 269 /* 270 * Format of /etc/devices/pci_unitaddr_persistent: 271 * 272 * The persistent record of unit-address assignments contains 273 * a list of name/value pairs, where name is a string representation 274 * of the "index value" of the PCI root-bus and the value is 275 * the assigned unit-address. 276 * 277 * The "index value" is simply the zero-based index of the PCI 278 * root-buses ordered by physical bus number; first PCI bus is 0, 279 * second is 1, and so on. 280 */ 281 282 /*ARGSUSED*/ 283 static int 284 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) 285 { 286 long index; 287 int32_t value; 288 nvpair_t *np; 289 pua_node_t *node; 290 291 np = NULL; 292 while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { 293 /* name of nvpair is index value */ 294 if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) 295 continue; 296 297 if (nvpair_value_int32(np, &value) != 0) 298 continue; 299 300 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 301 node->pua_index = index; 302 node->pua_addr = value; 303 list_insert_tail(nvf_list(hdl), node); 304 } 305 306 pua_cache_valid = 1; 307 return (DDI_SUCCESS); 308 } 309 310 static int 311 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) 312 { 313 int rval; 314 nvlist_t *nvl, *sub_nvl; 315 list_t *listp; 316 pua_node_t *pua; 317 char buf[13]; 318 319 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 320 321 rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 322 if (rval != DDI_SUCCESS) { 323 nvf_error("%s: nvlist alloc error %d\n", 324 nvf_cache_name(hdl), rval); 325 return (DDI_FAILURE); 326 } 327 328 sub_nvl = NULL; 329 rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); 330 if (rval != DDI_SUCCESS) 331 goto error; 332 333 listp = nvf_list(hdl); 334 for (pua = list_head(listp); pua != NULL; 335 pua = list_next(listp, pua)) { 336 (void) snprintf(buf, sizeof (buf), "%d", pua->pua_index); 337 rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); 338 if (rval != DDI_SUCCESS) 339 goto error; 340 } 341 342 rval = nvlist_add_nvlist(nvl, "table", sub_nvl); 343 if (rval != DDI_SUCCESS) 344 goto error; 345 nvlist_free(sub_nvl); 346 347 *ret_nvl = nvl; 348 return (DDI_SUCCESS); 349 350 error: 351 if (sub_nvl) 352 nvlist_free(sub_nvl); 353 ASSERT(nvl); 354 nvlist_free(nvl); 355 *ret_nvl = NULL; 356 return (DDI_FAILURE); 357 } 358 359 static void 360 pci_cache_free_list(nvf_handle_t hdl) 361 { 362 list_t *listp; 363 pua_node_t *pua; 364 365 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 366 367 listp = nvf_list(hdl); 368 for (pua = list_head(listp); pua != NULL; 369 pua = list_next(listp, pua)) { 370 list_remove(listp, pua); 371 kmem_free(pua, sizeof (pua_node_t)); 372 } 373 } 374 375 376 static int 377 pci_unitaddr_cache_valid(void) 378 { 379 380 /* read only, no need for rw lock */ 381 return (pua_cache_valid); 382 } 383 384 385 static int 386 pci_bus_unitaddr(int index) 387 { 388 pua_node_t *pua; 389 list_t *listp; 390 int addr; 391 392 rw_enter(nvf_lock(puafd_handle), RW_READER); 393 394 addr = -1; /* default return if no match */ 395 listp = nvf_list(puafd_handle); 396 for (pua = list_head(listp); pua != NULL; 397 pua = list_next(listp, pua)) { 398 if (pua->pua_index == index) { 399 addr = pua->pua_addr; 400 break; 401 } 402 } 403 404 rw_exit(nvf_lock(puafd_handle)); 405 return (addr); 406 } 407 408 static void 409 pci_unitaddr_cache_create(void) 410 { 411 int i, index; 412 pua_node_t *node; 413 list_t *listp; 414 415 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 416 417 index = 0; 418 listp = nvf_list(puafd_handle); 419 for (i = 0; i <= pci_bios_maxbus; i++) { 420 /* skip non-root (peer) PCI busses */ 421 if ((pci_bus_res[i].par_bus != (uchar_t)-1) || 422 (pci_bus_res[i].dip == NULL)) 423 continue; 424 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 425 node->pua_index = index++; 426 node->pua_addr = pci_bus_res[i].root_addr; 427 list_insert_tail(listp, node); 428 } 429 430 (void) nvf_mark_dirty(puafd_handle); 431 rw_exit(nvf_lock(puafd_handle)); 432 nvf_wake_daemon(); 433 } 434 435 436 /* 437 * Enumerate all PCI devices 438 */ 439 void 440 pci_setup_tree(void) 441 { 442 uint_t i, root_bus_addr = 0; 443 444 alloc_res_array(); 445 for (i = 0; i <= pci_bios_maxbus; i++) { 446 pci_bus_res[i].par_bus = (uchar_t)-1; 447 pci_bus_res[i].root_addr = (uchar_t)-1; 448 pci_bus_res[i].sub_bus = i; 449 } 450 451 pci_bus_res[0].root_addr = root_bus_addr++; 452 create_root_bus_dip(0); 453 enumerate_bus_devs(0, CONFIG_INFO); 454 455 /* 456 * Now enumerate peer busses 457 * 458 * We loop till pci_bios_maxbus. On most systems, there is 459 * one more bus at the high end, which implements the ISA 460 * compatibility bus. We don't care about that. 461 * 462 * Note: In the old (bootconf) enumeration, the peer bus 463 * address did not use the bus number, and there were 464 * too many peer busses created. The root_bus_addr is 465 * used to maintain the old peer bus address assignment. 466 * However, we stop enumerating phantom peers with no 467 * device below. 468 */ 469 for (i = 1; i <= pci_bios_maxbus; i++) { 470 if (pci_bus_res[i].dip == NULL) { 471 pci_bus_res[i].root_addr = root_bus_addr++; 472 } 473 enumerate_bus_devs(i, CONFIG_INFO); 474 475 /* add slot-names property for named pci hot-plug slots */ 476 add_bus_slot_names_prop(i); 477 } 478 479 } 480 481 /* 482 * >0 = present, 0 = not present, <0 = error 483 */ 484 static int 485 pci_bbn_present(int bus) 486 { 487 ACPI_HANDLE hdl; 488 int rv; 489 490 /* no dip means no _BBN */ 491 if (pci_bus_res[bus].dip == NULL) 492 return (0); 493 494 rv = -1; /* default return value in case of error below */ 495 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 496 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 497 case AE_OK: 498 rv = 1; 499 break; 500 case AE_NOT_FOUND: 501 rv = 0; 502 break; 503 default: 504 break; 505 } 506 } 507 508 return (rv); 509 } 510 511 /* 512 * Return non-zero if any PCI bus in the system has an associated 513 * _BBN object, 0 otherwise. 514 */ 515 static int 516 pci_roots_have_bbn(void) 517 { 518 int i; 519 520 /* 521 * Scan the PCI busses and look for at least 1 _BBN 522 */ 523 for (i = 0; i <= pci_bios_maxbus; i++) { 524 /* skip non-root (peer) PCI busses */ 525 if (pci_bus_res[i].par_bus != (uchar_t)-1) 526 continue; 527 528 if (pci_bbn_present(i) > 0) 529 return (1); 530 } 531 return (0); 532 533 } 534 535 /* 536 * return non-zero if the machine is one on which we renumber 537 * the internal pci unit-addresses 538 */ 539 static int 540 pci_bus_renumber() 541 { 542 ACPI_TABLE_HEADER *fadt; 543 544 if (pci_bus_always_renumber) 545 return (1); 546 547 /* get the FADT */ 548 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 549 AE_OK) 550 return (0); 551 552 /* compare OEM Table ID to "SUNm31" */ 553 if (strncmp("SUNm31", fadt->OemId, 6)) 554 return (0); 555 else 556 return (1); 557 } 558 559 /* 560 * Initial enumeration of the physical PCI bus hierarchy can 561 * leave 'gaps' in the order of peer PCI bus unit-addresses. 562 * Systems with more than one peer PCI bus *must* have an ACPI 563 * _BBN object associated with each peer bus; use the presence 564 * of this object to remove gaps in the numbering of the peer 565 * PCI bus unit-addresses - only peer busses with an associated 566 * _BBN are counted. 567 */ 568 static void 569 pci_renumber_root_busses(void) 570 { 571 int pci_regs[] = {0, 0, 0}; 572 int i, root_addr = 0; 573 574 /* 575 * Currently, we only enable the re-numbering on specific 576 * Sun machines; this is a work-around for the more complicated 577 * issue of upgrade changing physical device paths 578 */ 579 if (!pci_bus_renumber()) 580 return; 581 582 /* 583 * If we find no _BBN objects at all, we either don't need 584 * to do anything or can't do anything anyway 585 */ 586 if (!pci_roots_have_bbn()) 587 return; 588 589 for (i = 0; i <= pci_bios_maxbus; i++) { 590 /* skip non-root (peer) PCI busses */ 591 if (pci_bus_res[i].par_bus != (uchar_t)-1) 592 continue; 593 594 if (pci_bbn_present(i) < 1) { 595 pci_bus_res[i].root_addr = (uchar_t)-1; 596 continue; 597 } 598 599 ASSERT(pci_bus_res[i].dip != NULL); 600 if (pci_bus_res[i].root_addr != root_addr) { 601 /* update reg property for node */ 602 pci_bus_res[i].root_addr = root_addr; 603 pci_regs[0] = pci_bus_res[i].root_addr; 604 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 605 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 606 } 607 root_addr++; 608 } 609 } 610 611 void 612 pci_register_isa_resources(int type, uint32_t base, uint32_t size) 613 { 614 (void) memlist_insert( 615 (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 616 base, size); 617 } 618 619 /* 620 * Remove the resources which are already used by devices under a subtractive 621 * bridge from the bus's resources lists, because they're not available, and 622 * shouldn't be allocated to other buses. This is necessary because tracking 623 * resources for subtractive bridges is not complete. (Subtractive bridges only 624 * track some of their claimed resources, not "the rest of the address space" as 625 * they should, so that allocation to peer non-subtractive PPBs is easier. We 626 * need a fully-capable global resource allocator). 627 */ 628 static void 629 remove_subtractive_res() 630 { 631 int i, j; 632 struct memlist *list; 633 634 for (i = 0; i <= pci_bios_maxbus; i++) { 635 if (pci_bus_res[i].subtractive) { 636 /* remove used io ports */ 637 list = pci_bus_res[i].io_used; 638 while (list) { 639 for (j = 0; j <= pci_bios_maxbus; j++) 640 (void) memlist_remove( 641 &pci_bus_res[j].io_avail, 642 list->address, list->size); 643 list = list->next; 644 } 645 /* remove used mem resource */ 646 list = pci_bus_res[i].mem_used; 647 while (list) { 648 for (j = 0; j <= pci_bios_maxbus; j++) { 649 (void) memlist_remove( 650 &pci_bus_res[j].mem_avail, 651 list->address, list->size); 652 (void) memlist_remove( 653 &pci_bus_res[j].pmem_avail, 654 list->address, list->size); 655 } 656 list = list->next; 657 } 658 /* remove used prefetchable mem resource */ 659 list = pci_bus_res[i].pmem_used; 660 while (list) { 661 for (j = 0; j <= pci_bios_maxbus; j++) { 662 (void) memlist_remove( 663 &pci_bus_res[j].pmem_avail, 664 list->address, list->size); 665 (void) memlist_remove( 666 &pci_bus_res[j].mem_avail, 667 list->address, list->size); 668 } 669 list = list->next; 670 } 671 } 672 } 673 } 674 675 /* 676 * Set up (or complete the setup of) the bus_avail resource list 677 */ 678 static void 679 setup_bus_res(int bus) 680 { 681 uchar_t par_bus; 682 683 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 684 return; 685 686 /* 687 * Set up bus_avail if not already filled in by populate_bus_res() 688 */ 689 if (pci_bus_res[bus].bus_avail == NULL) { 690 ASSERT(pci_bus_res[bus].sub_bus >= bus); 691 memlist_insert(&pci_bus_res[bus].bus_avail, bus, 692 pci_bus_res[bus].sub_bus - bus + 1); 693 } 694 695 ASSERT(pci_bus_res[bus].bus_avail != NULL); 696 697 /* 698 * Remove resources from parent bus node if this is not a 699 * root bus. 700 */ 701 par_bus = pci_bus_res[bus].par_bus; 702 if (par_bus != (uchar_t)-1) { 703 ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 704 memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 705 pci_bus_res[bus].bus_avail); 706 } 707 708 /* remove self from bus_avail */; 709 (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 710 } 711 712 static uint64_t 713 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 714 { 715 uint64_t addr = 0; 716 uchar_t res_bus; 717 718 /* 719 * Skip root(peer) buses in multiple-root-bus systems when 720 * ACPI resource discovery was not successfully done. 721 */ 722 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 723 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 724 return (0); 725 726 res_bus = parbus; 727 while (pci_bus_res[res_bus].subtractive) { 728 if (pci_bus_res[res_bus].io_avail) 729 break; 730 res_bus = pci_bus_res[res_bus].par_bus; 731 if (res_bus == (uchar_t)-1) 732 break; /* root bus already */ 733 } 734 735 if (pci_bus_res[res_bus].io_avail) { 736 addr = memlist_find(&pci_bus_res[res_bus].io_avail, 737 size, align); 738 if (addr) { 739 memlist_insert(&pci_bus_res[res_bus].io_used, 740 addr, size); 741 742 /* free the old resource */ 743 memlist_free_all(&pci_bus_res[bus].io_avail); 744 memlist_free_all(&pci_bus_res[bus].io_used); 745 746 /* add the new resource */ 747 memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 748 } 749 } 750 751 return (addr); 752 } 753 754 static uint64_t 755 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 756 { 757 uint64_t addr = 0; 758 uchar_t res_bus; 759 760 /* 761 * Skip root(peer) buses in multiple-root-bus systems when 762 * ACPI resource discovery was not successfully done. 763 */ 764 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 765 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 766 return (0); 767 768 res_bus = parbus; 769 while (pci_bus_res[res_bus].subtractive) { 770 if (pci_bus_res[res_bus].mem_avail) 771 break; 772 res_bus = pci_bus_res[res_bus].par_bus; 773 if (res_bus == (uchar_t)-1) 774 break; /* root bus already */ 775 } 776 777 if (pci_bus_res[res_bus].mem_avail) { 778 addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 779 size, align); 780 if (addr) { 781 memlist_insert(&pci_bus_res[res_bus].mem_used, 782 addr, size); 783 (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 784 addr, size); 785 786 /* free the old resource */ 787 memlist_free_all(&pci_bus_res[bus].mem_avail); 788 memlist_free_all(&pci_bus_res[bus].mem_used); 789 790 /* add the new resource */ 791 memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 792 } 793 } 794 795 return (addr); 796 } 797 798 /* 799 * given a cap_id, return its cap_id location in config space 800 */ 801 static int 802 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 803 { 804 uint8_t curcap, cap_id_loc; 805 uint16_t status; 806 int location = -1; 807 808 /* 809 * Need to check the Status register for ECP support first. 810 * Also please note that for type 1 devices, the 811 * offset could change. Should support type 1 next. 812 */ 813 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 814 if (!(status & PCI_STAT_CAP)) { 815 return (-1); 816 } 817 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 818 819 /* Walk the list of capabilities */ 820 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 821 curcap = pci_getb(bus, dev, func, cap_id_loc); 822 823 if (curcap == cap_id) { 824 location = cap_id_loc; 825 break; 826 } 827 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 828 } 829 return (location); 830 } 831 832 /* 833 * Does this resource element live in the legacy VGA range? 834 */ 835 836 int 837 is_vga(struct memlist *elem, enum io_mem io) 838 { 839 840 if (io == IO) { 841 if ((elem->address == 0x3b0 && elem->size == 0xc) || 842 (elem->address == 0x3c0 && elem->size == 0x20)) 843 return (1); 844 } else { 845 if (elem->address == 0xa0000 && elem->size == 0x20000) 846 return (1); 847 } 848 return (0); 849 } 850 851 /* 852 * Does this entire resource list consist only of legacy VGA resources? 853 */ 854 855 int 856 list_is_vga_only(struct memlist *l, enum io_mem io) 857 { 858 do { 859 if (!is_vga(l, io)) 860 return (0); 861 } while ((l = l->next) != NULL); 862 return (1); 863 } 864 865 /* 866 * Assign valid resources to unconfigured pci(e) bridges. We are trying 867 * to reprogram the bridge when its 868 * i) SECBUS == SUBBUS || 869 * ii) IOBASE > IOLIM || 870 * iii) MEMBASE > MEMLIM 871 * This must be done after one full pass through the PCI tree to collect 872 * all BIOS-configured resources, so that we know what resources are 873 * free and available to assign to the unconfigured PPBs. 874 */ 875 static void 876 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 877 { 878 uchar_t bus, dev, func; 879 uchar_t parbus, subbus; 880 uint_t io_base, io_limit, mem_base, mem_limit; 881 uint_t io_size, mem_size, io_align, mem_align; 882 uint64_t addr = 0; 883 int *regp = NULL; 884 uint_t reglen; 885 int rv, cap_ptr, physhi; 886 dev_info_t *dip; 887 uint16_t cmd_reg; 888 struct memlist *list, *scratch_list; 889 890 /* skip root (peer) PCI busses */ 891 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 892 return; 893 894 /* skip subtractive PPB when prog_sub is not TRUE */ 895 if (pci_bus_res[secbus].subtractive && !prog_sub) 896 return; 897 898 /* some entries may be empty due to discontiguous bus numbering */ 899 dip = pci_bus_res[secbus].dip; 900 if (dip == NULL) 901 return; 902 903 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 904 "reg", ®p, ®len); 905 if (rv != DDI_PROP_SUCCESS || reglen == 0) 906 return; 907 physhi = regp[0]; 908 ddi_prop_free(regp); 909 910 func = (uchar_t)PCI_REG_FUNC_G(physhi); 911 dev = (uchar_t)PCI_REG_DEV_G(physhi); 912 bus = (uchar_t)PCI_REG_BUS_G(physhi); 913 914 /* 915 * If pcie bridge, check to see if link is enabled 916 */ 917 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 918 if (cap_ptr != -1) { 919 cmd_reg = pci_getw(bus, dev, func, 920 (uint16_t)cap_ptr + PCIE_LINKCTL); 921 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 922 dcmn_err(CE_NOTE, 923 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 924 bus, dev, func); 925 return; 926 } 927 } 928 929 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 930 parbus = pci_bus_res[secbus].par_bus; 931 ASSERT(parbus == bus); 932 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 933 934 /* 935 * If we have a Cardbus bridge, but no bus space 936 */ 937 if (pci_bus_res[secbus].num_cbb != 0 && 938 pci_bus_res[secbus].bus_avail == NULL) { 939 uchar_t range; 940 941 /* normally there are 2 buses under a cardbus bridge */ 942 range = pci_bus_res[secbus].num_cbb * 2; 943 944 /* 945 * Try to find and allocate a bus-range starting at subbus+1 946 * from the parent of the PPB. 947 */ 948 for (; range != 0; range--) { 949 if (memlist_find_with_startaddr( 950 &pci_bus_res[parbus].bus_avail, 951 subbus + 1, range, 1) != NULL) 952 break; /* find bus range resource at parent */ 953 } 954 if (range != 0) { 955 memlist_insert(&pci_bus_res[secbus].bus_avail, 956 subbus + 1, range); 957 subbus = subbus + range; 958 pci_bus_res[secbus].sub_bus = subbus; 959 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 960 add_bus_range_prop(secbus); 961 962 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 963 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 964 secbus, subbus); 965 } 966 } 967 968 /* 969 * Calculate required IO size and alignment 970 * If bus io_size is zero, we are going to assign 512 bytes per bus, 971 * otherwise, we'll choose the maximum value of such calculation and 972 * bus io_size. The size needs to be 4K aligned. 973 * 974 * We calculate alignment as the largest power of two less than the 975 * the sum of all children's IO size requirements, because this will 976 * align to the size of the largest child request within that size 977 * (which is always a power of two). 978 */ 979 io_size = (subbus - secbus + 1) * 0x200; 980 if (io_size < pci_bus_res[secbus].io_size) 981 io_size = pci_bus_res[secbus].io_size; 982 io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 983 io_align = io_size; 984 P2LE(io_align); 985 986 /* 987 * Calculate required MEM size and alignment 988 * If bus mem_size is zero, we are going to assign 1M bytes per bus, 989 * otherwise, we'll choose the maximum value of such calculation and 990 * bus mem_size. The size needs to be 1M aligned. 991 * 992 * For the alignment, refer to the I/O comment above. 993 */ 994 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 995 if (mem_size < pci_bus_res[secbus].mem_size) { 996 mem_size = pci_bus_res[secbus].mem_size; 997 mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 998 } 999 mem_align = mem_size; 1000 P2LE(mem_align); 1001 1002 /* Subtractive bridge */ 1003 if (pci_bus_res[secbus].subtractive && prog_sub) { 1004 /* 1005 * We program an arbitrary amount of I/O and memory resource 1006 * for the subtractive bridge so that child dynamic-resource- 1007 * allocating devices (such as Cardbus bridges) have a chance 1008 * of success. Until we have full-tree resource rebalancing, 1009 * dynamic resource allocation (thru busra) only looks at the 1010 * parent bridge, so all PPBs must have some allocatable 1011 * resource. For non-subtractive bridges, the resources come 1012 * from the base/limit register "windows", but subtractive 1013 * bridges often don't program those (since they don't need to). 1014 * If we put all the remaining resources on the subtractive 1015 * bridge, then peer non-subtractive bridges can't allocate 1016 * more space (even though this is probably most correct). 1017 * If we put the resources only on the parent, then allocations 1018 * from children of subtractive bridges will fail without 1019 * special-case code for bypassing the subtractive bridge. 1020 * This solution is the middle-ground temporary solution until 1021 * we have fully-capable resource allocation. 1022 */ 1023 1024 /* 1025 * Add an arbitrary I/O resource to the subtractive PPB 1026 */ 1027 if (pci_bus_res[secbus].io_avail == NULL) { 1028 addr = get_parbus_io_res(parbus, secbus, io_size, 1029 io_align); 1030 if (addr) { 1031 add_ranges_prop(secbus, 1); 1032 pci_bus_res[secbus].io_reprogram = 1033 pci_bus_res[parbus].io_reprogram; 1034 1035 cmn_err(CE_NOTE, "!add io-range on subtractive" 1036 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 1037 bus, dev, func, (uint32_t)addr, 1038 (uint32_t)addr + io_size - 1); 1039 } 1040 } 1041 /* 1042 * Add an arbitrary memory resource to the subtractive PPB 1043 */ 1044 if (pci_bus_res[secbus].mem_avail == NULL) { 1045 addr = get_parbus_mem_res(parbus, secbus, mem_size, 1046 mem_align); 1047 if (addr) { 1048 add_ranges_prop(secbus, 1); 1049 pci_bus_res[secbus].mem_reprogram = 1050 pci_bus_res[parbus].mem_reprogram; 1051 1052 cmn_err(CE_NOTE, "!add mem-range on " 1053 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 1054 bus, dev, func, (uint32_t)addr, 1055 (uint32_t)addr + mem_size - 1); 1056 } 1057 } 1058 1059 goto cmd_enable; 1060 } 1061 1062 /* 1063 * Check to see if we need to reprogram I/O space, either because the 1064 * parent bus needed reprogramming and so do we, or because I/O space is 1065 * disabled in base/limit or command register. 1066 */ 1067 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1068 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1069 io_base = (io_base & 0xf0) << 8; 1070 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 1071 1072 /* Form list of all resources passed (avail + used) */ 1073 scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 1074 memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 1075 1076 if ((pci_bus_res[parbus].io_reprogram || 1077 (io_base > io_limit) || 1078 (!(cmd_reg & PCI_COMM_IO))) && 1079 !list_is_vga_only(scratch_list, IO)) { 1080 if (pci_bus_res[secbus].io_used) { 1081 memlist_subsume(&pci_bus_res[secbus].io_used, 1082 &pci_bus_res[secbus].io_avail); 1083 } 1084 if (pci_bus_res[secbus].io_avail && 1085 (!pci_bus_res[parbus].io_reprogram) && 1086 (!pci_bus_res[parbus].subtractive)) { 1087 /* rechoose old io ports info */ 1088 list = pci_bus_res[secbus].io_avail; 1089 io_base = 0; 1090 do { 1091 if (is_vga(list, IO)) 1092 continue; 1093 if (!io_base) { 1094 io_base = (uint_t)list->address; 1095 io_limit = (uint_t) 1096 list->address + list->size - 1; 1097 io_base = 1098 P2ALIGN(io_base, PPB_IO_ALIGNMENT); 1099 } else { 1100 if (list->address + list->size > 1101 io_limit) { 1102 io_limit = (uint_t) 1103 (list->address + 1104 list->size - 1); 1105 } 1106 } 1107 } while ((list = list->next) != NULL); 1108 /* 4K aligned */ 1109 io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 1110 io_size = io_limit - io_base + 1; 1111 ASSERT(io_base <= io_limit); 1112 memlist_free_all(&pci_bus_res[secbus].io_avail); 1113 memlist_insert(&pci_bus_res[secbus].io_avail, 1114 io_base, io_size); 1115 memlist_insert(&pci_bus_res[parbus].io_used, 1116 io_base, io_size); 1117 (void) memlist_remove(&pci_bus_res[parbus].io_avail, 1118 io_base, io_size); 1119 pci_bus_res[secbus].io_reprogram = B_TRUE; 1120 } else { 1121 /* get new io ports from parent bus */ 1122 addr = get_parbus_io_res(parbus, secbus, io_size, 1123 io_align); 1124 if (addr) { 1125 io_base = addr; 1126 io_limit = addr + io_size - 1; 1127 pci_bus_res[secbus].io_reprogram = B_TRUE; 1128 } 1129 } 1130 if (pci_bus_res[secbus].io_reprogram) { 1131 /* reprogram PPB regs */ 1132 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 1133 (uchar_t)((io_base>>8) & 0xf0)); 1134 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 1135 (uchar_t)((io_limit>>8) & 0xf0)); 1136 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 1137 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 1138 add_ranges_prop(secbus, 1); 1139 1140 cmn_err(CE_NOTE, "!reprogram io-range on" 1141 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 1142 bus, dev, func, io_base, io_limit); 1143 } 1144 } 1145 memlist_free_all(&scratch_list); 1146 1147 /* 1148 * Check memory space as we did I/O space. 1149 */ 1150 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1151 mem_base = (mem_base & 0xfff0) << 16; 1152 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1153 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 1154 1155 scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 1156 memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 1157 1158 if ((pci_bus_res[parbus].mem_reprogram || 1159 (mem_base > mem_limit) || 1160 (!(cmd_reg & PCI_COMM_MAE))) && 1161 !list_is_vga_only(scratch_list, MEM)) { 1162 if (pci_bus_res[secbus].mem_used) { 1163 memlist_subsume(&pci_bus_res[secbus].mem_used, 1164 &pci_bus_res[secbus].mem_avail); 1165 } 1166 if (pci_bus_res[secbus].mem_avail && 1167 (!pci_bus_res[parbus].mem_reprogram) && 1168 (!pci_bus_res[parbus].subtractive)) { 1169 /* rechoose old mem resource */ 1170 list = pci_bus_res[secbus].mem_avail; 1171 mem_base = 0; 1172 do { 1173 if (is_vga(list, MEM)) 1174 continue; 1175 if (mem_base == 0) { 1176 mem_base = (uint_t)list->address; 1177 mem_base = P2ALIGN(mem_base, 1178 PPB_MEM_ALIGNMENT); 1179 mem_limit = (uint_t) 1180 (list->address + list->size - 1); 1181 } else { 1182 if ((list->address + list->size) > 1183 mem_limit) { 1184 mem_limit = (uint_t) 1185 (list->address + 1186 list->size - 1); 1187 } 1188 } 1189 } while ((list = list->next) != NULL); 1190 mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 1191 mem_size = mem_limit + 1 - mem_base; 1192 ASSERT(mem_base <= mem_limit); 1193 memlist_free_all(&pci_bus_res[secbus].mem_avail); 1194 memlist_insert(&pci_bus_res[secbus].mem_avail, 1195 mem_base, mem_size); 1196 memlist_insert(&pci_bus_res[parbus].mem_used, 1197 mem_base, mem_size); 1198 (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 1199 mem_base, mem_size); 1200 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1201 } else { 1202 /* get new mem resource from parent bus */ 1203 addr = get_parbus_mem_res(parbus, secbus, mem_size, 1204 mem_align); 1205 if (addr) { 1206 mem_base = addr; 1207 mem_limit = addr + mem_size - 1; 1208 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1209 } 1210 } 1211 1212 if (pci_bus_res[secbus].mem_reprogram) { 1213 /* reprogram PPB MEM regs */ 1214 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 1215 (uint16_t)((mem_base>>16) & 0xfff0)); 1216 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 1217 (uint16_t)((mem_limit>>16) & 0xfff0)); 1218 /* 1219 * Disable PMEM window by setting base > limit. 1220 * We currently don't reprogram the PMEM like we've 1221 * done for I/O and MEM. (Devices that support prefetch 1222 * can use non-prefetch MEM.) Anyway, if the MEM access 1223 * bit is initially disabled by BIOS, we disable the 1224 * PMEM window manually by setting PMEM base > PMEM 1225 * limit here, in case there are incorrect values in 1226 * them from BIOS, so that we won't get in trouble once 1227 * the MEM access bit is enabled at the end of this 1228 * function. 1229 */ 1230 if (!(cmd_reg & PCI_COMM_MAE)) { 1231 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 1232 0xfff0); 1233 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 1234 0x0); 1235 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 1236 0xffffffff); 1237 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 1238 0x0); 1239 } 1240 1241 add_ranges_prop(secbus, 1); 1242 1243 cmn_err(CE_NOTE, "!reprogram mem-range on" 1244 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 1245 bus, dev, func, mem_base, mem_limit); 1246 } 1247 } 1248 memlist_free_all(&scratch_list); 1249 1250 cmd_enable: 1251 if (pci_bus_res[secbus].io_avail) 1252 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 1253 if (pci_bus_res[secbus].mem_avail) 1254 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 1255 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1256 } 1257 1258 void 1259 pci_reprogram(void) 1260 { 1261 int i, pci_reconfig = 1; 1262 char *onoff; 1263 int bus; 1264 1265 /* 1266 * Scan ACPI namespace for _BBN objects, make sure that 1267 * childless root-bridges appear in devinfo tree 1268 */ 1269 pci_scan_bbn(); 1270 pci_unitaddr_cache_init(); 1271 1272 /* 1273 * Fix-up unit-address assignments if cache is available 1274 */ 1275 if (pci_unitaddr_cache_valid()) { 1276 int pci_regs[] = {0, 0, 0}; 1277 int new_addr; 1278 int index = 0; 1279 1280 for (bus = 0; bus <= pci_bios_maxbus; bus++) { 1281 /* skip non-root (peer) PCI busses */ 1282 if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || 1283 (pci_bus_res[bus].dip == NULL)) 1284 continue; 1285 1286 new_addr = pci_bus_unitaddr(index); 1287 if (pci_bus_res[bus].root_addr != new_addr) { 1288 /* update reg property for node */ 1289 pci_regs[0] = pci_bus_res[bus].root_addr = 1290 new_addr; 1291 (void) ndi_prop_update_int_array( 1292 DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1293 "reg", (int *)pci_regs, 3); 1294 } 1295 index++; 1296 } 1297 } else { 1298 /* perform legacy processing */ 1299 pci_renumber_root_busses(); 1300 pci_unitaddr_cache_create(); 1301 } 1302 1303 /* 1304 * Do root-bus resource discovery 1305 */ 1306 for (bus = 0; bus <= pci_bios_maxbus; bus++) { 1307 /* skip non-root (peer) PCI busses */ 1308 if (pci_bus_res[bus].par_bus != (uchar_t)-1) 1309 continue; 1310 1311 /* 1312 * 1. find resources associated with this root bus 1313 */ 1314 populate_bus_res(bus); 1315 1316 1317 /* 1318 * 2. Remove used PCI and ISA resources from bus resource map 1319 */ 1320 1321 memlist_remove_list(&pci_bus_res[bus].io_avail, 1322 pci_bus_res[bus].io_used); 1323 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1324 pci_bus_res[bus].mem_used); 1325 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1326 pci_bus_res[bus].pmem_used); 1327 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1328 pci_bus_res[bus].pmem_used); 1329 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1330 pci_bus_res[bus].mem_used); 1331 1332 memlist_remove_list(&pci_bus_res[bus].io_avail, 1333 isa_res.io_used); 1334 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1335 isa_res.mem_used); 1336 1337 /* 1338 * 3. Exclude <1M address range here in case below reserved 1339 * ranges for BIOS data area, ROM area etc are wrongly reported 1340 * in ACPI resource producer entries for PCI root bus. 1341 * 00000000 - 000003FF RAM 1342 * 00000400 - 000004FF BIOS data area 1343 * 00000500 - 0009FFFF RAM 1344 * 000A0000 - 000BFFFF VGA RAM 1345 * 000C0000 - 000FFFFF ROM area 1346 */ 1347 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000); 1348 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 1349 0, 0x100000); 1350 } 1351 1352 memlist_free_all(&isa_res.io_used); 1353 memlist_free_all(&isa_res.mem_used); 1354 1355 /* add bus-range property for root/peer bus nodes */ 1356 for (i = 0; i <= pci_bios_maxbus; i++) { 1357 /* create bus-range property on root/peer buses */ 1358 if (pci_bus_res[i].par_bus == (uchar_t)-1) 1359 add_bus_range_prop(i); 1360 1361 /* setup bus range resource on each bus */ 1362 setup_bus_res(i); 1363 } 1364 1365 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1366 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 1367 if (strcmp(onoff, "off") == 0) { 1368 pci_reconfig = 0; 1369 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 1370 } 1371 ddi_prop_free(onoff); 1372 } 1373 1374 remove_subtractive_res(); 1375 1376 /* reprogram the non-subtractive PPB */ 1377 if (pci_reconfig) 1378 for (i = 0; i <= pci_bios_maxbus; i++) 1379 fix_ppb_res(i, B_FALSE); 1380 1381 for (i = 0; i <= pci_bios_maxbus; i++) { 1382 /* configure devices not configured by BIOS */ 1383 if (pci_reconfig) { 1384 /* 1385 * Reprogram the subtractive PPB. At this time, all its 1386 * siblings should have got their resources already. 1387 */ 1388 if (pci_bus_res[i].subtractive) 1389 fix_ppb_res(i, B_TRUE); 1390 enumerate_bus_devs(i, CONFIG_NEW); 1391 } 1392 } 1393 1394 /* All dev programmed, so we can create available prop */ 1395 for (i = 0; i <= pci_bios_maxbus; i++) 1396 add_bus_available_prop(i); 1397 } 1398 1399 /* 1400 * populate bus resources 1401 */ 1402 static void 1403 populate_bus_res(uchar_t bus) 1404 { 1405 1406 /* scan BIOS structures */ 1407 pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); 1408 pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); 1409 pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); 1410 pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); 1411 1412 /* 1413 * attempt to initialize sub_bus from the largest range-end 1414 * in the bus_avail list 1415 */ 1416 if (pci_bus_res[bus].bus_avail != NULL) { 1417 struct memlist *entry; 1418 int current; 1419 1420 entry = pci_bus_res[bus].bus_avail; 1421 while (entry != NULL) { 1422 current = entry->address + entry->size - 1; 1423 if (current > pci_bus_res[bus].sub_bus) 1424 pci_bus_res[bus].sub_bus = current; 1425 entry = entry->next; 1426 } 1427 } 1428 1429 if (bus == 0) { 1430 /* 1431 * Special treatment of bus 0: 1432 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 1433 * pcimem from boot and make I/O space the entire range 1434 * starting at 0x100. 1435 */ 1436 if (pci_bus_res[0].mem_avail == NULL) 1437 pci_bus_res[0].mem_avail = 1438 memlist_dup(bootops->boot_mem->pcimem); 1439 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1440 if (pci_bus_res[0].io_avail == NULL) 1441 memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 1442 } 1443 1444 /* 1445 * Create 'ranges' property here before any resources are 1446 * removed from the resource lists 1447 */ 1448 add_ranges_prop(bus, 0); 1449 } 1450 1451 1452 /* 1453 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1454 */ 1455 static void 1456 create_root_bus_dip(uchar_t bus) 1457 { 1458 int pci_regs[] = {0, 0, 0}; 1459 dev_info_t *dip; 1460 1461 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1462 1463 num_root_bus++; 1464 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1465 (pnode_t)DEVI_SID_NODEID, &dip); 1466 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1467 "#address-cells", 3); 1468 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1469 "#size-cells", 2); 1470 pci_regs[0] = pci_bus_res[bus].root_addr; 1471 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1472 "reg", (int *)pci_regs, 3); 1473 1474 /* 1475 * If system has PCIe bus, then create different properties 1476 */ 1477 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1478 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1479 "device_type", "pci"); 1480 1481 (void) ndi_devi_bind_driver(dip, 0); 1482 pci_bus_res[bus].dip = dip; 1483 } 1484 1485 /* 1486 * For any fixed configuration (often compatability) pci devices 1487 * and those with their own expansion rom, create device nodes 1488 * to hold the already configured device details. 1489 */ 1490 void 1491 enumerate_bus_devs(uchar_t bus, int config_op) 1492 { 1493 uchar_t dev, func, nfunc, header; 1494 ushort_t venid; 1495 struct pci_devfunc *devlist = NULL, *entry; 1496 1497 if (config_op == CONFIG_NEW) { 1498 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1499 } else if (config_op == CONFIG_FIX) { 1500 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1501 } else 1502 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1503 1504 if (config_op == CONFIG_NEW) { 1505 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1506 while (devlist) { 1507 entry = devlist; 1508 devlist = entry->next; 1509 if (entry->reprogram || 1510 pci_bus_res[bus].io_reprogram || 1511 pci_bus_res[bus].mem_reprogram) { 1512 /* reprogram device(s) */ 1513 (void) add_reg_props(entry->dip, bus, 1514 entry->dev, entry->func, CONFIG_NEW, 0); 1515 } 1516 kmem_free(entry, sizeof (*entry)); 1517 } 1518 pci_bus_res[bus].privdata = NULL; 1519 return; 1520 } 1521 1522 for (dev = 0; dev < max_dev_pci; dev++) { 1523 nfunc = 1; 1524 for (func = 0; func < nfunc; func++) { 1525 1526 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1527 dev, func); 1528 1529 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1530 1531 if ((venid == 0xffff) || (venid == 0)) { 1532 /* no function at this address */ 1533 continue; 1534 } 1535 1536 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1537 if (header == 0xff) { 1538 continue; /* illegal value */ 1539 } 1540 1541 /* 1542 * according to some mail from Microsoft posted 1543 * to the pci-drivers alias, their only requirement 1544 * for a multifunction device is for the 1st 1545 * function to have to PCI_HEADER_MULTI bit set. 1546 */ 1547 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1548 nfunc = 8; 1549 } 1550 1551 if (config_op == CONFIG_FIX || 1552 config_op == CONFIG_INFO) { 1553 /* 1554 * Create the node, unconditionally, on the 1555 * first pass only. It may still need 1556 * resource assignment, which will be 1557 * done on the second, CONFIG_NEW, pass. 1558 */ 1559 process_devfunc(bus, dev, func, header, 1560 venid, config_op); 1561 1562 } 1563 } 1564 } 1565 1566 /* percolate bus used resources up through parents to root */ 1567 if (config_op == CONFIG_INFO) { 1568 int par_bus; 1569 1570 par_bus = pci_bus_res[bus].par_bus; 1571 while (par_bus != (uchar_t)-1) { 1572 pci_bus_res[par_bus].io_size += 1573 pci_bus_res[bus].io_size; 1574 pci_bus_res[par_bus].mem_size += 1575 pci_bus_res[bus].mem_size; 1576 1577 if (pci_bus_res[bus].io_used) 1578 memlist_merge(&pci_bus_res[bus].io_used, 1579 &pci_bus_res[par_bus].io_used); 1580 1581 if (pci_bus_res[bus].mem_used) 1582 memlist_merge(&pci_bus_res[bus].mem_used, 1583 &pci_bus_res[par_bus].mem_used); 1584 1585 if (pci_bus_res[bus].pmem_used) 1586 memlist_merge(&pci_bus_res[bus].pmem_used, 1587 &pci_bus_res[par_bus].pmem_used); 1588 1589 bus = par_bus; 1590 par_bus = pci_bus_res[par_bus].par_bus; 1591 } 1592 } 1593 } 1594 1595 static int 1596 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1597 ushort_t subvenid, ushort_t subdevid) 1598 { 1599 static int prop_exist = -1; 1600 static char *pciide_str; 1601 char compat[32]; 1602 1603 if (prop_exist == -1) { 1604 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1605 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1606 &pciide_str) == DDI_SUCCESS); 1607 } 1608 1609 if (!prop_exist) 1610 return (0); 1611 1612 /* compare property value against various forms of compatible */ 1613 if (subvenid) { 1614 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1615 venid, devid, subvenid, subdevid, revid); 1616 if (strcmp(pciide_str, compat) == 0) 1617 return (1); 1618 1619 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1620 venid, devid, subvenid, subdevid); 1621 if (strcmp(pciide_str, compat) == 0) 1622 return (1); 1623 1624 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1625 subvenid, subdevid); 1626 if (strcmp(pciide_str, compat) == 0) 1627 return (1); 1628 } 1629 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1630 venid, devid, revid); 1631 if (strcmp(pciide_str, compat) == 0) 1632 return (1); 1633 1634 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1635 if (strcmp(pciide_str, compat) == 0) 1636 return (1); 1637 1638 return (0); 1639 } 1640 1641 static int 1642 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1643 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1644 { 1645 struct ide_table { /* table for PCI_MASS_OTHER */ 1646 ushort_t venid; 1647 ushort_t devid; 1648 } *entry; 1649 1650 /* XXX SATA and other devices: need a way to add dynamically */ 1651 static struct ide_table ide_other[] = { 1652 {0x1095, 0x3112}, 1653 {0x1095, 0x3114}, 1654 {0x1095, 0x3512}, 1655 {0x1095, 0x680}, /* Sil0680 */ 1656 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1657 {0, 0} 1658 }; 1659 1660 if (basecl != PCI_CLASS_MASS) 1661 return (0); 1662 1663 if (subcl == PCI_MASS_IDE) { 1664 return (1); 1665 } 1666 1667 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1668 return (1); 1669 1670 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1671 return (0); 1672 } 1673 1674 entry = &ide_other[0]; 1675 while (entry->venid) { 1676 if (entry->venid == venid && entry->devid == devid) 1677 return (1); 1678 entry++; 1679 } 1680 return (0); 1681 } 1682 1683 static int 1684 is_display(uint_t classcode) 1685 { 1686 static uint_t disp_classes[] = { 1687 0x000100, 1688 0x030000, 1689 0x030001 1690 }; 1691 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1692 1693 for (i = 0; i < nclasses; i++) { 1694 if (classcode == disp_classes[i]) 1695 return (1); 1696 } 1697 return (0); 1698 } 1699 1700 static void 1701 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1702 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1703 { 1704 struct pci_fixundo *newundo; 1705 1706 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1707 1708 /* 1709 * Adding an item to this list means that we must turn its NMIENABLE 1710 * bit back on at a later time. 1711 */ 1712 newundo->bus = bus; 1713 newundo->dev = dev; 1714 newundo->fn = fn; 1715 newundo->undofn = undofn; 1716 newundo->next = undolist; 1717 1718 /* add to the undo list in LIFO order */ 1719 undolist = newundo; 1720 } 1721 1722 void 1723 add_pci_fixes(void) 1724 { 1725 int i; 1726 1727 for (i = 0; i <= pci_bios_maxbus; i++) { 1728 /* 1729 * For each bus, apply needed fixes to the appropriate devices. 1730 * This must be done before the main enumeration loop because 1731 * some fixes must be applied to devices normally encountered 1732 * later in the pci scan (e.g. if a fix to device 7 must be 1733 * applied before scanning device 6, applying fixes in the 1734 * normal enumeration loop would obviously be too late). 1735 */ 1736 enumerate_bus_devs(i, CONFIG_FIX); 1737 } 1738 } 1739 1740 void 1741 undo_pci_fixes(void) 1742 { 1743 struct pci_fixundo *nextundo; 1744 uint8_t bus, dev, fn; 1745 1746 /* 1747 * All fixes in the undo list are performed unconditionally. Future 1748 * fixes may require selective undo. 1749 */ 1750 while (undolist != NULL) { 1751 1752 bus = undolist->bus; 1753 dev = undolist->dev; 1754 fn = undolist->fn; 1755 1756 (*(undolist->undofn))(bus, dev, fn); 1757 1758 nextundo = undolist->next; 1759 kmem_free(undolist, sizeof (struct pci_fixundo)); 1760 undolist = nextundo; 1761 } 1762 } 1763 1764 static void 1765 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1766 { 1767 uint8_t val8; 1768 1769 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1770 /* 1771 * The NMIONERR bit is turned back on to allow the SMM BIOS 1772 * to handle more critical PCI errors (e.g. PERR#). 1773 */ 1774 val8 |= AMD8111_ENABLENMI; 1775 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1776 } 1777 1778 static void 1779 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1780 { 1781 uint8_t val8; 1782 1783 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1784 1785 if ((val8 & AMD8111_ENABLENMI) == 0) 1786 return; 1787 1788 /* 1789 * We reset NMIONERR in the LPC because master-abort on the PCI 1790 * bridge side of the 8111 will cause NMI, which might cause SMI, 1791 * which sometimes prevents all devices from being enumerated. 1792 */ 1793 val8 &= ~AMD8111_ENABLENMI; 1794 1795 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1796 1797 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1798 } 1799 1800 static void 1801 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1802 { 1803 uint16_t status; 1804 uint8_t header; 1805 uint8_t cap_ptr; 1806 uint8_t cap_id; 1807 uint16_t pmcsr; 1808 1809 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1810 if (!(status & PCI_STAT_CAP)) 1811 return; /* No capabilities list */ 1812 1813 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1814 if (header == PCI_HEADER_CARDBUS) 1815 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1816 else 1817 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1818 /* 1819 * Walk the capabilities list searching for a PM entry. 1820 */ 1821 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1822 cap_ptr &= PCI_CAP_PTR_MASK; 1823 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1824 if (cap_id == PCI_CAP_ID_PM) { 1825 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1826 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1827 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1828 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1829 break; 1830 } 1831 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1832 } 1833 1834 } 1835 1836 #define is_isa(bc, sc) \ 1837 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 1838 1839 static void 1840 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1841 ushort_t vendorid, int config_op) 1842 { 1843 char nodename[32], unitaddr[5]; 1844 dev_info_t *dip; 1845 uchar_t basecl, subcl, progcl, intr, revid; 1846 ushort_t subvenid, subdevid, status; 1847 ushort_t slot_num; 1848 uint_t classcode, revclass; 1849 int reprogram = 0, pciide = 0; 1850 int power[2] = {1, 1}; 1851 int pciex = 0; 1852 ushort_t is_pci_bridge = 0; 1853 struct pci_devfunc *devlist = NULL, *entry = NULL; 1854 gfx_entry_t *gfxp; 1855 1856 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1857 1858 switch (header & PCI_HEADER_TYPE_M) { 1859 case PCI_HEADER_ZERO: 1860 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1861 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1862 break; 1863 case PCI_HEADER_CARDBUS: 1864 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1865 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1866 /* Record the # of cardbus bridges found on the bus */ 1867 if (config_op == CONFIG_INFO) 1868 pci_bus_res[bus].num_cbb++; 1869 break; 1870 default: 1871 subvenid = 0; 1872 subdevid = 0; 1873 break; 1874 } 1875 1876 if (config_op == CONFIG_FIX) { 1877 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1878 pci_fix_amd8111(bus, dev, func); 1879 } 1880 return; 1881 } 1882 1883 /* XXX should be use generic names? derive from class? */ 1884 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1885 classcode = revclass >> 8; 1886 revid = revclass & 0xff; 1887 1888 /* figure out if this is pci-ide */ 1889 basecl = classcode >> 16; 1890 subcl = (classcode >> 8) & 0xff; 1891 progcl = classcode & 0xff; 1892 1893 1894 if (is_display(classcode)) 1895 (void) snprintf(nodename, sizeof (nodename), "display"); 1896 else if (!pseudo_isa && is_isa(basecl, subcl)) 1897 (void) snprintf(nodename, sizeof (nodename), "isa"); 1898 else if (subvenid != 0) 1899 (void) snprintf(nodename, sizeof (nodename), 1900 "pci%x,%x", subvenid, subdevid); 1901 else 1902 (void) snprintf(nodename, sizeof (nodename), 1903 "pci%x,%x", vendorid, deviceid); 1904 1905 /* make sure parent bus dip has been created */ 1906 if (pci_bus_res[bus].dip == NULL) 1907 create_root_bus_dip(bus); 1908 1909 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1910 DEVI_SID_NODEID, &dip); 1911 1912 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1913 &is_pci_bridge) == B_TRUE) 1914 pciex = 1; 1915 1916 /* add properties */ 1917 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1918 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1919 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1920 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1921 "class-code", classcode); 1922 if (func == 0) 1923 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1924 else 1925 (void) snprintf(unitaddr, sizeof (unitaddr), 1926 "%x,%x", dev, func); 1927 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1928 "unit-address", unitaddr); 1929 1930 /* add device_type for display nodes */ 1931 if (is_display(classcode)) { 1932 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1933 "device_type", "display"); 1934 } 1935 /* add special stuff for header type */ 1936 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1937 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1938 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1939 1940 if (subvenid != 0) { 1941 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1942 "subsystem-id", subdevid); 1943 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1944 "subsystem-vendor-id", subvenid); 1945 } 1946 if (!pciex) 1947 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1948 "min-grant", mingrant); 1949 if (!pciex) 1950 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1951 "max-latency", maxlatency); 1952 } 1953 1954 /* interrupt, record if not 0 */ 1955 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1956 if (intr != 0) 1957 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1958 "interrupts", intr); 1959 1960 /* 1961 * Add support for 133 mhz pci eventually 1962 */ 1963 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1964 1965 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1966 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1967 if (!pciex && (status & PCI_STAT_FBBC)) 1968 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1969 "fast-back-to-back"); 1970 if (!pciex && (status & PCI_STAT_66MHZ)) 1971 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1972 "66mhz-capable"); 1973 if (status & PCI_STAT_UDF) 1974 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1975 "udf-supported"); 1976 if (pciex && slot_num) { 1977 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1978 "physical-slot#", slot_num); 1979 if (!is_pci_bridge) 1980 pciex_slot_names_prop(dip, slot_num); 1981 } 1982 1983 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1984 "power-consumption", power, 2); 1985 1986 /* Set the device PM state to D0 */ 1987 set_devpm_d0(bus, dev, func); 1988 1989 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1990 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 1991 else { 1992 /* 1993 * Record the non-PPB devices on the bus for possible 1994 * reprogramming at 2nd bus enumeration. 1995 * Note: PPB reprogramming is done in fix_ppb_res() 1996 */ 1997 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1998 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 1999 entry->dip = dip; 2000 entry->dev = dev; 2001 entry->func = func; 2002 entry->next = devlist; 2003 pci_bus_res[bus].privdata = entry; 2004 } 2005 2006 if (config_op == CONFIG_INFO && 2007 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 2008 create_ioapic_node(bus, dev, func, vendorid, deviceid); 2009 } 2010 2011 /* check for ck8-04 based PCI ISA bridge only */ 2012 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 2013 (func == 0)) 2014 add_nvidia_isa_bridge_props(dip, bus, dev, func); 2015 2016 if (pciex && is_pci_bridge) 2017 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2018 (char *)"PCIe-PCI bridge"); 2019 else 2020 add_model_prop(dip, classcode); 2021 2022 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 2023 revid, classcode, pciex); 2024 2025 /* 2026 * See if this device is a controller that advertises 2027 * itself to be a standard ATA task file controller, or one that 2028 * has been hard coded. 2029 * 2030 * If it is, check if any other higher precedence driver listed in 2031 * driver_aliases will claim the node by calling 2032 * ddi_compatibile_driver_major. If so, clear pciide and do not 2033 * create a pci-ide node or any other special handling. 2034 * 2035 * If another driver does not bind, set the node name to pci-ide 2036 * and then let the special pci-ide handling for registers and 2037 * child pci-ide nodes proceed below. 2038 */ 2039 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 2040 subvenid, subdevid) == 1) { 2041 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 2042 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 2043 pciide = 1; 2044 } 2045 } 2046 2047 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 2048 (void) ndi_devi_bind_driver(dip, 0); 2049 2050 /* special handling for pci-ide */ 2051 if (pciide) { 2052 dev_info_t *cdip; 2053 2054 /* 2055 * Create properties specified by P1275 Working Group 2056 * Proposal #414 Version 1 2057 */ 2058 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2059 "device_type", "pci-ide"); 2060 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2061 "#address-cells", 1); 2062 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2063 "#size-cells", 0); 2064 2065 /* allocate two child nodes */ 2066 ndi_devi_alloc_sleep(dip, "ide", 2067 (pnode_t)DEVI_SID_NODEID, &cdip); 2068 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2069 "reg", 0); 2070 (void) ndi_devi_bind_driver(cdip, 0); 2071 ndi_devi_alloc_sleep(dip, "ide", 2072 (pnode_t)DEVI_SID_NODEID, &cdip); 2073 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2074 "reg", 1); 2075 (void) ndi_devi_bind_driver(cdip, 0); 2076 2077 reprogram = 0; /* don't reprogram pci-ide bridge */ 2078 } 2079 2080 if (is_display(classcode)) { 2081 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 2082 gfxp->g_dip = dip; 2083 gfxp->g_prev = NULL; 2084 gfxp->g_next = gfx_devinfo_list; 2085 gfx_devinfo_list = gfxp; 2086 if (gfxp->g_next) 2087 gfxp->g_next->g_prev = gfxp; 2088 } 2089 2090 /* special handling for isa */ 2091 if (!pseudo_isa && is_isa(basecl, subcl)) { 2092 /* add device_type */ 2093 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2094 "device_type", "isa"); 2095 } 2096 2097 if (reprogram && (entry != NULL)) 2098 entry->reprogram = B_TRUE; 2099 2100 } 2101 2102 /* 2103 * Some vendors do not use unique subsystem IDs in their products, which 2104 * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 2105 * Allow for these compatible forms to be excluded on a per-device basis. 2106 */ 2107 /*ARGSUSED*/ 2108 static boolean_t 2109 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 2110 ushort_t subdevid, uchar_t revid, uint_t classcode) 2111 { 2112 /* Nvidia display adapters */ 2113 if ((venid == 0x10de) && (is_display(classcode))) 2114 return (B_TRUE); 2115 2116 return (B_FALSE); 2117 } 2118 2119 /* 2120 * Set the compatible property to a value compliant with 2121 * rev 2.1 of the IEEE1275 PCI binding. 2122 * (Also used for PCI-Express devices). 2123 * 2124 * pciVVVV,DDDD.SSSS.ssss.RR (0) 2125 * pciVVVV,DDDD.SSSS.ssss (1) 2126 * pciSSSS,ssss (2) 2127 * pciVVVV,DDDD.RR (3) 2128 * pciVVVV,DDDD (4) 2129 * pciclass,CCSSPP (5) 2130 * pciclass,CCSS (6) 2131 * 2132 * The Subsystem (SSSS) forms are not inserted if 2133 * subsystem-vendor-id is 0. 2134 * 2135 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 2136 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 2137 * 2138 * Set with setprop and \x00 between each 2139 * to generate the encoded string array form. 2140 */ 2141 void 2142 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 2143 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 2144 int pciex) 2145 { 2146 int i = 0; 2147 int size = COMPAT_BUFSIZE; 2148 char *compat[13]; 2149 char *buf, *curr; 2150 2151 curr = buf = kmem_alloc(size, KM_SLEEP); 2152 2153 if (pciex) { 2154 if (subvenid) { 2155 compat[i++] = curr; /* form 0 */ 2156 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 2157 vendorid, deviceid, subvenid, subdevid, revid); 2158 size -= strlen(curr) + 1; 2159 curr += strlen(curr) + 1; 2160 2161 compat[i++] = curr; /* form 1 */ 2162 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 2163 vendorid, deviceid, subvenid, subdevid); 2164 size -= strlen(curr) + 1; 2165 curr += strlen(curr) + 1; 2166 2167 } 2168 compat[i++] = curr; /* form 3 */ 2169 (void) snprintf(curr, size, "pciex%x,%x.%x", 2170 vendorid, deviceid, revid); 2171 size -= strlen(curr) + 1; 2172 curr += strlen(curr) + 1; 2173 2174 compat[i++] = curr; /* form 4 */ 2175 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 2176 size -= strlen(curr) + 1; 2177 curr += strlen(curr) + 1; 2178 2179 compat[i++] = curr; /* form 5 */ 2180 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 2181 size -= strlen(curr) + 1; 2182 curr += strlen(curr) + 1; 2183 2184 compat[i++] = curr; /* form 6 */ 2185 (void) snprintf(curr, size, "pciexclass,%04x", 2186 (classcode >> 8)); 2187 size -= strlen(curr) + 1; 2188 curr += strlen(curr) + 1; 2189 } 2190 2191 if (subvenid) { 2192 compat[i++] = curr; /* form 0 */ 2193 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 2194 vendorid, deviceid, subvenid, subdevid, revid); 2195 size -= strlen(curr) + 1; 2196 curr += strlen(curr) + 1; 2197 2198 compat[i++] = curr; /* form 1 */ 2199 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 2200 vendorid, deviceid, subvenid, subdevid); 2201 size -= strlen(curr) + 1; 2202 curr += strlen(curr) + 1; 2203 2204 if (subsys_compat_exclude(vendorid, deviceid, subvenid, 2205 subdevid, revid, classcode) == B_FALSE) { 2206 compat[i++] = curr; /* form 2 */ 2207 (void) snprintf(curr, size, "pci%x,%x", subvenid, 2208 subdevid); 2209 size -= strlen(curr) + 1; 2210 curr += strlen(curr) + 1; 2211 } 2212 } 2213 compat[i++] = curr; /* form 3 */ 2214 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 2215 size -= strlen(curr) + 1; 2216 curr += strlen(curr) + 1; 2217 2218 compat[i++] = curr; /* form 4 */ 2219 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 2220 size -= strlen(curr) + 1; 2221 curr += strlen(curr) + 1; 2222 2223 compat[i++] = curr; /* form 5 */ 2224 (void) snprintf(curr, size, "pciclass,%06x", classcode); 2225 size -= strlen(curr) + 1; 2226 curr += strlen(curr) + 1; 2227 2228 compat[i++] = curr; /* form 6 */ 2229 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 2230 size -= strlen(curr) + 1; 2231 curr += strlen(curr) + 1; 2232 2233 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 2234 "compatible", compat, i); 2235 kmem_free(buf, COMPAT_BUFSIZE); 2236 } 2237 2238 /* 2239 * Adjust the reg properties for a dual channel PCI-IDE device. 2240 * 2241 * NOTE: don't do anything that changes the order of the hard-decodes 2242 * and programmed BARs. The kernel driver depends on these values 2243 * being in this order regardless of whether they're for a 'native' 2244 * mode BAR or not. 2245 */ 2246 /* 2247 * config info for pci-ide devices 2248 */ 2249 static struct { 2250 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 2251 uchar_t bar_offset; /* offset for alt status register */ 2252 ushort_t addr; /* compatibility mode base address */ 2253 ushort_t length; /* number of ports for this BAR */ 2254 } pciide_bar[] = { 2255 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 2256 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 2257 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 2258 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 2259 }; 2260 2261 static int 2262 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 2263 { 2264 int hard_decode = 0; 2265 2266 /* 2267 * Adjust the base and len for the BARs of the PCI-IDE 2268 * device's primary and secondary controllers. The first 2269 * two BARs are for the primary controller and the next 2270 * two BARs are for the secondary controller. The fifth 2271 * and sixth bars are never adjusted. 2272 */ 2273 if (index >= 0 && index <= 3) { 2274 *lenp = pciide_bar[index].length; 2275 2276 if (progcl & pciide_bar[index].native_mask) { 2277 *basep += pciide_bar[index].bar_offset; 2278 } else { 2279 *basep = pciide_bar[index].addr; 2280 hard_decode = 1; 2281 } 2282 } 2283 2284 /* 2285 * if either base or len is zero make certain both are zero 2286 */ 2287 if (*basep == 0 || *lenp == 0) { 2288 *basep = 0; 2289 *lenp = 0; 2290 hard_decode = 0; 2291 } 2292 2293 return (hard_decode); 2294 } 2295 2296 2297 /* 2298 * Add the "reg" and "assigned-addresses" property 2299 */ 2300 static int 2301 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2302 int config_op, int pciide) 2303 { 2304 uchar_t baseclass, subclass, progclass, header; 2305 ushort_t bar_sz; 2306 uint_t value = 0, len, devloc; 2307 uint_t base, base_hi, type; 2308 ushort_t offset, end; 2309 int max_basereg, j, reprogram = 0; 2310 uint_t phys_hi; 2311 struct memlist **io_avail, **io_used; 2312 struct memlist **mem_avail, **mem_used; 2313 struct memlist **pmem_avail, **pmem_used; 2314 uchar_t res_bus; 2315 2316 pci_regspec_t regs[16] = {{0}}; 2317 pci_regspec_t assigned[15] = {{0}}; 2318 int nreg, nasgn; 2319 2320 io_avail = &pci_bus_res[bus].io_avail; 2321 io_used = &pci_bus_res[bus].io_used; 2322 mem_avail = &pci_bus_res[bus].mem_avail; 2323 mem_used = &pci_bus_res[bus].mem_used; 2324 pmem_avail = &pci_bus_res[bus].pmem_avail; 2325 pmem_used = &pci_bus_res[bus].pmem_used; 2326 2327 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 2328 regs[0].pci_phys_hi = devloc; 2329 nreg = 1; /* rest of regs[0] is all zero */ 2330 nasgn = 0; 2331 2332 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 2333 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 2334 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2335 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 2336 2337 switch (header) { 2338 case PCI_HEADER_ZERO: 2339 max_basereg = PCI_BASE_NUM; 2340 break; 2341 case PCI_HEADER_PPB: 2342 max_basereg = PCI_BCNF_BASE_NUM; 2343 break; 2344 case PCI_HEADER_CARDBUS: 2345 max_basereg = PCI_CBUS_BASE_NUM; 2346 reprogram = 1; 2347 break; 2348 default: 2349 max_basereg = 0; 2350 break; 2351 } 2352 2353 /* 2354 * Create the register property by saving the current 2355 * value of the base register. Write 0xffffffff to the 2356 * base register. Read the value back to determine the 2357 * required size of the address space. Restore the base 2358 * register contents. 2359 * 2360 * Do not disable I/O and memory access; this isn't necessary 2361 * since no driver is yet attached to this device, and disabling 2362 * I/O and memory access has the side-effect of disabling PCI-PCI 2363 * bridge mappings, which makes the bridge transparent to secondary- 2364 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 2365 * Spec V1.2). 2366 */ 2367 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 2368 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 2369 j++, offset += bar_sz) { 2370 /* determine the size of the address space */ 2371 base = pci_getl(bus, dev, func, offset); 2372 pci_putl(bus, dev, func, offset, 0xffffffff); 2373 value = pci_getl(bus, dev, func, offset); 2374 pci_putl(bus, dev, func, offset, base); 2375 2376 /* construct phys hi,med.lo, size hi, lo */ 2377 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 2378 int hard_decode = 0; 2379 2380 /* i/o space */ 2381 bar_sz = PCI_BAR_SZ_32; 2382 value &= PCI_BASE_IO_ADDR_M; 2383 len = ((value ^ (value-1)) + 1) >> 1; 2384 2385 /* XXX Adjust first 4 IDE registers */ 2386 if (pciide) { 2387 if (subclass != PCI_MASS_IDE) 2388 progclass = (PCI_IDE_IF_NATIVE_PRI | 2389 PCI_IDE_IF_NATIVE_SEC); 2390 hard_decode = pciIdeAdjustBAR(progclass, j, 2391 &base, &len); 2392 } else if (value == 0) { 2393 /* skip base regs with size of 0 */ 2394 continue; 2395 } 2396 2397 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 2398 (hard_decode ? PCI_RELOCAT_B : offset); 2399 regs[nreg].pci_phys_low = hard_decode ? 2400 base & PCI_BASE_IO_ADDR_M : 0; 2401 assigned[nasgn].pci_phys_hi = 2402 PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 2403 regs[nreg].pci_size_low = 2404 assigned[nasgn].pci_size_low = len; 2405 type = base & (~PCI_BASE_IO_ADDR_M); 2406 base &= PCI_BASE_IO_ADDR_M; 2407 /* 2408 * A device under a subtractive PPB can allocate 2409 * resources from its parent bus if there is no resource 2410 * available on its own bus. 2411 */ 2412 if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 2413 res_bus = bus; 2414 while (pci_bus_res[res_bus].subtractive) { 2415 res_bus = pci_bus_res[res_bus].par_bus; 2416 if (res_bus == (uchar_t)-1) 2417 break; /* root bus already */ 2418 if (pci_bus_res[res_bus].io_avail) { 2419 io_avail = &pci_bus_res 2420 [res_bus].io_avail; 2421 break; 2422 } 2423 } 2424 } 2425 2426 /* 2427 * first pass - gather what's there 2428 * update/second pass - adjust/allocate regions 2429 * config - allocate regions 2430 */ 2431 if (config_op == CONFIG_INFO) { /* first pass */ 2432 /* take out of the resource map of the bus */ 2433 if (base != 0) { 2434 (void) memlist_remove(io_avail, base, 2435 len); 2436 memlist_insert(io_used, base, len); 2437 } else { 2438 reprogram = 1; 2439 } 2440 pci_bus_res[bus].io_size += len; 2441 } else if ((*io_avail && base == 0) || 2442 pci_bus_res[bus].io_reprogram) { 2443 base = (uint_t)memlist_find(io_avail, len, len); 2444 if (base != 0) { 2445 memlist_insert(io_used, base, len); 2446 /* XXX need to worry about 64-bit? */ 2447 pci_putl(bus, dev, func, offset, 2448 base | type); 2449 base = pci_getl(bus, dev, func, offset); 2450 base &= PCI_BASE_IO_ADDR_M; 2451 } 2452 if (base == 0) { 2453 cmn_err(CE_WARN, "failed to program" 2454 " IO space [%d/%d/%d] BAR@0x%x" 2455 " length 0x%x", 2456 bus, dev, func, offset, len); 2457 } 2458 } 2459 assigned[nasgn].pci_phys_low = base; 2460 nreg++, nasgn++; 2461 2462 } else { 2463 /* memory space */ 2464 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2465 bar_sz = PCI_BAR_SZ_64; 2466 base_hi = pci_getl(bus, dev, func, offset + 4); 2467 phys_hi = PCI_ADDR_MEM64; 2468 } else { 2469 bar_sz = PCI_BAR_SZ_32; 2470 base_hi = 0; 2471 phys_hi = PCI_ADDR_MEM32; 2472 } 2473 2474 /* skip base regs with size of 0 */ 2475 value &= PCI_BASE_M_ADDR_M; 2476 2477 if (value == 0) 2478 continue; 2479 2480 len = ((value ^ (value-1)) + 1) >> 1; 2481 regs[nreg].pci_size_low = 2482 assigned[nasgn].pci_size_low = len; 2483 2484 phys_hi |= (devloc | offset); 2485 if (base & PCI_BASE_PREF_M) 2486 phys_hi |= PCI_PREFETCH_B; 2487 2488 /* 2489 * A device under a subtractive PPB can allocate 2490 * resources from its parent bus if there is no resource 2491 * available on its own bus. 2492 */ 2493 if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 2494 res_bus = bus; 2495 while (pci_bus_res[res_bus].subtractive) { 2496 res_bus = pci_bus_res[res_bus].par_bus; 2497 if (res_bus == (uchar_t)-1) 2498 break; /* root bus already */ 2499 mem_avail = 2500 &pci_bus_res[res_bus].mem_avail; 2501 pmem_avail = 2502 &pci_bus_res [res_bus].pmem_avail; 2503 /* 2504 * Break out as long as at least 2505 * mem_avail is available 2506 */ 2507 if ((*pmem_avail && 2508 (phys_hi & PCI_PREFETCH_B)) || 2509 *mem_avail) 2510 break; 2511 } 2512 } 2513 2514 regs[nreg].pci_phys_hi = 2515 assigned[nasgn].pci_phys_hi = phys_hi; 2516 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2517 assigned[nasgn].pci_phys_mid = base_hi; 2518 type = base & ~PCI_BASE_M_ADDR_M; 2519 base &= PCI_BASE_M_ADDR_M; 2520 2521 if (config_op == CONFIG_INFO) { 2522 /* take out of the resource map of the bus */ 2523 if (base != NULL) { 2524 /* remove from PMEM and MEM space */ 2525 (void) memlist_remove(mem_avail, 2526 base, len); 2527 (void) memlist_remove(pmem_avail, 2528 base, len); 2529 /* only note as used in correct map */ 2530 if (phys_hi & PCI_PREFETCH_B) 2531 memlist_insert(pmem_used, 2532 base, len); 2533 else 2534 memlist_insert(mem_used, 2535 base, len); 2536 } else { 2537 reprogram = 1; 2538 } 2539 pci_bus_res[bus].mem_size += len; 2540 } else if ((*mem_avail && base == NULL) || 2541 pci_bus_res[bus].mem_reprogram) { 2542 /* 2543 * When desired, attempt a prefetchable 2544 * allocation first 2545 */ 2546 if (phys_hi & PCI_PREFETCH_B) { 2547 base = (uint_t)memlist_find(pmem_avail, 2548 len, len); 2549 if (base != NULL) { 2550 memlist_insert(pmem_used, 2551 base, len); 2552 (void) memlist_remove(mem_avail, 2553 base, len); 2554 } 2555 } 2556 /* 2557 * If prefetchable allocation was not 2558 * desired, or failed, attempt ordinary 2559 * memory allocation 2560 */ 2561 if (base == NULL) { 2562 base = (uint_t)memlist_find(mem_avail, 2563 len, len); 2564 if (base != NULL) { 2565 memlist_insert(mem_used, 2566 base, len); 2567 (void) memlist_remove( 2568 pmem_avail, base, len); 2569 } 2570 } 2571 if (base != NULL) { 2572 pci_putl(bus, dev, func, offset, 2573 base | type); 2574 base = pci_getl(bus, dev, func, offset); 2575 base &= PCI_BASE_M_ADDR_M; 2576 } else 2577 cmn_err(CE_WARN, "failed to program " 2578 "mem space [%d/%d/%d] BAR@0x%x" 2579 " length 0x%x", 2580 bus, dev, func, offset, len); 2581 } 2582 assigned[nasgn].pci_phys_low = base; 2583 nreg++, nasgn++; 2584 } 2585 } 2586 switch (header) { 2587 case PCI_HEADER_ZERO: 2588 offset = PCI_CONF_ROM; 2589 break; 2590 case PCI_HEADER_PPB: 2591 offset = PCI_BCNF_ROM; 2592 break; 2593 default: /* including PCI_HEADER_CARDBUS */ 2594 goto done; 2595 } 2596 2597 /* 2598 * Add the expansion rom memory space 2599 * Determine the size of the ROM base reg; don't write reserved bits 2600 * ROM isn't in the PCI memory space. 2601 */ 2602 base = pci_getl(bus, dev, func, offset); 2603 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2604 value = pci_getl(bus, dev, func, offset); 2605 pci_putl(bus, dev, func, offset, base); 2606 if (value & PCI_BASE_ROM_ENABLE) 2607 value &= PCI_BASE_ROM_ADDR_M; 2608 else 2609 value = 0; 2610 2611 if (value != 0) { 2612 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2613 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2614 PCI_ADDR_MEM32 | devloc) + offset; 2615 base &= PCI_BASE_ROM_ADDR_M; 2616 assigned[nasgn].pci_phys_low = base; 2617 len = ((value ^ (value-1)) + 1) >> 1; 2618 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2619 nreg++, nasgn++; 2620 /* take it out of the memory resource */ 2621 if (base != NULL) { 2622 (void) memlist_remove(mem_avail, base, len); 2623 memlist_insert(mem_used, base, len); 2624 pci_bus_res[bus].mem_size += len; 2625 } 2626 } 2627 2628 /* 2629 * Account for "legacy" (alias) video adapter resources 2630 */ 2631 2632 /* add the three hard-decode, aliased address spaces for VGA */ 2633 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2634 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2635 2636 /* VGA hard decode 0x3b0-0x3bb */ 2637 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2638 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2639 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2640 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2641 nreg++, nasgn++; 2642 (void) memlist_remove(io_avail, 0x3b0, 0xc); 2643 memlist_insert(io_used, 0x3b0, 0xc); 2644 pci_bus_res[bus].io_size += 0xc; 2645 2646 /* VGA hard decode 0x3c0-0x3df */ 2647 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2648 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2649 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2650 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2651 nreg++, nasgn++; 2652 (void) memlist_remove(io_avail, 0x3c0, 0x20); 2653 memlist_insert(io_used, 0x3c0, 0x20); 2654 pci_bus_res[bus].io_size += 0x20; 2655 2656 /* Video memory */ 2657 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2658 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 2659 regs[nreg].pci_phys_low = 2660 assigned[nasgn].pci_phys_low = 0xa0000; 2661 regs[nreg].pci_size_low = 2662 assigned[nasgn].pci_size_low = 0x20000; 2663 nreg++, nasgn++; 2664 /* remove from MEM and PMEM space */ 2665 (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 2666 (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 2667 memlist_insert(mem_used, 0xa0000, 0x20000); 2668 pci_bus_res[bus].mem_size += 0x20000; 2669 } 2670 2671 /* add the hard-decode, aliased address spaces for 8514 */ 2672 if ((baseclass == PCI_CLASS_DISPLAY) && 2673 (subclass == PCI_DISPLAY_VGA) && 2674 (progclass & PCI_DISPLAY_IF_8514)) { 2675 2676 /* hard decode 0x2e8 */ 2677 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2678 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2679 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2680 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2681 nreg++, nasgn++; 2682 (void) memlist_remove(io_avail, 0x2e8, 0x1); 2683 memlist_insert(io_used, 0x2e8, 0x1); 2684 pci_bus_res[bus].io_size += 0x1; 2685 2686 /* hard decode 0x2ea-0x2ef */ 2687 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2688 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2689 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2690 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2691 nreg++, nasgn++; 2692 (void) memlist_remove(io_avail, 0x2ea, 0x6); 2693 memlist_insert(io_used, 0x2ea, 0x6); 2694 pci_bus_res[bus].io_size += 0x6; 2695 } 2696 2697 done: 2698 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2699 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2700 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2701 "assigned-addresses", 2702 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2703 2704 return (reprogram); 2705 } 2706 2707 static void 2708 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2709 int pciex, ushort_t is_pci_bridge) 2710 { 2711 char *dev_type; 2712 int i; 2713 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 2714 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2715 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2716 uchar_t progclass; 2717 2718 ASSERT(secbus <= subbus); 2719 2720 /* 2721 * Check if it's a subtractive PPB. 2722 */ 2723 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2724 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2725 pci_bus_res[secbus].subtractive = B_TRUE; 2726 2727 /* 2728 * Some BIOSes lie about max pci busses, we allow for 2729 * such mistakes here 2730 */ 2731 if (subbus > pci_bios_maxbus) { 2732 pci_bios_maxbus = subbus; 2733 alloc_res_array(); 2734 } 2735 2736 ASSERT(pci_bus_res[secbus].dip == NULL); 2737 pci_bus_res[secbus].dip = dip; 2738 pci_bus_res[secbus].par_bus = bus; 2739 2740 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 2741 2742 /* setup bus number hierarchy */ 2743 pci_bus_res[secbus].sub_bus = subbus; 2744 /* 2745 * Keep track of the largest subordinate bus number (this is essential 2746 * for peer busses because there is no other way of determining its 2747 * subordinate bus number). 2748 */ 2749 if (subbus > pci_bus_res[bus].sub_bus) 2750 pci_bus_res[bus].sub_bus = subbus; 2751 /* 2752 * Loop through subordinate busses, initializing their parent bus 2753 * field to this bridge's parent. The subordinate busses' parent 2754 * fields may very well be further refined later, as child bridges 2755 * are enumerated. (The value is to note that the subordinate busses 2756 * are not peer busses by changing their par_bus fields to anything 2757 * other than -1.) 2758 */ 2759 for (i = secbus + 1; i <= subbus; i++) 2760 pci_bus_res[i].par_bus = bus; 2761 2762 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2763 "device_type", dev_type); 2764 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2765 "#address-cells", 3); 2766 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2767 "#size-cells", 2); 2768 2769 /* 2770 * Collect bridge window specifications, and use them to populate 2771 * the "avail" resources for the bus. Not all of those resources will 2772 * end up being available; this is done top-down, and so the initial 2773 * collection of windows populates the 'ranges' property for the 2774 * bus node. Later, as children are found, resources are removed from 2775 * the 'avail' list, so that it becomes the freelist for 2776 * this point in the tree. ranges may be set again after bridge 2777 * reprogramming in fix_ppb_res(), in which case it's set from 2778 * used + avail. 2779 * 2780 * According to PPB spec, the base register should be programmed 2781 * with a value bigger than the limit register when there are 2782 * no resources available. This applies to io, memory, and 2783 * prefetchable memory. 2784 */ 2785 2786 /* 2787 * io range 2788 * We determine i/o windows that are left unconfigured by BIOS 2789 * through its i/o enable bit as Microsoft recommends OEMs to do. 2790 * If it is unset, we disable i/o and mark it for reconfiguration in 2791 * later passes by setting the base > limit 2792 */ 2793 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2794 if (val & PCI_COMM_IO) { 2795 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2796 io_range[0] = ((val & 0xf0) << 8); 2797 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2798 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 2799 } else { 2800 io_range[0] = 0x9fff; 2801 io_range[1] = 0x1000; 2802 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2803 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2804 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2805 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2806 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2807 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2808 } 2809 2810 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2811 memlist_insert(&pci_bus_res[secbus].io_avail, 2812 (uint64_t)io_range[0], 2813 (uint64_t)(io_range[1] - io_range[0] + 1)); 2814 memlist_insert(&pci_bus_res[bus].io_used, 2815 (uint64_t)io_range[0], 2816 (uint64_t)(io_range[1] - io_range[0] + 1)); 2817 if (pci_bus_res[bus].io_avail != NULL) { 2818 (void) memlist_remove(&pci_bus_res[bus].io_avail, 2819 (uint64_t)io_range[0], 2820 (uint64_t)(io_range[1] - io_range[0] + 1)); 2821 } 2822 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 2823 secbus, io_range[0], io_range[1]); 2824 /* if 32-bit supported, make sure upper bits are not set */ 2825 if ((val & 0xf) == 1 && 2826 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 2827 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 2828 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2829 } 2830 } 2831 2832 /* mem range */ 2833 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2834 mem_range[0] = ((val & 0xFFF0) << 16); 2835 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2836 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2837 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2838 memlist_insert(&pci_bus_res[secbus].mem_avail, 2839 (uint64_t)mem_range[0], 2840 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2841 memlist_insert(&pci_bus_res[bus].mem_used, 2842 (uint64_t)mem_range[0], 2843 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2844 /* remove from parent resource list */ 2845 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2846 (uint64_t)mem_range[0], 2847 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2848 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 2849 (uint64_t)mem_range[0], 2850 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2851 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 2852 secbus, mem_range[0], mem_range[1]); 2853 } 2854 2855 /* prefetchable memory range */ 2856 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2857 pmem_range[0] = ((val & 0xFFF0) << 16); 2858 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2859 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2860 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2861 memlist_insert(&pci_bus_res[secbus].pmem_avail, 2862 (uint64_t)pmem_range[0], 2863 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2864 memlist_insert(&pci_bus_res[bus].pmem_used, 2865 (uint64_t)pmem_range[0], 2866 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2867 /* remove from parent resource list */ 2868 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 2869 (uint64_t)pmem_range[0], 2870 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2871 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2872 (uint64_t)pmem_range[0], 2873 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2874 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 2875 secbus, pmem_range[0], pmem_range[1]); 2876 /* if 64-bit supported, make sure upper bits are not set */ 2877 if ((val & 0xf) == 1 && 2878 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 2879 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 2880 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2881 } 2882 } 2883 2884 /* 2885 * Add VGA legacy resources to the bridge's pci_bus_res if it 2886 * has VGA_ENABLE set. Note that we put them in 'avail', 2887 * because that's used to populate the ranges prop; they'll be 2888 * removed from there by the VGA device once it's found. Also, 2889 * remove them from the parent's available list and note them as 2890 * used in the parent. 2891 */ 2892 2893 if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 2894 PCI_BCNF_BCNTRL_VGA_ENABLE) { 2895 2896 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 2897 2898 memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 2899 if (pci_bus_res[bus].io_avail != NULL) { 2900 (void) memlist_remove(&pci_bus_res[bus].io_avail, 2901 0x3b0, 0xc); 2902 } 2903 2904 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 2905 2906 memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 2907 if (pci_bus_res[bus].io_avail != NULL) { 2908 (void) memlist_remove(&pci_bus_res[bus].io_avail, 2909 0x3c0, 0x20); 2910 } 2911 2912 memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 2913 0x20000); 2914 2915 memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 2916 if (pci_bus_res[bus].mem_avail != NULL) { 2917 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2918 0xa0000, 0x20000); 2919 } 2920 } 2921 add_bus_range_prop(secbus); 2922 add_ranges_prop(secbus, 1); 2923 } 2924 2925 extern const struct pci_class_strings_s class_pci[]; 2926 extern int class_pci_items; 2927 2928 static void 2929 add_model_prop(dev_info_t *dip, uint_t classcode) 2930 { 2931 const char *desc; 2932 int i; 2933 uchar_t baseclass = classcode >> 16; 2934 uchar_t subclass = (classcode >> 8) & 0xff; 2935 uchar_t progclass = classcode & 0xff; 2936 2937 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 2938 desc = "IDE controller"; 2939 } else { 2940 for (desc = 0, i = 0; i < class_pci_items; i++) { 2941 if ((baseclass == class_pci[i].base_class) && 2942 (subclass == class_pci[i].sub_class) && 2943 (progclass == class_pci[i].prog_class)) { 2944 desc = class_pci[i].actual_desc; 2945 break; 2946 } 2947 } 2948 if (i == class_pci_items) 2949 desc = "Unknown class of pci/pnpbios device"; 2950 } 2951 2952 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2953 (char *)desc); 2954 } 2955 2956 static void 2957 add_bus_range_prop(int bus) 2958 { 2959 int bus_range[2]; 2960 2961 if (pci_bus_res[bus].dip == NULL) 2962 return; 2963 bus_range[0] = bus; 2964 bus_range[1] = pci_bus_res[bus].sub_bus; 2965 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2966 "bus-range", (int *)bus_range, 2); 2967 } 2968 2969 /* 2970 * Add slot-names property for any named pci hot-plug slots 2971 */ 2972 static void 2973 add_bus_slot_names_prop(int bus) 2974 { 2975 char slotprop[256]; 2976 int len; 2977 2978 if (pci_bus_res[bus].dip != NULL) { 2979 /* simply return if the property is already defined */ 2980 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2981 DDI_PROP_DONTPASS, "slot-names")) 2982 return; 2983 } 2984 2985 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2986 if (len > 0) { 2987 /* 2988 * Only create a peer bus node if this bus may be a peer bus. 2989 * It may be a peer bus if the dip is NULL and if par_bus is 2990 * -1 (par_bus is -1 if this bus was not found to be 2991 * subordinate to any PCI-PCI bridge). 2992 * If it's not a peer bus, then the ACPI BBN-handling code 2993 * will remove it later. 2994 */ 2995 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 2996 pci_bus_res[bus].dip == NULL) { 2997 2998 create_root_bus_dip(bus); 2999 } 3000 if (pci_bus_res[bus].dip != NULL) { 3001 ASSERT((len % sizeof (int)) == 0); 3002 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3003 pci_bus_res[bus].dip, "slot-names", 3004 (int *)slotprop, len / sizeof (int)); 3005 } else { 3006 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 3007 "IRQ routing table; Not adding slot-names " 3008 "property for incorrect bus %d", bus); 3009 } 3010 } 3011 } 3012 3013 /* 3014 * Handle both PCI root and PCI-PCI bridge range properties; 3015 * non-zero 'ppb' argument select PCI-PCI bridges versus root. 3016 */ 3017 static void 3018 memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 3019 { 3020 ppb_ranges_t *ppb_rp = *rp; 3021 pci_ranges_t *pci_rp = *rp; 3022 3023 while (entry != NULL) { 3024 if (ppb) { 3025 ppb_rp->child_high = ppb_rp->parent_high = type; 3026 ppb_rp->child_mid = ppb_rp->parent_mid = 3027 (uint32_t)(entry->address >> 32); /* XXX */ 3028 ppb_rp->child_low = ppb_rp->parent_low = 3029 (uint32_t)entry->address; 3030 ppb_rp->size_high = 3031 (uint32_t)(entry->size >> 32); /* XXX */ 3032 ppb_rp->size_low = (uint32_t)entry->size; 3033 *rp = ++ppb_rp; 3034 } else { 3035 pci_rp->child_high = type; 3036 pci_rp->child_mid = pci_rp->parent_high = 3037 (uint32_t)(entry->address >> 32); /* XXX */ 3038 pci_rp->child_low = pci_rp->parent_low = 3039 (uint32_t)entry->address; 3040 pci_rp->size_high = 3041 (uint32_t)(entry->size >> 32); /* XXX */ 3042 pci_rp->size_low = (uint32_t)entry->size; 3043 *rp = ++pci_rp; 3044 } 3045 entry = entry->next; 3046 } 3047 } 3048 3049 static void 3050 add_ranges_prop(int bus, int ppb) 3051 { 3052 int total, alloc_size; 3053 void *rp, *next_rp; 3054 struct memlist *iolist, *memlist, *pmemlist; 3055 3056 /* no devinfo node - unused bus, return */ 3057 if (pci_bus_res[bus].dip == NULL) 3058 return; 3059 3060 iolist = memlist = pmemlist = (struct memlist *)NULL; 3061 3062 memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 3063 memlist_merge(&pci_bus_res[bus].io_used, &iolist); 3064 memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 3065 memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 3066 memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 3067 memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 3068 3069 total = memlist_count(iolist); 3070 total += memlist_count(memlist); 3071 total += memlist_count(pmemlist); 3072 3073 /* no property is created if no ranges are present */ 3074 if (total == 0) 3075 return; 3076 3077 alloc_size = total * 3078 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 3079 3080 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 3081 3082 memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 3083 memlist_to_ranges(&next_rp, memlist, 3084 PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 3085 memlist_to_ranges(&next_rp, pmemlist, 3086 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 3087 3088 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3089 "ranges", (int *)rp, alloc_size / sizeof (int)); 3090 3091 kmem_free(rp, alloc_size); 3092 memlist_free_all(&iolist); 3093 memlist_free_all(&memlist); 3094 memlist_free_all(&pmemlist); 3095 } 3096 3097 static void 3098 memlist_remove_list(struct memlist **list, struct memlist *remove_list) 3099 { 3100 while (list && *list && remove_list) { 3101 (void) memlist_remove(list, remove_list->address, 3102 remove_list->size); 3103 remove_list = remove_list->next; 3104 } 3105 } 3106 3107 static int 3108 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 3109 { 3110 int i = 0; 3111 3112 while (list) { 3113 /* assume 32-bit addresses */ 3114 sp->pci_phys_hi = type; 3115 sp->pci_phys_mid = 0; 3116 sp->pci_phys_low = (uint32_t)list->address; 3117 sp->pci_size_hi = 0; 3118 sp->pci_size_low = (uint32_t)list->size; 3119 3120 list = list->next; 3121 sp++, i++; 3122 } 3123 return (i); 3124 } 3125 3126 static void 3127 add_bus_available_prop(int bus) 3128 { 3129 int i, count; 3130 struct pci_phys_spec *sp; 3131 3132 /* no devinfo node - unused bus, return */ 3133 if (pci_bus_res[bus].dip == NULL) 3134 return; 3135 3136 count = memlist_count(pci_bus_res[bus].io_avail) + 3137 memlist_count(pci_bus_res[bus].mem_avail) + 3138 memlist_count(pci_bus_res[bus].pmem_avail); 3139 3140 if (count == 0) /* nothing available */ 3141 return; 3142 3143 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 3144 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 3145 PCI_ADDR_IO | PCI_REG_REL_M); 3146 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 3147 PCI_ADDR_MEM32 | PCI_REG_REL_M); 3148 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 3149 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 3150 ASSERT(i == count); 3151 3152 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3153 "available", (int *)sp, 3154 i * sizeof (struct pci_phys_spec) / sizeof (int)); 3155 kmem_free(sp, count * sizeof (*sp)); 3156 } 3157 3158 static void 3159 alloc_res_array(void) 3160 { 3161 static int array_max = 0; 3162 int old_max; 3163 void *old_res; 3164 3165 if (array_max > pci_bios_maxbus + 1) 3166 return; /* array is big enough */ 3167 3168 old_max = array_max; 3169 old_res = pci_bus_res; 3170 3171 if (array_max == 0) 3172 array_max = 16; /* start with a reasonable number */ 3173 3174 while (array_max < pci_bios_maxbus + 1) 3175 array_max <<= 1; 3176 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 3177 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 3178 3179 if (old_res) { /* copy content and free old array */ 3180 bcopy(old_res, pci_bus_res, 3181 old_max * sizeof (struct pci_bus_resource)); 3182 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 3183 } 3184 } 3185 3186 static void 3187 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 3188 ushort_t deviceid) 3189 { 3190 static dev_info_t *ioapicsnode = NULL; 3191 static int numioapics = 0; 3192 dev_info_t *ioapic_node; 3193 uint64_t physaddr; 3194 uint32_t lobase, hibase = 0; 3195 3196 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 3197 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 3198 3199 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 3200 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 3201 return; 3202 3203 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 3204 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 3205 3206 lobase &= PCI_BASE_M_ADDR_M; 3207 3208 physaddr = (((uint64_t)hibase) << 32) | lobase; 3209 3210 /* 3211 * Create a nexus node for all IOAPICs under the root node. 3212 */ 3213 if (ioapicsnode == NULL) { 3214 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 3215 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 3216 return; 3217 } 3218 (void) ndi_devi_online(ioapicsnode, 0); 3219 } 3220 3221 /* 3222 * Create a child node for this IOAPIC 3223 */ 3224 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 3225 DEVI_SID_NODEID, numioapics++); 3226 if (ioapic_node == NULL) { 3227 return; 3228 } 3229 3230 /* Vendor and Device ID */ 3231 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3232 IOAPICS_PROP_VENID, vendorid); 3233 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3234 IOAPICS_PROP_DEVID, deviceid); 3235 3236 /* device_type */ 3237 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 3238 "device_type", IOAPICS_DEV_TYPE); 3239 3240 /* reg */ 3241 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 3242 "reg", physaddr); 3243 } 3244 3245 /* 3246 * NOTE: For PCIe slots, the name is generated from the slot number 3247 * information obtained from Slot Capabilities register. 3248 * For non-PCIe slots, it is generated based on the slot number 3249 * information in the PCI IRQ table. 3250 */ 3251 static void 3252 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 3253 { 3254 char slotprop[256]; 3255 int len; 3256 3257 bzero(slotprop, sizeof (slotprop)); 3258 3259 /* set mask to 1 as there is only one slot (i.e dev 0) */ 3260 *(uint32_t *)slotprop = 1; 3261 len = 4; 3262 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 3263 slot_num); 3264 len += strlen(slotprop + len) + 1; 3265 len += len % 4; 3266 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 3267 (int *)slotprop, len / sizeof (int)); 3268 } 3269