xref: /titanic_50/usr/src/uts/intel/io/pci/mps_table.h (revision ae115bc77f6fcde83175c75b4206dc2e50747966)
1*ae115bc7Smrj /*
2*ae115bc7Smrj  * CDDL HEADER START
3*ae115bc7Smrj  *
4*ae115bc7Smrj  * The contents of this file are subject to the terms of the
5*ae115bc7Smrj  * Common Development and Distribution License, Version 1.0 only
6*ae115bc7Smrj  * (the "License").  You may not use this file except in compliance
7*ae115bc7Smrj  * with the License.
8*ae115bc7Smrj  *
9*ae115bc7Smrj  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*ae115bc7Smrj  * or http://www.opensolaris.org/os/licensing.
11*ae115bc7Smrj  * See the License for the specific language governing permissions
12*ae115bc7Smrj  * and limitations under the License.
13*ae115bc7Smrj  *
14*ae115bc7Smrj  * When distributing Covered Code, include this CDDL HEADER in each
15*ae115bc7Smrj  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*ae115bc7Smrj  * If applicable, add the following below this CDDL HEADER, with the
17*ae115bc7Smrj  * fields enclosed by brackets "[]" replaced with your own identifying
18*ae115bc7Smrj  * information: Portions Copyright [yyyy] [name of copyright owner]
19*ae115bc7Smrj  *
20*ae115bc7Smrj  * CDDL HEADER END
21*ae115bc7Smrj  */
22*ae115bc7Smrj /*
23*ae115bc7Smrj  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24*ae115bc7Smrj  * Use is subject to license terms.
25*ae115bc7Smrj  *
26*ae115bc7Smrj  * mps_table.h -- MP Specification table definitions
27*ae115bc7Smrj  */
28*ae115bc7Smrj 
29*ae115bc7Smrj #ifndef	_MPS_TABLE_H
30*ae115bc7Smrj #define	_MPS_TABLE_H
31*ae115bc7Smrj 
32*ae115bc7Smrj #pragma ident	"%Z%%M%	%I%	%E% SMI"
33*ae115bc7Smrj 
34*ae115bc7Smrj #ifdef	__cplusplus
35*ae115bc7Smrj extern "C" {
36*ae115bc7Smrj #endif
37*ae115bc7Smrj 
38*ae115bc7Smrj 
39*ae115bc7Smrj struct mps_fps_hdr {		/* MP Floating Pointer Structure	*/
40*ae115bc7Smrj 	uint32_t fps_sig;	/* _MP_ (0x5F4D505F)			*/
41*ae115bc7Smrj 	uint32_t fps_mpct_paddr; /* paddr of MP Configuration Table	*/
42*ae115bc7Smrj 	uchar_t	fps_len;	/* in paragraph (16-bytes units)	*/
43*ae115bc7Smrj 	uchar_t	fps_spec_rev;	/* MP Spec. version no.			*/
44*ae115bc7Smrj 	uchar_t	fps_cksum;	/* checksum of complete structure	*/
45*ae115bc7Smrj 	uchar_t	fps_featinfo1;	/* mp feature info byte 1 		*/
46*ae115bc7Smrj 	uchar_t	fps_featinfo2;	/* mp feature info byte 2		*/
47*ae115bc7Smrj 	uchar_t	fps_featinfo3;	/* mp feature info byte 3		*/
48*ae115bc7Smrj 	uchar_t	fps_featinfo4;	/* mp feature info byte 4		*/
49*ae115bc7Smrj 	uchar_t	fps_featinfo5;	/* mp feature info byte 5		*/
50*ae115bc7Smrj };
51*ae115bc7Smrj 
52*ae115bc7Smrj struct mps_ct_hdr {		/* MP Configuration Table Header	*/
53*ae115bc7Smrj 	uint32_t ct_sig;	/* "PCMP"				*/
54*ae115bc7Smrj 	uint16_t ct_len;	/* base configuration in bytes 		*/
55*ae115bc7Smrj 	uchar_t	ct_spec_rev;	/* MP Spec. version no.			*/
56*ae115bc7Smrj 	uchar_t	ct_cksum;	/* base configuration table checksum	*/
57*ae115bc7Smrj 	char	ct_oem_id[8];	/* string identifies the manufacturer	*/
58*ae115bc7Smrj 	char	ct_prod_id[12]; /* string identifies the product	*/
59*ae115bc7Smrj 	uint32_t ct_oem_ptr;	/* paddr to an OEM-defined table	*/
60*ae115bc7Smrj 	uint16_t ct_oem_tbl_len; /* size of base OEM table in bytes	*/
61*ae115bc7Smrj 	uint16_t ct_entry_cnt;	/* no. of entries in the base table	*/
62*ae115bc7Smrj 	uint32_t ct_local_apic;	/* paddr of local APIC			*/
63*ae115bc7Smrj 	uint16_t ct_ext_tbl_len; /* extended table in bytes 		*/
64*ae115bc7Smrj 	uchar_t	ct_ext_cksum;	/* checksum for the extended table	*/
65*ae115bc7Smrj };
66*ae115bc7Smrj 
67*ae115bc7Smrj /* Base MP Configuration Table entry type definitions */
68*ae115bc7Smrj #define	CPU_TYPE	0
69*ae115bc7Smrj #define	BUS_TYPE	1
70*ae115bc7Smrj #define	IO_APIC_TYPE	2
71*ae115bc7Smrj #define	IO_INTR_TYPE	3
72*ae115bc7Smrj #define	LOCAL_INTR_TYPE	4
73*ae115bc7Smrj 
74*ae115bc7Smrj /* Base MP Configuration Table entry size definitions */
75*ae115bc7Smrj #define	CPU_SIZE	20
76*ae115bc7Smrj #define	BUS_SIZE	8
77*ae115bc7Smrj #define	IO_APIC_SIZE	8
78*ae115bc7Smrj #define	IO_INTR_SIZE	8
79*ae115bc7Smrj #define	LOCAL_INTR_SIZE	8
80*ae115bc7Smrj 
81*ae115bc7Smrj /* Extended MP Configuration Table entry type definitions */
82*ae115bc7Smrj #define	SYS_AS_MAPPING		128
83*ae115bc7Smrj #define	BUS_HIERARCHY_DESC	129
84*ae115bc7Smrj #define	COMP_BUS_AS_MODIFIER	130
85*ae115bc7Smrj 
86*ae115bc7Smrj /* Extended MP Configuration Table entry size definitions */
87*ae115bc7Smrj #define	SYS_AS_MAPPING_SIZE		20
88*ae115bc7Smrj #define	BUS_HIERARCHY_DESC_SIZE		8
89*ae115bc7Smrj #define	COMP_BUS_AS_MODIFIER_SIZE	8
90*ae115bc7Smrj 
91*ae115bc7Smrj struct sasm {			/* System Address Space Mapping Entry	*/
92*ae115bc7Smrj 	uchar_t sasm_type;	/* type 128				*/
93*ae115bc7Smrj 	uchar_t sasm_len;	/* entry length in bytes (20)		*/
94*ae115bc7Smrj 	uchar_t sasm_bus_id;	/* bus id where this is mapped		*/
95*ae115bc7Smrj 	uchar_t sasm_as_type;	/* system address type			*/
96*ae115bc7Smrj /* system address type definitions */
97*ae115bc7Smrj #define	IO_TYPE		0
98*ae115bc7Smrj #define	MEM_TYPE	1
99*ae115bc7Smrj #define	PREFETCH_TYPE	2
100*ae115bc7Smrj #define	BUSRANGE_TYPE	3
101*ae115bc7Smrj 	uint32_t sasm_as_base;	/* starting address			*/
102*ae115bc7Smrj 	uint32_t sasm_as_base_hi;
103*ae115bc7Smrj 	uint32_t sasm_as_len;	/* no. of addresses visiblie to the bus	*/
104*ae115bc7Smrj 	uint32_t sasm_as_len_hi;
105*ae115bc7Smrj };
106*ae115bc7Smrj 
107*ae115bc7Smrj struct bhd {			/* Bus Hierarchy Descriptor Entry	*/
108*ae115bc7Smrj 	uchar_t bhd_type;	/* type 129				*/
109*ae115bc7Smrj 	uchar_t bhd_len;	/* entry length in bytes (8)		*/
110*ae115bc7Smrj 	uchar_t bhd_bus_id;	/* bus id of this bus			*/
111*ae115bc7Smrj 	uchar_t bhd_bus_info;	/* bus information			*/
112*ae115bc7Smrj /* Bus Information bit definition */
113*ae115bc7Smrj #define	BHD_BUS_INFO_SD	1	/* Subtractive Decode Bus		*/
114*ae115bc7Smrj 	uchar_t bhd_parent;
115*ae115bc7Smrj };
116*ae115bc7Smrj 
117*ae115bc7Smrj struct cbasm {	/* Compatibility Bus Address Space Modifier Entry */
118*ae115bc7Smrj 	uchar_t cbasm_type;	/* type 130				*/
119*ae115bc7Smrj 	uchar_t cbasm_len;	/* entry length in bytes (8)		*/
120*ae115bc7Smrj 	uchar_t cbasm_bus_id;	/* bus to be modified			*/
121*ae115bc7Smrj 	uchar_t cbasm_addr_mod;	/* address modifier			*/
122*ae115bc7Smrj /* Address Modifier bit definiton */
123*ae115bc7Smrj #define	CBASM_ADDR_MOD_PR	1	/* 1 = subtracted, 0 = added */
124*ae115bc7Smrj 	uint32_t cbasm_pr_list;	/* identify list of predefined address ranges */
125*ae115bc7Smrj };
126*ae115bc7Smrj 
127*ae115bc7Smrj #ifdef	__cplusplus
128*ae115bc7Smrj }
129*ae115bc7Smrj #endif
130*ae115bc7Smrj 
131*ae115bc7Smrj #endif	/* _MPS_TABLE_H */
132