1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NB5000_H 28 #define _NB5000_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/cpu_module.h> 35 36 #define NB_5000_MAX_MEM_CONTROLLERS 2 37 #define NB_MAX_DIMMS_PER_CHANNEL (nb_chipset == INTEL_NB_7300 ? 8 : 4) 38 #define NB_MEM_BRANCH_SELECT (nb_chipset == INTEL_NB_5400 ? 2 : 3) 39 #define NB_MAX_MEM_BRANCH_SELECT 3 40 #define NB_MEM_RANK_SELECT (nb_chipset == INTEL_NB_7300 ? 7 : 5) 41 #define NB_MAX_MEM_RANK_SELECT 7 42 #define NB_RANKS_IN_SELECT 4 43 #define NB_PCI_DEV 10 44 45 #define NB_PCI_NFUNC 4 46 47 #define DOCMD_PEX_MASK 0x00 48 #define DOCMD_5400_PEX_MASK 0x000 49 #define DOCMD_PEX 0xf0 50 #define DOCMD_5400_PEX 0xff0 51 52 #define SPD_BUSY 0x1000 53 #define SPD_BUS_ERROR 0x2000 54 #define SPD_READ_DATA_VALID 0x8000 55 #define SPD_EEPROM_WRITE 0xa8000000 56 #define SPD_ADDR(slave, addr) ((((slave) & 7) << 24) | (((addr) & 0xff) << 16)) 57 58 #define MC_MIRROR 0x10000 59 #define MC_PATROL_SCRUB 0x80 60 #define MC_DEMAND_SCRUB 0x40 61 62 #define MCA_SCHDIMM 0x4000 63 64 #define TLOW_MAX 0x100000000ULL 65 66 #define MTR_PRESENT(mtr) \ 67 ((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0400 : 0x0100)) 68 #define MTR_ETHROTTLE(mtr) \ 69 ((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0200 : 0x0080)) 70 #define MTR_WIDTH(mtr) \ 71 (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0100 : 0x0040)) ? 8 : 4) 72 #define MTR_NUMBANK(mtr) \ 73 (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0040 : 0x0020)) ? 8 : 4) 74 #define MTR_NUMRANK(mtr) \ 75 (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0020 : 0x0010)) ? 2 : 1) 76 #define MTR_NUMROW(mtr) ((((mtr) >> 2) & 3) + 13) 77 #define MTR_NUMCOL(mtr) (((mtr) & 3) + 10) 78 79 #define MTR_DIMMSIZE(mtr) ((1ULL << (MTR_NUMCOL(mtr) + MTR_NUMROW(mtr))) \ 80 * MTR_NUMRANK(mtr) * MTR_NUMBANK(mtr) * MTR_WIDTH(mtr)) 81 82 /* FERR_GLOBAL and NERR_GLOBAL */ 83 #define GE_FERR_FSB3_FATAL 0x800000000ULL /* FSB3 Fatal Error */ 84 #define GE_FERR_FSB2_FATAL 0x400000000ULL /* FSB2 Fatal Error */ 85 #define GE_FERR_FSB3_NF 0x200000000ULL /* FSB3 Non-Fatal Error */ 86 #define GE_FERR_FSB2_NF 0x100000000ULL /* FSB2 Non-Fatal Error */ 87 88 #define GE_INT_FATAL 0x80000000 /* North Bridge Internal Error */ 89 #define GE_DMA_FATAL 0x40000000 /* DMA engine Fatal Error */ 90 #define GE_FSB1_FATAL 0x20000000 /* FSB1 Fatal Error */ 91 #define GE_FSB0_FATAL 0x10000000 /* FSB0 Fatal Error */ 92 #define GE_FERR_FBD_FATAL 0x08000000 /* FBD channel Fatal Error */ 93 #define GE_FERR_FBD3_FATAL 0x08000000 /* FBD3 channel Fatal Error */ 94 #define GE_FERR_FBD2_FATAL 0x04000000 /* FBD2 channel Fatal Error */ 95 #define GE_FERR_FBD1_FATAL 0x02000000 /* FBD1 channel Fatal Error */ 96 #define GE_FERR_FBD0_FATAL 0x01000000 /* FBD0 channel Fatal Error */ 97 #define GE_FERR_THERMAL_FATAL 0x04000000 /* Thermal Fatal Error */ 98 #define GE_PCIEX9_FATAL 0x02000000 /* PCI Express device 9 Fatal Error */ 99 #define GE_PCIEX8_FATAL 0x01000000 /* PCI Express device 8 Fatal Error */ 100 #define GE_PCIEX7_FATAL 0x00800000 /* PCI Express device 7 Fatal Error */ 101 #define GE_PCIEX6_FATAL 0x00400000 /* PCI Express device 6 Fatal Error */ 102 #define GE_PCIEX5_FATAL 0x00200000 /* PCI Express device 5 Fatal Error */ 103 #define GE_PCIEX4_FATAL 0x00100000 /* PCI Express device 4 Fatal Error */ 104 #define GE_PCIEX3_FATAL 0x00080000 /* PCI Express device 3 Fatal Error */ 105 #define GE_PCIEX2_FATAL 0x00040000 /* PCI Express device 2 Fatal Error */ 106 #define GE_PCIEX1_FATAL 0x00020000 /* PCI Express device 1 Fatal Error */ 107 #define GE_ESI_FATAL 0x00010000 /* ESI Fatal Error */ 108 #define GE_INT_NF 0x00008000 /* North Bridge Internal Error */ 109 #define GE_DMA_NF 0x00004000 /* DMA engine Non-Fatal Error */ 110 #define GE_FSB1_NF 0x00002000 /* FSB1 Non-Fatal Error */ 111 #define GE_FSB0_NF 0x00001000 /* FSB0 Non-Fatal Error */ 112 #define GE_FERR_FBD3_NF 0x00000800 /* FBD channel 3 Non-Fatal Error */ 113 #define GE_FERR_FBD2_NF 0x00000400 /* FBD channel 2 Non-Fatal Error */ 114 #define GE_FERR_FBD1_NF 0x00000200 /* FBD channel 1 Non-Fatal Error */ 115 #define GE_FERR_FBD0_NF 0x00000100 /* FBD channel 0 Non-Fatal Error */ 116 #define GE_FERR_FBD_NF 0x00000800 /* FBD channel Non-Fatal Error */ 117 #define GE_FERR_THERMAL_NF 0x00000400 /* Thermal Non-Fatal Error */ 118 #define GE_PCIEX9_NF 0x00000200 /* PCI Express dev 9 Non-Fatal Error */ 119 #define GE_PCIEX8_NF 0x00000100 /* PCI Express dev 8 Non-Fatal Error */ 120 #define GE_PCIEX7_NF 0x00000080 /* PCI Express dev 7 Non-Fatal Error */ 121 #define GE_PCIEX6_NF 0x00000040 /* PCI Express dev 6 Non-Fatal Error */ 122 #define GE_PCIEX5_NF 0x00000020 /* PCI Express dev 5 Non-Fatal Error */ 123 #define GE_PCIEX4_NF 0x00000010 /* PCI Express dev 4 Non-Fatal Error */ 124 #define GE_PCIEX3_NF 0x00000008 /* PCI Express dev 3 Non-Fatal Error */ 125 #define GE_PCIEX2_NF 0x00000004 /* PCI Express dev 2 Non-Fatal Error */ 126 #define GE_PCIEX1_NF 0x00000002 /* PCI Express dev 1 Non-Fatal Error */ 127 #define GE_ESI_NF 0x00000001 /* ESI Non-Fatal Error */ 128 129 #define GE_NERR_FSB2_FATAL 0x08000000 /* FSB2 Fatal Error */ 130 #define GE_NERR_FSB3_FATAL 0x04000000 /* FSB3 Fatal Error */ 131 #define GE_NERR_FBD_FATAL 0x01000000 /* FBD channel Fatal Error */ 132 #define GE_NERR_FSB2_NF 0x00000800 /* FSB2 Non-Fatal Error */ 133 #define GE_NERR_FSB3_NF 0x00000400 /* FSB3 Non-Fatal Error */ 134 #define GE_NERR_FBD_NF 0x00000100 /* FBD channel Non-Fatal Error */ 135 136 #define ERR_FAT_FSB_F9 0x20 /* F9Msk FSB Protocol */ 137 #define ERR_FAT_FSB_F2 0x08 /* F2Msk Unsupported Bus Transaction */ 138 #define ERR_FAT_FSB_F1 0x01 /* F1Msk Request/Address Parity */ 139 140 #define ERR_NF_FSB_F7 0x04 /* F7Msk Detected MCERR */ 141 #define ERR_NF_FSB_F8 0x02 /* F8Msk B-INIT */ 142 #define ERR_NF_FSB_F6 0x01 /* F6Msk Data Parity */ 143 144 #define EMASK_FSB_F1 0x0001 /* F1Msk Request/Address Parity */ 145 #define EMASK_FSB_F2 0x0002 /* F2Msk Unsupported Bus Transaction */ 146 #define EMASK_FSB_F6 0x0020 /* F6Msk Data Parity */ 147 #define EMASK_FSB_F7 0x0040 /* F7Msk Detected MCERR */ 148 #define EMASK_FSB_F8 0x0080 /* F8Msk B-INIT */ 149 #define EMASK_FSB_F9 0x0100 /* F9Msk FSB Protocol */ 150 151 #define EMASK_FSB_FATAL (EMASK_FSB_F1 | EMASK_FSB_F2 | EMASK_FSB_F9) 152 #define EMASK_FSB_NF (EMASK_FSB_F6 | EMASK_FSB_F7 | EMASK_FSB_F8) 153 154 #define ERR_FBD_CH_SHIFT 28 /* channel index in fat_fbd and nf_fbd */ 155 156 #define ERR_FAT_FBD_M23 0x00400000 /* M23Err Non-Redundant Fast Reset */ 157 /* Timeout */ 158 #define ERR_FAT_FBD_M3 0x00000004 /* M3Err >Tmid thermal event with */ 159 /* intelligent throttling disabled */ 160 #define ERR_FAT_FBD_M2 0x00000002 /* M2Err memory or FBD configuration */ 161 /* CRC read error */ 162 #define ERR_FAT_FBD_M1 0x00000001 /* M1Err memory write error on */ 163 /* non-redundant retry or FBD */ 164 /* configuration write error on retry */ 165 #define ERR_FAT_FBD_MASK 0x007fffff 166 167 #define ERR_NF_FBD_M29 0x02000000 /* M29Err DIMM-Isolation Completed */ 168 #define ERR_NF_FBD_M28 0x01000000 /* M28Err DIMM-Spare Copy Completed */ 169 #define ERR_NF_FBD_M27 0x00800000 /* M27Err DIMM-Spare Copy Initiated */ 170 #define ERR_NF_FBD_M26 0x00400000 /* M26Err Redundant Fast Reset */ 171 /* Timeout */ 172 #define ERR_NF_FBD_M25 0x00200000 /* M25Err Memory write error on */ 173 #define ERR_NF_FBD_M24 0x00100000 /* M24Err refresh error */ 174 /* redundant retry */ 175 #define ERR_NF_FBD_M22 0x00040000 /* M22Err SPD protocol */ 176 #define ERR_NF_FBD_M21 0x00020000 /* M21Err FBD Northbound parity on */ 177 /* FBD sync status */ 178 #define ERR_NF_FBD_M20 0x00010000 /* M20Err Correctable patrol data ECC */ 179 #define ERR_NF_FBD_M19 0x00008000 /* M19Err Correctasble resilver or */ 180 /* spare-copy data ECC */ 181 #define ERR_NF_FBD_M18 0x00004000 /* M18Err Correctable Mirrored demand */ 182 /* data ECC */ 183 #define ERR_NF_FBD_M17 0x00002000 /* M17Err Correctable Non-mirrored */ 184 /* demand data ECC */ 185 #define ERR_NF_FBD_M16 0x00001000 /* M16Err channel failed over */ 186 #define ERR_NF_FBD_M15 0x00000800 /* M15Err Memory or FBD configuration */ 187 /* CRC read error */ 188 #define ERR_NF_FBD_M14 0x00000400 /* M14Err FBD configuration write */ 189 /* error on first attempt */ 190 #define ERR_NF_FBD_M13 0x00000200 /* M13Err Memory write error on first */ 191 /* attempt */ 192 #define ERR_NF_FBD_M12 0x00000100 /* M12Err Non-Aliased uncorrectable */ 193 /* patrol data ECC */ 194 #define ERR_NF_FBD_M11 0x00000080 /* M11Err Non-Aliased uncorrectable */ 195 /* resilver or spare copy data ECC */ 196 #define ERR_NF_FBD_M10 0x00000040 /* M10Err Non-Aliased uncorrectable */ 197 /* mirrored demand data ECC */ 198 #define ERR_NF_FBD_M9 0x00000020 /* M9Err Non-Aliased uncorrectable */ 199 /* non-mirrored demand data ECC */ 200 #define ERR_NF_FBD_M8 0x00000010 /* M8Err Aliased uncorrectable */ 201 /* patrol data ECC */ 202 #define ERR_NF_FBD_M7 0x00000008 /* M7Err Aliased uncorrectable */ 203 /* resilver or spare copy data ECC */ 204 #define ERR_NF_FBD_M6 0x00000004 /* M6Err Aliased uncorrectable */ 205 /* mirrored demand data ECC */ 206 #define ERR_NF_FBD_M5 0x00000002 /* M5Err Aliased uncorrectable */ 207 /* non-mirrored demand data ECC */ 208 #define ERR_NF_FBD_M4 0x00000001 /* M4Err uncorrectable data ECC on */ 209 /* replay */ 210 211 #define ERR_NF_FBD_MASK 0x01ffffff 212 #define ERR_NF_FBD_ECC_UE (ERR_NF_FBD_M12|ERR_NF_FBD_M11|ERR_NF_FBD_M10| \ 213 ERR_NF_FBD_M9|ERR_NF_FBD_M8|ERR_NF_FBD_M7|ERR_NF_FBD_M6|ERR_NF_FBD_M5| \ 214 ERR_NF_FBD_M4) 215 #define ERR_NF_FBD_MA (ERR_NF_FBD_M14) 216 #define ERR_NF_FBD_ECC_CE (ERR_NF_FBD_M20|ERR_NF_FBD_M19|ERR_NF_FBD_M18| \ 217 ERR_NF_FBD_M17|ERR_NF_FBD_M15|ERR_NF_FBD_M21) 218 #define ERR_NF_FBD_SPARE (ERR_NF_FBD_M28|ERR_NF_FBD_M27) 219 220 #define EMASK_FBD_M29 0x10000000 /* M29Err DIMM-Isolation Completed */ 221 #define EMASK_FBD_M28 0x08000000 /* M28Err DIMM-Spare Copy Completed */ 222 #define EMASK_FBD_M27 0x04000000 /* M27Err DIMM-Spare Copy Initiated */ 223 #define EMASK_FBD_M26 0x02000000 /* M26Err Redundant Fast Reset */ 224 /* Timeout */ 225 #define EMASK_FBD_M25 0x01000000 /* M25Err Memory write error on */ 226 /* redundant retry */ 227 #define EMASK_FBD_M24 0x00800000 /* M24Err refresh error */ 228 #define EMASK_FBD_M23 0x00400000 /* M23Err Non-Redundant Fast Reset */ 229 /* Timeout */ 230 #define EMASK_FBD_M22 0x00200000 /* M22Err SPD protocol */ 231 #define EMASK_FBD_M21 0x00100000 /* M21Err FBD Northbound parity on */ 232 /* FBD sync status */ 233 #define EMASK_FBD_M20 0x00080000 /* M20Err Correctable patrol data ECC */ 234 #define EMASK_FBD_M19 0x00040000 /* M19Err Correctasble resilver or */ 235 /* spare-copy data ECC */ 236 #define EMASK_FBD_M18 0x00020000 /* M18Err Correctable Mirrored demand */ 237 /* data ECC */ 238 #define EMASK_FBD_M17 0x00010000 /* M17Err Correctable Non-mirrored */ 239 /* demand data ECC */ 240 #define EMASK_FBD_M16 0x00008000 /* M16Err channel failed over */ 241 #define EMASK_FBD_M15 0x00004000 /* M15Err Memory or FBD configuration */ 242 /* CRC read error */ 243 #define EMASK_FBD_M14 0x00002000 /* M14Err FBD configuration write */ 244 /* error on first attempt */ 245 #define EMASK_FBD_M13 0x00001000 /* M13Err Memory write error on first */ 246 /* attempt */ 247 #define EMASK_FBD_M12 0x00000800 /* M12Err Non-Aliased uncorrectable */ 248 /* patrol data ECC */ 249 #define EMASK_FBD_M11 0x00000400 /* M11Err Non-Aliased uncorrectable */ 250 /* resilver or spare copy data ECC */ 251 #define EMASK_FBD_M10 0x00000200 /* M10Err Non-Aliased uncorrectable */ 252 /* mirrored demand data ECC */ 253 #define EMASK_FBD_M9 0x00000100 /* M9Err Non-Aliased uncorrectable */ 254 /* non-mirrored demand data ECC */ 255 #define EMASK_FBD_M8 0x00000080 /* M8Err Aliased uncorrectable */ 256 /* patrol data ECC */ 257 #define EMASK_FBD_M7 0x00000040 /* M7Err Aliased uncorrectable */ 258 /* resilver or spare copy data ECC */ 259 #define EMASK_FBD_M6 0x00000020 /* M6Err Aliased uncorrectable */ 260 /* mirrored demand data ECC */ 261 #define EMASK_FBD_M5 0x00000010 /* M5Err Aliased uncorrectable */ 262 /* non-mirrored demand data ECC */ 263 #define EMASK_FBD_M4 0x00000008 /* M4Err uncorrectable data ECC on */ 264 /* replay */ 265 #define EMASK_FBD_M3 0x00000004 /* M3Err >Tmid thermal event with */ 266 /* intelligent throttling disabled */ 267 #define EMASK_FBD_M2 0x00000002 /* M2Err memory or FBD configuration */ 268 /* CRC read error */ 269 #define EMASK_FBD_M1 0x00000001 /* M1Err memory write error on */ 270 /* non-redundant retry or FBD */ 271 /* configuration write error on retry */ 272 /* MCH 7300 errata 34 (reserved mask bits) */ 273 #define EMASK_5000_FBD_RES (EMASK_FBD_M24|EMASK_FBD_M16) 274 #define EMASK_FBD_RES (nb_chipset == INTEL_NB_5400 ? 0 : EMASK_5000_FBD_RES) 275 276 #define EMASK_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M3|EMASK_FBD_M2|EMASK_FBD_M1) 277 #define EMASK_FBD_NF (EMASK_FBD_M28|EMASK_FBD_M27|EMASK_FBD_M26|EMASK_FBD_M25| \ 278 EMASK_FBD_M22|EMASK_FBD_M21|EMASK_FBD_M20|EMASK_FBD_M19|EMASK_FBD_M18| \ 279 EMASK_FBD_M17|EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \ 280 EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \ 281 EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4) 282 #define EMASK_5400_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M2|EMASK_FBD_M1) 283 #define EMASK_5400_FBD_NF (EMASK_FBD_M29|EMASK_FBD_M28|EMASK_FBD_M27| \ 284 EMASK_FBD_M26|EMASK_FBD_M25|EMASK_FBD_M24|EMASK_FBD_M22|EMASK_FBD_M21| \ 285 EMASK_FBD_M20|EMASK_FBD_M19|EMASK_FBD_M18|EMASK_FBD_M17|EMASK_FBD_M16| \ 286 EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \ 287 EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \ 288 EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4) 289 290 #define ERR_FAT_INT_B14 0x0400 /* B14Msk SF Scrub DBE */ 291 #define ERR_FAT_INT_B12 0x0100 /* B12Msk Parity Protected register */ 292 #define ERR_FAT_INT_B25 0x0080 /* B25Msk illegal HISMM/TSEG access */ 293 #define ERR_FAT_INT_B23 0x0040 /* B23Msk Vt Unaffiliated port error */ 294 #define ERR_FAT_INT_B21 0x0020 /* B21Msk illegal way */ 295 #define ERR_FAT_INT_B7 0x0010 /* B7Msk Multiple ECC error in any of */ 296 /* the ways during SF lookup */ 297 #define ERR_FAT_INT_B4 0x08 /* B4Msk Virtual pin port error */ 298 #define ERR_FAT_INT_B3 0x04 /* B3Msk Coherency violation error for EWB */ 299 #define ERR_FAT_INT_B2 0x02 /* B2Msk Multi-tag hit SF */ 300 #define ERR_FAT_INT_B1 0x01 /* B1Msk DM parity error */ 301 302 #define ERR_NF_INT_B27 0x4000 /* B27Msk Request received when in S1 */ 303 #define ERR_NF_INT_B24 0x2000 /* B24Msk DFXERR */ 304 #define ERR_NF_INT_B19 0x1000 /* B19Msk scrub SBE (SF) */ 305 #define ERR_NF_INT_B18 0x0800 /* B18Msk perfmon task completion */ 306 #define ERR_NF_INT_B17 0x0400 /* B17Msk JTAG/TAP error status */ 307 #define ERR_NF_INT_B16 0x0200 /* B16Msk SMBus error status */ 308 #define ERR_NF_INT_B22 0x0080 /* B22Msk Victim ROM parity */ 309 #define ERR_NF_INT_B20 0x0040 /* B20Msk Configuration write abort */ 310 #define ERR_NF_INT_B11 0x0020 /* B11Msk Victim Ram parity error */ 311 #define ERR_NF_INT_B10 0x0010 /* B10Msk DM Parity */ 312 #define ERR_NF_INT_B9 0x0008 /* B9Msk illeagl access */ 313 #define ERR_NF_INT_B8 0x0004 /* B8Msk SF Coherency Error for BIL */ 314 #define ERR_NF_INT_B6 0x0002 /* B6Msk Single ECC error on SF lookup */ 315 #define ERR_NF_INT_B5 0x0001 /* B5Msk Address Map error */ 316 317 #define NERR_NF_5400_INT_B26 0x0004 /* B26Msk Illeagl Access to */ 318 /* non-coherent address space */ 319 320 #define EMASK_INT_RES 0x02000000 /* Do not change */ 321 #define EMASK_INT_B25 0x01000000 /* B25Msk illegal HISMM/TSEG access */ 322 #define EMASK_INT_B23 0x00400000 /* B23Msk Vt Unaffiliated port error */ 323 #define EMASK_INT_B22 0x00200000 /* B22Msk Victim ROM parity */ 324 #define EMASK_INT_B21 0x00100000 /* B21Msk illegal way */ 325 #define EMASK_INT_B20 0x00080000 /* B20Msk Configuration write abort */ 326 #define EMASK_INT_B19 0x00040000 /* B19Msk Scrub SBE */ 327 #define EMASK_INT_B14 0x00002000 /* B14Msk Scrub DBE */ 328 #define EMASK_INT_B12 0x00000800 /* B12Msk Parity Protected */ 329 #define EMASK_INT_B11 0x00000400 /* B11Msk Victim Ram parity error */ 330 #define EMASK_INT_B10 0x00000200 /* B10Msk DM Parity */ 331 #define EMASK_INT_B9 0x00000100 /* B9Msk Illegal Accesss */ 332 333 #define EMASK_INT_B8 0x80 /* B8Msk SF Coherency Error for BIL */ 334 #define EMASK_INT_B7 0x40 /* B7Msk Multiple ECC error in any of */ 335 /* the ways during SF lookup */ 336 #define EMASK_INT_B6 0x20 /* B6Msk Single ECC error on SF lookup */ 337 #define EMASK_INT_B5 0x10 /* B5Msk Address Map error */ 338 #define EMASK_INT_B4 0x08 /* B4Msk Virtual pin port error */ 339 #define EMASK_INT_B3 0x04 /* B3Msk Coherency violation error for EWB */ 340 #define EMASK_INT_B2 0x02 /* B2Msk Multi-tag hit SF */ 341 #define EMASK_INT_B1 0x01 /* B1Msk DM parity error */ 342 343 /* MCH 5000 errata 2 */ 344 #define EMASK_INT_5000 EMASK_INT_B1 345 /* MCH 7300 errata 17 & 20 */ 346 #define EMASK_INT_7300 (EMASK_INT_B3|EMASK_INT_B1) 347 /* MCH 7300 errata 17,20 & 21 */ 348 #define EMASK_INT_7300_STEP_0 (EMASK_INT_B7|EMASK_INT_B3|EMASK_INT_B1) 349 350 #define EMASK_INT_FATAL (EMASK_INT_B7|EMASK_INT_B4|EMASK_INT_B3|EMASK_INT_B2| \ 351 EMASK_INT_B1) 352 #define EMASK_INT_NF (EMASK_INT_B8|EMASK_INT_B6|EMASK_INT_B5) 353 #define GE_FBD_FATAL ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_FATAL : \ 354 (GE_FERR_FBD0_FATAL|GE_FERR_FBD1_FATAL|GE_FERR_FBD2_FATAL| \ 355 GE_FERR_FBD3_FATAL)) 356 #define GE_FBD_NF ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_NF : \ 357 (GE_FERR_FBD0_NF|GE_FERR_FBD1_NF|GE_FERR_FBD2_NF|GE_FERR_FBD3_NF)) 358 359 #define EMASK_UNCOR_PEX_IO18 0x00200000 /* ESI Reset timeout */ 360 #define EMASK_UNCOR_PEX_IO2 0x00100000 /* Received an unsupported */ 361 /* request */ 362 #define EMASK_UNCOR_PEX_IO9 0x00040000 /* Malformed TLP Status */ 363 #define EMASK_UNCOR_PEX_IO10 0x00020000 /* Received buffer overflow */ 364 #define EMASK_UNCOR_PEX_IO8 0x00010000 /* unexpected completion */ 365 #define EMASK_UNCOR_PEX_IO7 0x00008000 /* completion abort */ 366 #define EMASK_UNCOR_PEX_IO6 0x00004000 /* completion timeout */ 367 #define EMASK_UNCOR_PEX_IO5 0x00002000 /* flow control protocol */ 368 #define EMASK_UNCOR_PEX_IO4 0x00001000 /* poisoned TLP */ 369 #define EMASK_UNCOR_PEX_IO19 0x00000020 /* surprise link down */ 370 #define EMASK_UNCOR_PEX_IO0 0x00000010 /* data link protocol */ 371 #define EMASK_UNCOR_PEX_IO3 0x00000001 /* training error */ 372 373 #define EMASK_COR_PEX_IO20 0x00002000 /* Advisory Non Fatal */ 374 #define EMASK_COR_PEX_IO16 0x00001000 /* replay timer timeout */ 375 #define EMASK_COR_PEX_IO15 0x00000100 /* replay num pollover */ 376 #define EMASK_COR_PEX_IO14 0x00000080 /* bad DLLP */ 377 #define EMASK_COR_PEX_IO13 0x00000040 /* bad TLP */ 378 #define EMASK_COR_PEX_IO12 0x00000001 /* receiver error mask */ 379 380 #define EMASK_RP_PEX_IO1 0x00000004 /* fatal message detect */ 381 #define EMASK_RP_PEX_IO11 0x00000002 /* uncorrectable message */ 382 #define EMASK_RP_PEX_IO17 0x00000001 /* correctable message */ 383 384 #define EMASK_UNIT_PEX_IO33 0x00002000 /* Link autonomous BW change */ 385 #define EMASK_UNIT_PEX_IO32 0x00001000 /* Received CA Posted Req */ 386 #define EMASK_UNIT_PEX_IO31 0x00000800 /* Received UR Posted Req */ 387 #define EMASK_UNIT_PEX_IO30 0x00000400 /* VT-d internal HW */ 388 #define EMASK_UNIT_PEX_IO29 0x00000200 /* MSI address */ 389 #define EMASK_UNIT_PEX_IO28 0x00000100 /* Link BW change */ 390 #define EMASK_UNIT_PEX_IO27 0x00000080 /* stop & scream */ 391 #define EMASK_UNIT_PEX_IO26 0x00000040 /* Received CA response */ 392 #define EMASK_UNIT_PEX_IO25 0x00000020 /* Received UR response */ 393 #define EMASK_UNIT_PEX_IO24 0x00000010 /* Outbound poisoned data */ 394 #define EMASK_UNIT_PEX_IO23 0x00000008 /* VTd fault */ 395 #define EMASK_UNIT_PEX_IO22 0x00000004 /* internal header/ctl parity */ 396 #define EMASK_UNIT_PEX_IO18 0x00000002 /* ESI reset timeout */ 397 #define EMASK_UNIT_PEX_VPP 0x00000001 /* correctable message detect */ 398 399 #define PEX_5400_FAT_IO32 0x00800000 /* Received CA Posted Request */ 400 #define PEX_5400_FAT_IO31 0x00400000 /* Received UR Posted Request */ 401 #define PEX_5400_FAT_IO30 0x00200000 /* VT-d Internal HW */ 402 #define PEX_5400_FAT_IO29 0x00100000 /* MSI Address */ 403 #define PEX_5400_FAT_IO27 0x00040000 /* Stop & Scream */ 404 #define PEX_5400_FAT_IO26 0x00020000 /* Received CA Response */ 405 #define PEX_5400_FAT_IO25 0x00010000 /* Received UR Response */ 406 #define PEX_5400_FAT_IO24 0x00008000 /* Outbound poisoned TLP */ 407 #define PEX_5400_FAT_IO23 0x00004000 /* VT-d Fault */ 408 #define PEX_5400_FAT_IO22 0x00002000 /* Internal Header/Control */ 409 /* Parity */ 410 #define PEX_5400_FAT_IO18 0x00001000 /* ESI reset timeout */ 411 #define PEX_5400_FAT_IO1 0x00000400 /* received fatal error msg */ 412 #define PEX_5400_FAT_IO2 0x00000200 /* received unsupported req */ 413 #define PEX_5400_FAT_IO9 0x00000100 /* malformed TLP */ 414 #define PEX_5400_FAT_IO10 0x00000080 /* receiver buffer overflow */ 415 #define PEX_5400_FAT_IO8 0x00000040 /* unexpected completion */ 416 #define PEX_5400_FAT_IO7 0x00000020 /* completer abort */ 417 #define PEX_5400_FAT_IO6 0x00000010 /* completion timeout */ 418 #define PEX_5400_FAT_IO5 0x00000008 /* flow control protocol */ 419 #define PEX_5400_FAT_IO4 0x00000004 /* poisoned TLP */ 420 #define PEX_5400_FAT_IO19 0x00000002 /* surprise link down */ 421 #define PEX_5400_FAT_IO0 0x00000001 /* data link layer protocol */ 422 #define PEX_FAT_IO19 0x00001000 /* surprise link down */ 423 #define PEX_FAT_IO18 0x00000800 /* ESI reset timeout */ 424 #define PEX_FAT_IO9 0x00000400 /* malformed TLP */ 425 #define PEX_FAT_IO10 0x00000200 /* receiver buffer overflow */ 426 #define PEX_FAT_IO8 0x00000100 /* unexpected completion */ 427 #define PEX_FAT_IO7 0x00000080 /* completer abort */ 428 #define PEX_FAT_IO6 0x00000040 /* completion timeout */ 429 #define PEX_FAT_IO5 0x00000020 /* flow control protocol */ 430 #define PEX_FAT_IO4 0x00000010 /* poisoned TLP */ 431 #define PEX_FAT_IO3 0x00000008 /* training error */ 432 #define PEX_FAT_IO2 0x00000004 /* received unsupported req */ 433 #define PEX_FAT_IO1 0x00000002 /* received fatal error message */ 434 #define PEX_FAT_IO0 0x00000001 /* data link layer protocol */ 435 436 #define PEX_5400_NF_IO33 0x20000000 /* link autonomous bandwidth */ 437 /* change (correctable) */ 438 #define PEX_5400_NF_IO32 0x10000000 /* Received CA Posted Request */ 439 #define PEX_5400_NF_IO31 0x08000000 /* Received UR Posted Request */ 440 #define PEX_5400_NF_IO30 0x04000000 /* VT-d Internal HW */ 441 #define PEX_5400_NF_IO29 0x02000000 /* MSI Address */ 442 #define PEX_5400_NF_IO28 0x01000000 /* Link bandwidth change */ 443 #define PEX_5400_NF_IO27 0x00800000 /* Stop & Scream */ 444 #define PEX_5400_NF_IO26 0x00400000 /* Received CA Response */ 445 #define PEX_5400_NF_IO25 0x00200000 /* Received UR Response */ 446 #define PEX_5400_NF_IO24 0x00100000 /* Outbound poisoned TLP */ 447 #define PEX_5400_NF_IO23 0x00080000 /* VT-d Fault */ 448 #define PEX_5400_NF_IO11 0x00040000 /* received non fatal err msg */ 449 #define PEX_5400_NF_IO17 0x00020000 /* rec correctable error msg */ 450 #define PEX_5400_NF_IO2 0x00008000 /* Received unsupported req */ 451 #define PEX_5400_NF_IO9 0x00004000 /* Malformed TLP */ 452 #define PEX_5400_NF_IO10 0x00002000 /* Received buffer overflow */ 453 #define PEX_5400_NF_IO8 0x00001000 /* unexpected completion err */ 454 #define PEX_5400_NF_IO7 0x00000800 /* completion abort */ 455 #define PEX_5400_NF_IO6 0x00000400 /* completion timeout */ 456 #define PEX_5400_NF_IO5 0x00000200 /* flow control protocol */ 457 #define PEX_5400_NF_IO4 0x00000100 /* poisoned TLP */ 458 #define PEX_5400_NF_IO19 0x00000080 /* surprise link down */ 459 #define PEX_5400_NF_IO0 0x00000040 /* data link layer protocol */ 460 #define PEX_5400_NF_IO20 0x00000020 /* Advisory Non Fatel */ 461 #define PEX_5400_NF_IO16 0x00000010 /* replay timer timeout */ 462 #define PEX_5400_NF_IO15 0x00000008 /* replay num pollover */ 463 #define PEX_5400_NF_IO14 0x00000004 /* bad DLLP */ 464 #define PEX_5400_NF_IO13 0x00000002 /* bad TLP */ 465 #define PEX_5400_NF_IO12 0x00000001 /* receiver error mask */ 466 #define PEX_NF_IO19 0x00020000 /* surprise link down */ 467 #define PEX_NF_IO17 0x00010000 /* received correctable error message */ 468 #define PEX_NF_IO16 0x00008000 /* replay timer timeout */ 469 #define PEX_NF_IO15 0x00004000 /* replay num pollover */ 470 #define PEX_NF_IO14 0x00002000 /* bad DLLP */ 471 #define PEX_NF_IO13 0x00001000 /* bad TLP */ 472 #define PEX_NF_IO12 0x00000800 /* receiver error mask */ 473 #define PEX_NF_IO11 0x00000400 /* received non fatal error message */ 474 #define PEX_NF_IO10 0x00000200 /* Received buffer overflow */ 475 #define PEX_NF_IO9 0x00000100 /* Malformed TLP */ 476 #define PEX_NF_IO8 0x00000080 477 #define PEX_NF_IO7 0x00000040 478 #define PEX_NF_IO6 0x00000020 /* completion timeout */ 479 #define PEX_NF_IO5 0x00000010 /* flow control protocol */ 480 #define PEX_NF_IO4 0x00000008 /* poisoned TLP */ 481 #define PEX_NF_IO3 0x00000004 482 #define PEX_NF_IO2 0x00000002 483 #define PEX_NF_IO0 0x00000001 /* data link layer protocol */ 484 485 #define ERR_FAT_TH2 0x02 /* >tmid thermal event */ 486 #define ERR_FAT_TH1 0x01 /* Catastrophic on-die thermal event */ 487 488 #define ERR_NF_TH5 0x10 /* timeout on cooling update */ 489 #define ERR_NF_TH4 0x08 /* TSMAX update */ 490 #define ERR_NF_TH3 0x04 /* on-die throttling event */ 491 492 #define EMASK_TH5 0x0010 /* TH5Msk timeout on cooling update */ 493 #define EMASK_TH4 0x0008 /* TH4Msk TSMAX update */ 494 #define EMASK_TH3 0x0004 /* TH3Msk on-die throttling event */ 495 #define EMASK_TH2 0x0002 /* TH2Msk >tmid thermal event */ 496 #define EMASK_TH1 0x0001 /* TH1Msk Catastrophic on-die thermal event */ 497 498 #define GE_FERR_FSB(ferr) ( \ 499 ((ferr) & (GE_FSB0_FATAL|GE_FSB0_NF)) ? 0 : \ 500 ((ferr) & (GE_FSB1_FATAL|GE_FSB1_NF)) ? 1 : \ 501 (nb_chipset == INTEL_NB_7300) && \ 502 ((ferr) & (GE_FERR_FSB2_FATAL|GE_FERR_FSB2_NF)) ? 2 : \ 503 (nb_chipset == INTEL_NB_7300) && \ 504 ((ferr) & (GE_FERR_FSB3_FATAL|GE_FERR_FSB3_NF)) ? 3 : \ 505 -1) 506 507 #define GE_NERR_TO_FERR_FSB(nerr) \ 508 ((((nerr) & GE_NERR_FSB3_FATAL) ? GE_FERR_FSB3_FATAL : 0) | \ 509 (((nerr) & GE_NERR_FSB2_FATAL) ? GE_FERR_FSB2_FATAL : 0) | \ 510 (((nerr) & GE_FSB1_FATAL) ? GE_FSB1_FATAL : 0) | \ 511 (((nerr) & GE_FSB0_FATAL) ? GE_FSB0_FATAL : 0) | \ 512 (((nerr) & GE_NERR_FSB3_NF) ? GE_FERR_FSB3_NF : 0) | \ 513 (((nerr) & GE_NERR_FSB2_NF) ? GE_FERR_FSB2_NF : 0) | \ 514 (((nerr) & GE_FSB1_NF) ? GE_FSB1_NF : 0) | \ 515 (((nerr) & GE_FSB0_NF) ? GE_FSB0_NF : 0)) 516 517 #define GE_ERR_PEX(ferr) ( \ 518 ((ferr) & (GE_ESI_FATAL|GE_ESI_NF)) ? 0 : \ 519 ((nb_chipset == INTEL_NB_7300 || nb_chipset == INTEL_NB_5400) && \ 520 ((ferr) & (GE_PCIEX1_FATAL|GE_PCIEX1_NF))) ? 1 : \ 521 ((ferr) & (GE_PCIEX2_FATAL|GE_PCIEX2_NF)) ? 2 : \ 522 ((ferr) & (GE_PCIEX3_FATAL|GE_PCIEX3_NF)) ? 3 : \ 523 ((ferr) & (GE_PCIEX4_FATAL|GE_PCIEX4_NF)) ? 4 : \ 524 ((ferr) & (GE_PCIEX5_FATAL|GE_PCIEX5_NF)) ? 5 : \ 525 ((ferr) & (GE_PCIEX6_FATAL|GE_PCIEX6_NF)) ? 6 : \ 526 ((ferr) & (GE_PCIEX7_FATAL|GE_PCIEX7_NF)) ? 7 : \ 527 (nb_chipset == INTEL_NB_5400) && \ 528 ((ferr) & (GE_PCIEX8_FATAL|GE_PCIEX8_NF)) ? 8 : \ 529 ((ferr) & (GE_PCIEX9_FATAL|GE_PCIEX9_NF)) ? 9 : \ 530 -1) 531 532 #define GE_FERR_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 533 (GE_INT_FATAL|GE_DMA_FATAL|GE_FERR_FSB3_FATAL|GE_FERR_FSB2_FATAL| \ 534 GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL|GE_PCIEX7_FATAL| \ 535 GE_PCIEX6_FATAL| GE_PCIEX5_FATAL|GE_PCIEX4_FATAL|GE_PCIEX3_FATAL| \ 536 GE_PCIEX2_FATAL| GE_ESI_FATAL) : \ 537 (GE_INT_FATAL|GE_DMA_FATAL|GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL| \ 538 GE_PCIEX7_FATAL|GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL| \ 539 GE_PCIEX3_FATAL|GE_PCIEX2_FATAL|GE_ESI_FATAL)) 540 541 #define GE_NERR_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 542 (GE_INT_FATAL|GE_DMA_FATAL|GE_NERR_FSB3_FATAL|GE_NERR_FSB2_FATAL| \ 543 GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL|GE_PCIEX7_FATAL| \ 544 GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL|GE_PCIEX3_FATAL| \ 545 GE_PCIEX2_FATALGE_ESI_FATAL) : \ 546 (GE_INT_FATAL|GE_DMA_FATAL|GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL| \ 547 GE_PCIEX7_FATAL|GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL| \ 548 GE_PCIEX3_FATAL|GE_PCIEX2_FATAL|GE_ESI_FATAL)) 549 550 #define GE_PCIEX_FATAL (GE_ESI_FATAL|GE_PCIEX1_FATAL|GE_PCIEX2_FATAL| \ 551 GE_PCIEX3_FATAL|GE_PCIEX4_FATAL|GE_PCIEX5_FATAL|GE_PCIEX6_FATAL| \ 552 GE_PCIEX7_FATAL) 553 #define GE_PCIEX_NF (GE_ESI_NF|GE_PCIEX1_NF|GE_PCIEX2_NF|GE_PCIEX3_NF| \ 554 GE_PCIEX4_NF|GE_PCIEX5_NF|GE_PCIEX6_NF|GE_PCIEX7_NF) 555 #define GE_FERR_FSB_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 556 (GE_FSB0_FATAL|GE_FSB1_FATAL|GE_FERR_FSB2_FATAL|GE_FERR_FSB3_FATAL) : \ 557 (GE_FSB0_FATAL|GE_FSB1_FATAL)) 558 #define GE_NERR_FSB_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 559 (GE_FSB0_FATAL|GE_FSB1_FATAL|GE_NERR_FSB2_FATAL|GE_NERR_FSB3_FATAL) : \ 560 (GE_FSB0_FATAL|GE_FSB1_FATAL)) 561 #define GE_FERR_FSB_NF ((nb_chipset == INTEL_NB_7300) ? \ 562 (GE_FSB0_NF|GE_FSB1_NF|GE_FERR_FSB2_NF|GE_FERR_FSB3_NF) : \ 563 (GE_FSB0_NF|GE_FSB1_NF)) 564 #define GE_NERR_FSB_NF ((nb_chipset == INTEL_NB_7300) ? \ 565 (GE_FSB0_NF|GE_FSB1_NF|GE_NERR_FSB2_NF|GE_NERR_FSB3_NF) : \ 566 (GE_FSB0_NF|GE_FSB1_NF)) 567 568 #define FERR_FBD_CHANNEL(reg) ((reg)>>28 & 3) 569 570 #define NB5000_STEPPING() nb_pci_getw(0, 0, 0, 8, 0) 571 572 #define FERR_GLOBAL_RD() ((nb_chipset == INTEL_NB_7300) ? \ 573 ((uint64_t)nb_pci_getl(0, 16, 2, \ 574 0x48, 0) << 32) | nb_pci_getl(0, 16, 2, \ 575 0x40, 0) : \ 576 (uint64_t)nb_pci_getl(0, 16, 2, 0x40, 0)) 577 #define NERR_GLOBAL_RD() nb_pci_getl(0, 16, 2, 0x44, 0) 578 #define FERR_FAT_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 579 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc0 : 0x40, ip) : \ 580 nb_pci_getb(0, 16, 0, fsb ? 0x480 : 0x180, ip)) 581 #define FERR_NF_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 582 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc1 : 0x41, ip) : \ 583 nb_pci_getb(0, 16, 0, fsb ? 0x481 : 0x181, ip)) 584 #define NERR_FAT_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 585 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc2 : 0x42, ip) : \ 586 nb_pci_getb(0, 16, 0, fsb ? 0x482 : 0x182, ip)) 587 #define NERR_NF_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 588 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc3 : 0x43, ip) : \ 589 nb_pci_getb(0, 16, 0, fsb ? 0x483 : 0x183, ip)) 590 591 #define NRECFSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 592 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc4 : 0x44, 0) : \ 593 nb_pci_getl(0, 16, 0, fsb ? 0x484 : 0x184, 0)) 594 #define NRECFSB_WR(fsb) \ 595 if (nb_chipset == INTEL_NB_7300) { \ 596 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc4 : 0x44, \ 597 0); \ 598 } else { \ 599 nb_pci_putl(0, 16, 0, fsb ? 0x484 : 0x184, 0); \ 600 } 601 #define RECFSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 602 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc8 : 0x48, 0) : \ 603 nb_pci_getl(0, 16, 0, fsb ? 0x488 : 0x188, 0)) 604 #define RECFSB_WR(fsb) \ 605 if (nb_chipset == INTEL_NB_7300) { \ 606 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc8 : 0x48, \ 607 0); \ 608 } else { \ 609 nb_pci_putl(0, 16, 0, fsb ? 0x488 : 0x188, 0); \ 610 } 611 #define NRECADDR_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 612 ((uint64_t)(nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, \ 613 (fsb & 1) ? 0xd0 : 0x50, 0)) << 32) | \ 614 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xcc : 0x4c, 0) : \ 615 ((uint64_t)(nb_pci_getb(0, 16, 0, fsb ? 0x490 : 0x190, 0)) << 32) | \ 616 nb_pci_getl(0, 16, 0, fsb ? 0x48c : 0x18c, 0)) 617 #define NRECADDR_WR(fsb) \ 618 if (nb_chipset == INTEL_NB_7300) { \ 619 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd0 : 0x50, \ 620 0); \ 621 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xcc : 0x4c, \ 622 0); \ 623 } else { \ 624 nb_pci_putb(0, 16, 0, fsb ? 0x490 : 0x190, 0); \ 625 nb_pci_putl(0, 16, 0, fsb ? 0x48c : 0x18c, 0); \ 626 } 627 #define EMASK_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 628 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd2 : 0x52, 0) : \ 629 nb_pci_getw(0, 16, 0, fsb ? 0x492 : 0x192, 0)) 630 #define ERR0_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 631 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd4 : 0x54, 0) : \ 632 nb_pci_getw(0, 16, 0, fsb ? 0x494 : 0x194, 0)) 633 #define ERR1_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 634 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd6 : 0x56, 0) : \ 635 nb_pci_getw(0, 16, 0, fsb ? 0x496 : 0x196, 0)) 636 #define ERR2_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 637 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd8 : 0x58, 0) : \ 638 nb_pci_getw(0, 16, 0, fsb ? 0x498 : 0x198, 0)) 639 #define MCERR_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 640 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xda : 0x5a, 0) : \ 641 nb_pci_getw(0, 16, 0, fsb ? 0x49a : 0x19a, 0)) 642 643 #define FERR_GLOBAL_WR(val) \ 644 if (nb_chipset == INTEL_NB_7300) \ 645 { \ 646 nb_pci_putl(0, 16, 2, 0x48, (uint32_t)(val >> 32)); \ 647 nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \ 648 } else { \ 649 nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \ 650 } 651 #define NERR_GLOBAL_WR(val) nb_pci_putl(0, 16, 2, 0x44, val) 652 #define FERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 653 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc0 : 0x40, val) : \ 654 nb_pci_putb(0, 16, 0, fsb ? 0x480 : 0x180, val)) 655 #define FERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 656 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc1 : 0x41, val) : \ 657 nb_pci_putb(0, 16, 0, fsb ? 0x481 : 0x181, val)) 658 #define NERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 659 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc2 : 0x42, val) : \ 660 nb_pci_putb(0, 16, 0, fsb ? 0x482 : 0x182, val)) 661 #define NERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 662 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc3 : 0x43, val) : \ 663 nb_pci_putb(0, 16, 0, fsb ? 0x483 : 0x183, val)) 664 #define EMASK_FSB_WR(fsb, val) \ 665 { \ 666 if (nb_chipset == INTEL_NB_7300) \ 667 nb_pci_putw(0, 17, ((fsb) & 2) ? 3 : 0, \ 668 ((fsb) & 1) ? 0xd2 : 0x52, val); \ 669 else \ 670 nb_pci_putw(0, 16, 0, fsb ? 0x492 : 0x192, val); \ 671 } 672 #define ERR0_FSB_WR(fsb, val) \ 673 { \ 674 if (nb_chipset == INTEL_NB_7300) \ 675 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 676 (fsb & 1) ? 0xd4 : 0x54, val); \ 677 else \ 678 nb_pci_putw(0, 16, 0, fsb ? 0x494 : 0x194, val); \ 679 } 680 #define ERR1_FSB_WR(fsb, val) \ 681 { \ 682 if (nb_chipset == INTEL_NB_7300) \ 683 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 684 (fsb & 1) ? 0xd6 : 0x56, val); \ 685 else \ 686 nb_pci_putw(0, 16, 0, fsb ? 0x496 : 0x196, val); \ 687 } 688 #define ERR2_FSB_WR(fsb, val) \ 689 { \ 690 if (nb_chipset == INTEL_NB_7300) \ 691 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 692 (fsb & 1) ? 0xd8 : 0x58, val); \ 693 else \ 694 nb_pci_putw(0, 16, 0, fsb ? 0x498 : 0x198, val); \ 695 } 696 #define MCERR_FSB_WR(fsb, val) \ 697 { \ 698 if (nb_chipset == INTEL_NB_7300) \ 699 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 700 (fsb & 1) ? 0xda : 0x5a, val); \ 701 else \ 702 nb_pci_putw(0, 16, 0, fsb ? 0x49a : 0x19a, val); \ 703 } 704 705 #define NRECSF_RD() (nb_chipset == INTEL_NB_5000X || \ 706 nb_chipset == INTEL_NB_7300) ? ((uint64_t)( \ 707 nb_pci_getl(0, 16, 2, 0xb4, 0)) << 32) | \ 708 nb_pci_getl(0, 16, 2, 0xb0, 0) : 0LL 709 #define RECSF_RD() (nb_chipset == INTEL_NB_5000X || \ 710 nb_chipset == INTEL_NB_7300) ? ((uint64_t)( \ 711 nb_pci_getl(0, 16, 2, 0xbc, 0)) << 32) | \ 712 nb_pci_getl(0, 16, 2, 0xb8, 0) : 0LL 713 714 #define NRECSF_WR() if (nb_chipset == INTEL_NB_5000X || \ 715 nb_chipset == INTEL_NB_7300) { \ 716 nb_pci_putl(0, 16, 2, 0xbc, 0); \ 717 nb_pci_putl(0, 16, 2, 0xb0, 0); \ 718 } 719 #define RECSF_WR() if (nb_chipset == INTEL_NB_5000X || \ 720 nb_chipset == INTEL_NB_7300) { \ 721 nb_pci_putl(0, 16, 2, 0xbc, 0); \ 722 nb_pci_putl(0, 16, 2, 0xb8, 0); \ 723 } 724 725 #define FERR_FAT_INT_RD(ip) (((nb_chipset == INTEL_NB_5400) ? \ 726 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip) << 8) : (uint16_t)0) | \ 727 nb_pci_getb(0, 16, 2, 0xc0, ip)) 728 #define FERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 729 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip) << 8) | \ 730 nb_pci_getb(0, 16, 2, 0xc2, ip) : \ 731 (uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip)) 732 #define NERR_FAT_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 733 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc4, ip) << 8) | \ 734 nb_pci_getb(0, 16, 2, 0xc5, ip) : \ 735 (uint16_t)nb_pci_getb(0, 16, 2, 0xc2, ip)) 736 #define NERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 737 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc6, ip) << 8) | \ 738 nb_pci_getb(0, 16, 2, 0xc7, ip) : \ 739 (uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip)) 740 #define EMASK_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 741 nb_pci_getl(0, 16, 2, 0xd0, 0) : nb_pci_getb(0, 16, 2, 0xcc, 0)) 742 #define ERR0_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 743 nb_pci_getl(0, 16, 2, 0xd4, 0) : nb_pci_getb(0, 16, 2, 0xd0, 0)) 744 #define ERR1_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 745 nb_pci_getl(0, 16, 2, 0xd8, 0) : nb_pci_getb(0, 16, 2, 0xd1, 0)) 746 #define ERR2_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 747 nb_pci_getl(0, 16, 2, 0xdc, 0) : nb_pci_getb(0, 16, 2, 0xd2, 0)) 748 #define MCERR_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 749 nb_pci_getl(0, 16, 2, 0xe0, 0) : nb_pci_getb(0, 16, 2, 0xd3, 0)) 750 751 #define FERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 752 nb_pci_putb(0, 16, 2, 0xc0, \ 753 val & 0xff); \ 754 nb_pci_putb(0, 16, 2, 0xc1, val >> 8); \ 755 } else { \ 756 nb_pci_putb(0, 16, 2, 0xc0, val); \ 757 } 758 #define FERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 759 nb_pci_putb(0, 16, 2, 0xc2, \ 760 val & 0xff); \ 761 nb_pci_putb(0, 16, 2, 0xc3, val >> 8); \ 762 } else { \ 763 nb_pci_putb(0, 16, 2, 0xc1, val); \ 764 } 765 #define NERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 766 nb_pci_putb(0, 16, 2, 0xc4, \ 767 val & 0xff); \ 768 nb_pci_putb(0, 16, 2, 0xc5, val >> 8); \ 769 } else { \ 770 nb_pci_putb(0, 16, 2, 0xc2, val); \ 771 } 772 #define NERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 773 nb_pci_putb(0, 16, 2, 0xc6, \ 774 val & 0xff); \ 775 nb_pci_putb(0, 16, 2, 0xc7, val >> 8); \ 776 } else { \ 777 nb_pci_putb(0, 16, 2, 0xc3, val); \ 778 } 779 #define EMASK_5000_INT_WR(val) nb_pci_putb(0, 16, 2, 0xcc, val) 780 #define EMASK_5400_INT_WR(val) nb_pci_putl(0, 16, 2, 0xd0, val) 781 #define EMASK_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 782 EMASK_5400_INT_WR(val); \ 783 } else { \ 784 EMASK_5000_INT_WR(val); \ 785 } 786 #define ERR0_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 787 nb_pci_putl(0, 16, 2, 0xd4, val); \ 788 } else { \ 789 nb_pci_putb(0, 16, 2, 0xd0, val); \ 790 } 791 #define ERR1_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 792 nb_pci_putl(0, 16, 2, 0xd8, val); \ 793 } else { \ 794 nb_pci_putb(0, 16, 2, 0xd1, val); \ 795 } 796 #define ERR2_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 797 nb_pci_putl(0, 16, 2, 0xdc, val); \ 798 } else { \ 799 nb_pci_putb(0, 16, 2, 0xd2, val); \ 800 } 801 #define MCERR_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 802 nb_pci_putl(0, 16, 2, 0xe0, val); \ 803 } else { \ 804 nb_pci_putb(0, 16, 2, 0xd3, val); \ 805 } 806 807 #define NRECINT_RD() nb_pci_getl(0, 16, 2, 0xc4, 0) 808 #define RECINT_RD() nb_pci_getl(0, 16, 2, 0xc8, 0) 809 810 #define NRECINT_WR() nb_pci_putl(0, 16, 2, 0xc4, 0) 811 #define RECINT_WR() nb_pci_putl(0, 16, 2, 0xc8, 0) 812 813 #define FERR_FAT_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0x98, ip) 814 #define NERR_FAT_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0x9c, ip) 815 #define FERR_NF_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0xa0, ip) 816 #define NERR_NF_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0xa4, ip) 817 #define EMASK_FBD_RD() nb_pci_getl(0, 16, 1, 0xa8, 0) 818 #define ERR0_FBD_RD() nb_pci_getl(0, 16, 1, 0xac, 0) 819 #define ERR1_FBD_RD() nb_pci_getl(0, 16, 1, 0xb0, 0) 820 #define ERR2_FBD_RD() nb_pci_getl(0, 16, 1, 0xb4, 0) 821 #define MCERR_FBD_RD() nb_pci_getl(0, 16, 1, 0xb8, 0) 822 823 #define FERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x98, val) 824 #define NERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x9c, val) 825 #define FERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa0, val) 826 #define NERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa4, val) 827 #define EMASK_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa8, val) 828 #define ERR0_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xac, val) 829 #define ERR1_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb0, val) 830 #define ERR2_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb4, val) 831 #define MCERR_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb8, val) 832 833 #define NRECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 834 nb_pci_getw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \ 835 nb_pci_getw(0, 16, 1, 0xbe, 0)) 836 #define NRECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 837 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \ 838 nb_pci_getl(0, 16, 1, 0xc0, 0)) 839 #define NRECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 840 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x74, 0) : \ 841 nb_pci_getl(0, 16, 1, 0xc4, 0)) 842 #define NRECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 843 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc4, 0) : \ 844 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc4 : 0xc8, 0)) 845 #define NRECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 846 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc8, 0) : \ 847 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc8 : 0xcc, 0)) 848 #define NRECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 849 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xcc, 0) : \ 850 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xcc : 0xd0, 0)) 851 #define NRECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 852 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd0, 0) : \ 853 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd0 : 0xd4, 0)) 854 #define NRECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 855 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd4, 0) : \ 856 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd4 : 0xd8, 0)) 857 #define NRECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 858 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd8, 0) : \ 859 nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xd8, 0) : 0) 860 #define REDMEMB_RD() (nb_chipset == INTEL_NB_5400 ? \ 861 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x7c, 0) : \ 862 nb_pci_getl(0, 16, 1, 0x7c, 0)) 863 #define RECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 864 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe0, 0) & 0xffffff : \ 865 nb_pci_getw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : 0xe2, 0)) 866 #define RECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 867 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe4, 0) : \ 868 nb_pci_getl(0, 16, 1, 0xe4, 0)) 869 #define RECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 870 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x78, 0) : \ 871 nb_chipset == INTEL_NB_7300 ? nb_pci_getl(0, 16, 1, 0x78, 0) : \ 872 nb_pci_getl(0, 16, 1, 0xe8, 0)) 873 #define RECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 874 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe8, 0) : \ 875 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe8 : 0xec, 0)) 876 #define RECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 877 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xec, 0) : \ 878 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xec : 0xf0, 0)) 879 #define RECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 880 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf0, 0) : \ 881 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf0 : 0xf4, 0)) 882 #define RECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 883 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf4, 0) : \ 884 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf4 : 0xf8, 0)) 885 #define RECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 886 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf8, 0) : \ 887 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf8 : 0xfc, 0)) 888 #define RECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 889 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xfc, 0) : \ 890 nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xfc, 0) : 0) 891 #define NRECMEMA_WR(branch) (nb_chipset == INTEL_NB_5400 ? \ 892 nb_pci_putw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \ 893 nb_pci_putw(0, 16, 1, 0xbe, 0)) 894 #define NRECMEMB_WR(branch) (nb_chipset == INTEL_NB_5400 ? \ 895 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \ 896 nb_pci_putl(0, 16, 1, 0xc0, 0)) 897 #define NRECFGLOG_WR(branch) \ 898 if (nb_chipset == INTEL_NB_5400) \ 899 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x74, 0); \ 900 else if (nb_chipset == INTEL_NB_7300) \ 901 nb_pci_putl(0, 16, 1, 0x74, 0); \ 902 else \ 903 nb_pci_putl(0, 16, 1, 0xc4, 0) 904 #define NRECFBDA_WR(branch) \ 905 if (nb_chipset == INTEL_NB_5400) \ 906 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc4, 0); \ 907 else if (nb_chipset == INTEL_NB_7300) \ 908 nb_pci_putl(0, 16, 1, 0xc4, 0); \ 909 else \ 910 nb_pci_putl(0, 16, 1, 0xc8, 0) 911 #define NRECFBDB_WR(branch) \ 912 if (nb_chipset == INTEL_NB_5400) \ 913 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc8, 0); \ 914 else if (nb_chipset == INTEL_NB_7300) \ 915 nb_pci_putl(0, 16, 1, 0xc8, 0); \ 916 else \ 917 nb_pci_putl(0, 16, 1, 0xcc, 0) 918 #define NRECFBDC_WR(branch) \ 919 if (nb_chipset == INTEL_NB_5400) \ 920 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xcc, 0); \ 921 else if (nb_chipset == INTEL_NB_7300) \ 922 nb_pci_putl(0, 16, 1, 0xcc, 0); \ 923 else \ 924 nb_pci_putl(0, 16, 1, 0xd0, 0) 925 #define NRECFBDD_WR(branch) \ 926 if (nb_chipset == INTEL_NB_5400) \ 927 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd0, 0); \ 928 else if (nb_chipset == INTEL_NB_7300) \ 929 nb_pci_putl(0, 16, 1, 0xd0, 0); \ 930 else \ 931 nb_pci_putl(0, 16, 1, 0xd4, 0) 932 #define NRECFBDE_WR(branch) \ 933 if (nb_chipset == INTEL_NB_5400) \ 934 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd4, 0); \ 935 else if (nb_chipset == INTEL_NB_7300) \ 936 nb_pci_putl(0, 16, 1, 0xd4, 0); \ 937 else \ 938 nb_pci_putl(0, 16, 1, 0xd8, 0) 939 #define NRECFBDF_WR(branch) \ 940 if (nb_chipset == INTEL_NB_5400) \ 941 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd8, 0); \ 942 else if (nb_chipset == INTEL_NB_7300) \ 943 nb_pci_putw(0, 16, 1, 0xd8, 0); 944 #define REDMEMB_WR(branch) \ 945 if (nb_chipset == INTEL_NB_5400) \ 946 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x7c, 0); \ 947 else \ 948 nb_pci_putl(0, 16, 1, 0x7c, 0) 949 #define RECMEMA_WR(branch) \ 950 if (nb_chipset == INTEL_NB_5400) \ 951 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe0, 0); \ 952 else \ 953 nb_pci_putw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : \ 954 0xe2, 0) 955 #define RECMEMB_WR(branch) \ 956 if (nb_chipset == INTEL_NB_5400) \ 957 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe4, 0); \ 958 else \ 959 nb_pci_putl(0, 16, 1, 0xe4, 0) 960 #define RECFGLOG_WR(branch) \ 961 if (nb_chipset == INTEL_NB_5400) \ 962 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x78, 0); \ 963 else if (nb_chipset == INTEL_NB_7300) \ 964 nb_pci_putl(0, 16, 1, 0x78, 0); \ 965 else \ 966 nb_pci_putl(0, 16, 1, 0xe8, 0) 967 #define RECFBDA_WR(branch) \ 968 if (nb_chipset == INTEL_NB_5400) \ 969 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe8, 0); \ 970 else if (nb_chipset == INTEL_NB_7300) \ 971 nb_pci_putl(0, 16, 1, 0xe8, 0); \ 972 else \ 973 nb_pci_putl(0, 16, 1, 0xec, 0) 974 #define RECFBDB_WR(branch) \ 975 if (nb_chipset == INTEL_NB_5400) \ 976 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xec, 0); \ 977 else if (nb_chipset == INTEL_NB_7300) \ 978 nb_pci_putl(0, 16, 1, 0xec, 0); \ 979 else \ 980 nb_pci_putl(0, 16, 1, 0xf0, 0) 981 #define RECFBDC_WR(branch) \ 982 if (nb_chipset == INTEL_NB_5400) \ 983 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf0, 0); \ 984 else if (nb_chipset == INTEL_NB_7300) \ 985 nb_pci_putl(0, 16, 1, 0xf0, 0); \ 986 else \ 987 nb_pci_putl(0, 16, 1, 0xf4, 0) 988 #define RECFBDD_WR(branch) \ 989 if (nb_chipset == INTEL_NB_5400) \ 990 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf4, 0); \ 991 else if (nb_chipset == INTEL_NB_7300) \ 992 nb_pci_putl(0, 16, 1, 0xf4, 0); \ 993 else \ 994 nb_pci_putl(0, 16, 1, 0xf8, 0) 995 #define RECFBDE_WR(branch) \ 996 if (nb_chipset == INTEL_NB_5400) \ 997 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf8, 0); \ 998 else if (nb_chipset == INTEL_NB_7300) \ 999 nb_pci_putl(0, 16, 1, 0xf8, 0); \ 1000 else \ 1001 nb_pci_putl(0, 16, 1, 0xfc, 0) 1002 #define RECFBDF_WR(branch) \ 1003 if (nb_chipset == INTEL_NB_5400) \ 1004 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xfc, 0); \ 1005 else if (nb_chipset == INTEL_NB_7300) \ 1006 nb_pci_putw(0, 16, 1, 0xf8, 0); \ 1007 1008 #define MC_RD() nb_pci_getl(0, 16, 1, 0x40, 0) 1009 #define MC_WR(val) nb_pci_putl(0, 16, 1, 0x40, val) 1010 #define MCA_RD() nb_pci_getl(0, 16, 1, 0x58, 0) 1011 #define TOLM_RD() nb_pci_getw(0, 16, 1, 0x6c, 0) 1012 1013 #define MTR_RD(branch, dimm) (nb_chipset == INTEL_NB_5400 ? \ 1014 nb_pci_getw(0, (branch) == 0 ? 21 : 22, 0, 0x80 + dimm * 2, 0) : \ 1015 ((branch) == 0) ? \ 1016 nb_pci_getw(0, 21, 0, \ 1017 dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : \ 1018 (nb_number_memory_controllers == 2) ? \ 1019 nb_pci_getw(0, 22, 0, \ 1020 dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : 0) 1021 #define MIR_RD(reg) nb_pci_getw(0, 16, 1, 0x80 + ((reg)*4), 0) 1022 1023 #define DMIR_RD(branch, reg) \ 1024 ((branch) == 0) ? nb_pci_getl(0, 21, 0, 0x90 + ((reg)*4), 0) : \ 1025 (nb_number_memory_controllers == 2) ? \ 1026 nb_pci_getl(0, 22, 0, 0x90 + ((reg)*4), 0) : 0 1027 1028 #define SPCPC_RD(branch) (nb_chipset == INTEL_NB_5000P || \ 1029 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1030 nb_chipset == INTEL_NB_5000Z ? \ 1031 (((branch) == 0) ? \ 1032 (uint32_t)nb_pci_getb(0, 21, 0, 0x40, 0) : \ 1033 (nb_number_memory_controllers == 2) ? \ 1034 (uint32_t)nb_pci_getb(0, 22, 0, 0x40, 0) : 0) : \ 1035 nb_pci_getl(0, ((branch) == 0) ? 21 : 22, 0, 0x40, 0)) 1036 1037 #define SPCPC_SPARE_ENABLE (nb_chipset == INTEL_NB_5000P || \ 1038 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1039 nb_chipset == INTEL_NB_5000Z ? 1 : 0x20) 1040 #define SPCPC_SPRANK(spcpc) (nb_chipset == INTEL_NB_5000P || \ 1041 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1042 nb_chipset == INTEL_NB_5000Z ? \ 1043 (((spcpc) >> 1) & 7) : ((spcpc) & 0xf)) 1044 1045 #define SPCPS_RD(branch) ((branch) == 0) ? \ 1046 nb_pci_getb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \ 1047 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1048 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : \ 1049 (nb_number_memory_controllers == 2) ? \ 1050 nb_pci_getb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \ 1051 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1052 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : 0 1053 1054 #define SPCPS_WR(branch) \ 1055 if ((branch) == 0) { \ 1056 nb_pci_putb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \ 1057 nb_chipset == INTEL_NB_5000X || \ 1058 nb_chipset == INTEL_NB_5000V || \ 1059 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \ 1060 } else if (nb_number_memory_controllers == 2) { \ 1061 nb_pci_putb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \ 1062 nb_chipset == INTEL_NB_5000X || \ 1063 nb_chipset == INTEL_NB_5000V || \ 1064 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \ 1065 } 1066 1067 #define SPCPS_SPARE_DEPLOYED (nb_chipset == INTEL_NB_5000P || \ 1068 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1069 nb_chipset == INTEL_NB_5000Z ? 0x11 : 0x60) 1070 #define SPCPS_FAILED_RANK(spcps) (nb_chipset == INTEL_NB_5000P || \ 1071 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1072 nb_chipset == INTEL_NB_5000Z ? (((spcps) >> 1) & 7) : ((spcps) & 0xf)) 1073 1074 #define UERRCNT_RD(branch) ((branch) == 0) ? \ 1075 nb_pci_getl(0, 21, 0, 0xa4, 0) : \ 1076 (nb_number_memory_controllers == 2) ? \ 1077 nb_pci_getl(0, 22, 0, 0xa4, 0) : 0 1078 #define CERRCNT_RD(branch) ((branch) == 0) ? \ 1079 nb_pci_getl(0, 21, 0, 0xa8, 0) : \ 1080 (nb_number_memory_controllers == 2) ? \ 1081 nb_pci_getl(0, 22, 0, 0xa8, 0) : 0 1082 #define CERRCNTA_RD(branch, channel) \ 1083 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1084 (channel & 1) == 0 ? 0xe0 : 0xf0, 0) 1085 #define CERRCNTB_RD(branch, channel) \ 1086 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1087 (channel & 1) == 0 ? 0xe4 : 0xf4, 0) 1088 #define CERRCNTC_RD(branch, channel) \ 1089 (nb_chipset == INTEL_NB_7300 ? \ 1090 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1091 (channel & 1) == 0 ? 0xe8 : 0xf8, 0) : 0) 1092 #define CERRCNTD_RD(branch, channel) \ 1093 (nb_chipset == INTEL_NB_7300 ? \ 1094 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1095 (channel & 1) == 0 ? 0xec : 0xfc, 0) : 0) 1096 #define BADRAMA_RD(branch) ((branch) == 0) ? \ 1097 nb_pci_getl(0, 21, 0, 0xac, 0) : \ 1098 (nb_number_memory_controllers == 2) ? \ 1099 nb_pci_getl(0, 22, 0, 0xac, 0) : 0 1100 #define BADRAMB_RD(branch) ((branch) == 0) ? \ 1101 nb_pci_getw(0, 21, 0, 0xb0, 0) : \ 1102 (nb_number_memory_controllers == 2) ? \ 1103 nb_pci_getw(0, 22, 0, 0xb0, 0) : 0 1104 #define BADCNT_RD(branch) ((branch) == 0) ? \ 1105 nb_pci_getl(0, 21, 0, 0xb4, 0) : \ 1106 (nb_number_memory_controllers == 2) ? \ 1107 nb_pci_getl(0, 22, 0, 0xb4, 0) : 0 1108 1109 #define UERRCNT_WR(branch, val) ((branch) == 0) ? \ 1110 nb_pci_putl(0, 21, 0, 0xa4, val) : \ 1111 (nb_number_memory_controllers == 2) ? \ 1112 nb_pci_putl(0, 22, 0, 0xa4, val) \ 1113 : 0 1114 #define CERRCNT_WR(branch, val) ((branch) == 0) ? \ 1115 nb_pci_putl(0, 21, 0, 0xa8, val) : \ 1116 (nb_number_memory_controllers == 2) ? \ 1117 nb_pci_putl(0, 22, 0, 0xa8, val) : 0 1118 #define BADRAMA_WR(branch, val) ((branch) == 0) ? \ 1119 nb_pci_putl(0, 21, 0, 0xac, val) : \ 1120 (nb_number_memory_controllers == 2) ? \ 1121 nb_pci_putl(0, 22, 0, 0xac, val) : 0 1122 #define BADRAMB_WR(branch, val) ((branch) == 0) ? \ 1123 nb_pci_putw(0, 21, 0, 0xb0, val) : \ 1124 (nb_number_memory_controllers == 2) ? \ 1125 nb_pci_putw(0, 22, 0, 0xb0) : 0 1126 #define BADCNT_WR(branch, val) ((branch) == 0) ? \ 1127 nb_pci_putl(0, 21, 0, 0xb4, val) : \ 1128 (nb_number_memory_controllers == 2) ? \ 1129 nb_pci_putl(0, 22, 0, 0xb4, val) : 0 1130 1131 #define SPD_RD(branch, channel) ((branch) == 0) ? \ 1132 nb_pci_getw(0, 21, 0, 0x74 + ((channel) * 2), 0) : \ 1133 (nb_number_memory_controllers == 2) ? \ 1134 nb_pci_getw(0, 22, 0, 0x74 + ((channel) * 2), 0) : 0 1135 #define SPDCMDRD(branch, channel) ((branch) == 0) ? \ 1136 nb_pci_getl(0, 21, 0, 0x78 + ((channel) * 4), 0) : \ 1137 (nb_number_memory_controllers == 2) ? \ 1138 nb_pci_getl(0, 22, 0, 0x78 + ((channel) * 4), 0) : 0 1139 1140 #define SPDCMD1_1_WR(val) nb_pci_putl(0, 21, 0, 0x7c, val) 1141 #define SPDCMD_WR(branch, channel, val) \ 1142 if ((branch) == 0) \ 1143 nb_pci_putl(0, 21, 0, 0x78 + ((channel) * 4), val); \ 1144 else if (nb_number_memory_controllers == 2) \ 1145 nb_pci_putl(0, 22, 0, 0x78 + ((channel) * 4), val) 1146 1147 #define UNCERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x104, 0) 1148 #define UNCERRMSK_RD(pex) nb_pci_getl(0, pex, 0, 0x108, 0) 1149 #define PEX_FAT_FERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x154, 0) 1150 #define PEX_FAT_NERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x15c, 0) 1151 #define PEX_NF_FERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x158, 0) 1152 #define PEX_NF_NERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x160, 0) 1153 #define PEX_ERR_DOCMD_RD(pex) ((nb_chipset == INTEL_NB_5400) ? \ 1154 nb_pci_getw(0, pex, 0, 0x144, 0) : nb_pci_getl(0, pex, 0, 0x144, 0)) 1155 #define PEX_ERR_PIN_MASK_RD(pex) nb_pci_getw(0, pex, 0, 0x146, 0) 1156 #define EMASK_UNCOR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x148, 0) 1157 #define EMASK_COR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x14c, 0) 1158 #define EMASK_RP_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x150, 0) 1159 1160 #define UNCERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x104, val) 1161 #define UNCERRMSK_WR(pex, val) nb_pci_putl(0, pex, 0, 0x108, val) 1162 #define PEX_FAT_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x154, val) 1163 #define PEX_FAT_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x15c, val) 1164 #define PEX_NF_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x158, val) 1165 #define PEX_NF_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x160, val) 1166 #define PEX_ERR_DOCMD_WR(pex, val) ((nb_chipset == INTEL_NB_5400) ? \ 1167 nb_pci_putw(0, pex, 0, 0x144, val) : nb_pci_putl(0, pex, 0, 0x144, val)) 1168 #define PEX_ERR_PIN_MASK_WR(pex, val) nb_pci_putw(0, pex, 0, 0x146, val) 1169 #define EMASK_UNCOR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x148, val) 1170 #define EMASK_COR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x14c, val) 1171 #define EMASK_RP_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x150, val) 1172 1173 #define PEX_FAT_FERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x154, ip) 1174 #define PEX_FAT_NERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x15c, ip) 1175 #define PEX_NF_FERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x158, ip) 1176 #define PEX_NF_NERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x160, ip) 1177 #define UNCERRSEV_RD(pex) nb_pci_getl(0, pex, 0, 0x10c, 0) 1178 #define CORERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x110, 0) 1179 #define RPERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x130, 0) 1180 #define RPERRSID_RD(pex) nb_pci_getl(0, pex, 0, 0x134, 0) 1181 #define AERRCAPCTRL_RD(pex) nb_pci_getl(0, pex, 0, 0x118, 0) 1182 #define PEXDEVSTS_RD(pex) nb_pci_getw(0, pex, 0, 0x76, 0) 1183 #define PEXROOTCTL_RD(pex) nb_pci_getw(0, pex, 0, 0x88, 0) 1184 1185 #define PEX_FAT_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x154, val) 1186 #define PEX_FAT_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x15c, val) 1187 #define PEX_NF_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x158, val) 1188 #define PEX_NF_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x160, val) 1189 #define CORERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x110, val) 1190 #define UNCERRSEV_WR(pex, val) nb_pci_putl(0, pex, 0, 0x10c, val) 1191 #define RPERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x130, val) 1192 #define PEXDEVSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x76, val) 1193 #define PEXROOTCTL_WR(pex, val) nb_pci_putw(0, pex, 0, 0x88, val) 1194 1195 #define PCISTS_RD(ip) nb_pci_getw(0, 8, 0, 0x6, ip) 1196 #define PCIDEVSTS_RD() nb_pci_getw(0, 8, 0, 0x76, 0) 1197 #define PCISTS_WR(val) nb_pci_putw(0, 8, 0, 0x6, val) 1198 #define PCIDEVSTS_WR(val) nb_pci_putw(0, 8, 0, 0x76, val) 1199 1200 #define RANK_MASK (nb_chipset != INTEL_NB_7300 ? 7 : 0xf) 1201 #define CAS_MASK (nb_chipset == INTEL_NB_5000P || \ 1202 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1203 nb_chipset == INTEL_NB_5000Z ? 0xfff : 0x1fff) 1204 #define RAS_MASK (nb_chipset == INTEL_NB_5000P || \ 1205 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1206 nb_chipset == INTEL_NB_5000Z ? 0x7fff : 0xffff) 1207 #define BANK_MASK 7 1208 1209 #define DMIR_RANKS(dmir, rank0, rank1, rank2, rank3) \ 1210 if (nb_chipset == INTEL_NB_5000P || nb_chipset == INTEL_NB_5000X || \ 1211 nb_chipset == INTEL_NB_5000V || nb_chipset == INTEL_NB_5000Z) { \ 1212 rank0 = (dmir) & 3; \ 1213 rank1 = ((dmir) >> 3) & 3; \ 1214 rank2 = ((dmir) >> 6) & 3; \ 1215 rank3 = ((dmir) >> 9) & 3; \ 1216 } else { \ 1217 rank0 = (dmir) & 0xf; \ 1218 rank1 = ((dmir) >> 4) & 0xf; \ 1219 rank2 = ((dmir) >> 8) & 0xf; \ 1220 rank3 = ((dmir) >> 12) & 0xf; \ 1221 } 1222 1223 #define FERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf0, ip) 1224 #define FERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf1, ip) 1225 #define NERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf2, ip) 1226 #define NERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf3, ip) 1227 #define EMASK_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf6, ip) 1228 #define ERR0_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf8, ip) 1229 #define ERR1_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfa, ip) 1230 #define ERR2_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfc, ip) 1231 #define MCERR_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfe, ip) 1232 #define CTSTS_RD() nb_pci_getb(0, 16, 4, 0xee, 0) 1233 #define THRTSTS_RD() nb_pci_getw(0, 16, 3, 0x68, 0) 1234 1235 #define FERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf0, val) 1236 #define FERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf1, val) 1237 #define NERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf2, val) 1238 #define NERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf3, val) 1239 #define EMASK_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf6, val) 1240 #define ERR0_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf8, val) 1241 #define ERR1_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfa, val) 1242 #define ERR2_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfc, val) 1243 #define MCERR_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfe, val) 1244 #define CTSTS_WR(val) nb_pci_putb(0, 16, 4, 0xee, val) 1245 #define THRTSTS_WR(val) nb_pci_putw(0, 16, 3, 0x68, val) 1246 1247 #define ERR_FAT_THR_F2 0x02 /* >tnid thermal event with intelligent */ 1248 /* throttling disabled */ 1249 #define ERR_FAT_THR_F1 0x01 /* catastrophic on-die thermal event */ 1250 1251 #define ERR_NF_THR_F5 0x10 /* deadman timeout on cooling update */ 1252 #define ERR_NF_THR_F4 0x08 /* TSMAX Updated */ 1253 #define ERR_NF_THR_F3 0x04 /* On-die throttling event */ 1254 1255 #define EMASK_THR_FATAL (ERR_FAT_THR_F2|ERR_FAT_THR_F1) 1256 #define EMASK_THR_NF (ERR_NF_THR_F5|ERR_NF_THR_F4|ERR_NF_THR_F3) 1257 1258 #define EMASK_THR_F5 0x0010 /* deadman timeout on cooling update */ 1259 #define EMASK_THR_F4 0x0008 /* TSMAX Updated */ 1260 #define EMASK_THR_F3 0x0004 /* On-die throttling event */ 1261 #define EMASK_THR_F2 0x0002 /* >tnid thermal event with intelligent */ 1262 /* throttling disabled */ 1263 #define EMASK_THR_F1 0x0001 /* catastrophic on-die thermal event */ 1264 1265 #ifdef __cplusplus 1266 } 1267 #endif 1268 1269 #endif /* _NB5000_H */ 1270