1 /* BEGIN CSTYLED */ 2 3 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 4 */ 5 /* 6 * 7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * Copyright (c) 2009, Intel Corporation. 9 * All Rights Reserved. 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the 13 * "Software"), to deal in the Software without restriction, including 14 * without limitation the rights to use, copy, modify, merge, publish, 15 * distribute, sub license, and/or sell copies of the Software, and to 16 * permit persons to whom the Software is furnished to do so, subject to 17 * the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the 20 * next paragraph) shall be included in all copies or substantial portions 21 * of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 24 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 26 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 27 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 30 * 31 */ 32 33 /* 34 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 35 * Use is subject to license terms. 36 */ 37 38 #ifndef _I915_DRV_H 39 #define _I915_DRV_H 40 41 /* General customization: 42 */ 43 44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46 #define DRIVER_NAME "i915" 47 #define DRIVER_DESC "Intel Graphics" 48 #define DRIVER_DATE "20080730" 49 50 #if defined(__SVR4) && defined(__sun) 51 #define spinlock_t kmutex_t 52 #endif 53 54 #define I915_NUM_PIPE 2 55 56 #define I915_NUM_PIPE 2 57 58 /* Interface history: 59 * 60 * 1.1: Original. 61 * 1.2: Add Power Management 62 * 1.3: Add vblank support 63 * 1.4: Fix cmdbuffer path, add heap destroy 64 * 1.5: Add vblank pipe configuration 65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 66 * - Support vertical blank on secondary display pipe 67 */ 68 #define DRIVER_MAJOR 1 69 #define DRIVER_MINOR 6 70 #define DRIVER_PATCHLEVEL 0 71 72 #if defined(__linux__) 73 #define I915_HAVE_FENCE 74 #define I915_HAVE_BUFFER 75 #endif 76 #define I915_HAVE_GEM 1 77 78 typedef struct _drm_i915_ring_buffer { 79 int tail_mask; 80 unsigned long Size; 81 u8 *virtual_start; 82 int head; 83 int tail; 84 int space; 85 drm_local_map_t map; 86 struct drm_gem_object *ring_obj; 87 } drm_i915_ring_buffer_t; 88 89 struct mem_block { 90 struct mem_block *next; 91 struct mem_block *prev; 92 int start; 93 int size; 94 drm_file_t *filp; /* 0: free, -1: heap, other: real files */ 95 }; 96 97 typedef struct _drm_i915_vbl_swap { 98 struct list_head head; 99 drm_drawable_t drw_id; 100 unsigned int plane; 101 unsigned int sequence; 102 int flip; 103 } drm_i915_vbl_swap_t; 104 105 typedef struct s3_i915_private { 106 ddi_acc_handle_t saveHandle; 107 caddr_t saveAddr; 108 uint32_t pgtbl_ctl; 109 uint8_t saveLBB; 110 uint32_t saveDSPACNTR; 111 uint32_t saveDSPBCNTR; 112 uint32_t saveDSPARB; 113 uint32_t saveRENDERSTANDBY; 114 uint32_t saveHWS; 115 uint32_t savePIPEACONF; 116 uint32_t savePIPEBCONF; 117 uint32_t savePIPEASRC; 118 uint32_t savePIPEBSRC; 119 uint32_t saveFPA0; 120 uint32_t saveFPA1; 121 uint32_t saveDPLL_A; 122 uint32_t saveDPLL_A_MD; 123 uint32_t saveHTOTAL_A; 124 uint32_t saveHBLANK_A; 125 uint32_t saveHSYNC_A; 126 uint32_t saveVTOTAL_A; 127 uint32_t saveVBLANK_A; 128 uint32_t saveVSYNC_A; 129 uint32_t saveBCLRPAT_A; 130 uint32_t saveDSPASTRIDE; 131 uint32_t saveDSPASIZE; 132 uint32_t saveDSPAPOS; 133 uint32_t saveDSPABASE; 134 uint32_t saveDSPASURF; 135 uint32_t saveDSPATILEOFF; 136 uint32_t savePFIT_PGM_RATIOS; 137 uint32_t saveBLC_PWM_CTL; 138 uint32_t saveBLC_PWM_CTL2; 139 uint32_t saveFPB0; 140 uint32_t saveFPB1; 141 uint32_t saveDPLL_B; 142 uint32_t saveDPLL_B_MD; 143 uint32_t saveHTOTAL_B; 144 uint32_t saveHBLANK_B; 145 uint32_t saveHSYNC_B; 146 uint32_t saveVTOTAL_B; 147 uint32_t saveVBLANK_B; 148 uint32_t saveVSYNC_B; 149 uint32_t saveBCLRPAT_B; 150 uint32_t saveDSPBSTRIDE; 151 uint32_t saveDSPBSIZE; 152 uint32_t saveDSPBPOS; 153 uint32_t saveDSPBBASE; 154 uint32_t saveDSPBSURF; 155 uint32_t saveDSPBTILEOFF; 156 uint32_t saveVCLK_DIVISOR_VGA0; 157 uint32_t saveVCLK_DIVISOR_VGA1; 158 uint32_t saveVCLK_POST_DIV; 159 uint32_t saveVGACNTRL; 160 uint32_t saveADPA; 161 uint32_t saveLVDS; 162 uint32_t saveLVDSPP_ON; 163 uint32_t saveLVDSPP_OFF; 164 uint32_t saveDVOA; 165 uint32_t saveDVOB; 166 uint32_t saveDVOC; 167 uint32_t savePP_ON; 168 uint32_t savePP_OFF; 169 uint32_t savePP_CONTROL; 170 uint32_t savePP_CYCLE; 171 uint32_t savePFIT_CONTROL; 172 uint32_t save_palette_a[256]; 173 uint32_t save_palette_b[256]; 174 uint32_t saveFBC_CFB_BASE; 175 uint32_t saveFBC_LL_BASE; 176 uint32_t saveFBC_CONTROL; 177 uint32_t saveFBC_CONTROL2; 178 uint32_t saveIER; 179 uint32_t saveIIR; 180 uint32_t saveIMR; 181 uint32_t saveD_STATE; 182 uint32_t saveCG_2D_DIS; 183 uint32_t saveMI_ARB_STATE; 184 uint32_t savePIPEASTAT; 185 uint32_t savePIPEBSTAT; 186 uint32_t saveCACHE_MODE_0; 187 uint32_t saveSWF0[16]; 188 uint32_t saveSWF1[16]; 189 uint32_t saveSWF2[3]; 190 uint8_t saveMSR; 191 uint8_t saveSR[8]; 192 uint8_t saveGR[25]; 193 uint8_t saveAR_INDEX; 194 uint8_t saveAR[21]; 195 uint8_t saveDACMASK; 196 uint8_t saveDACDATA[256*3]; /* 256 3-byte colors */ 197 uint8_t saveCR[37]; 198 } s3_i915_private_t; 199 200 struct drm_i915_error_state { 201 u32 eir; 202 u32 pgtbl_er; 203 u32 pipeastat; 204 u32 pipebstat; 205 u32 ipeir; 206 u32 ipehr; 207 u32 instdone; 208 u32 acthd; 209 u32 instpm; 210 u32 instps; 211 u32 instdone1; 212 u32 seqno; 213 struct timeval time; 214 }; 215 216 typedef struct drm_i915_private { 217 struct drm_device *dev; 218 219 drm_local_map_t *sarea; 220 drm_local_map_t *mmio_map; 221 222 drm_i915_sarea_t *sarea_priv; 223 drm_i915_ring_buffer_t ring; 224 225 drm_dma_handle_t *status_page_dmah; 226 void *hw_status_page; 227 dma_addr_t dma_status_page; 228 uint32_t counter; 229 unsigned int status_gfx_addr; 230 drm_local_map_t hws_map; 231 struct drm_gem_object *hws_obj; 232 233 unsigned int cpp; 234 int back_offset; 235 int front_offset; 236 int current_page; 237 int page_flipping; 238 239 wait_queue_head_t irq_queue; 240 atomic_t irq_received; 241 /** Protects user_irq_refcount and irq_mask_reg */ 242 spinlock_t user_irq_lock; 243 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 244 int user_irq_refcount; 245 /** Cached value of IMR to avoid reads in updating the bitfield */ 246 int irq_mask_reg; 247 uint32_t pipestat[2]; 248 249 int tex_lru_log_granularity; 250 int allow_batchbuffer; 251 struct mem_block *agp_heap; 252 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 253 int vblank_pipe; 254 255 spinlock_t error_lock; 256 struct drm_i915_error_state *first_error; 257 258 struct { 259 struct drm_mm gtt_space; 260 261 drm_local_map_t gtt_mapping; 262 /** 263 * List of objects currently involved in rendering from the 264 * ringbuffer. 265 * 266 * A reference is held on the buffer while on this list. 267 */ 268 struct list_head active_list; 269 270 /** 271 * List of objects which are not in the ringbuffer but which 272 * still have a write_domain which needs to be flushed before 273 * unbinding. 274 * 275 * A reference is held on the buffer while on this list. 276 */ 277 struct list_head flushing_list; 278 279 /** 280 * LRU list of objects which are not in the ringbuffer and 281 * are ready to unbind, but are still in the GTT. 282 * 283 * A reference is not held on the buffer while on this list, 284 * as merely being GTT-bound shouldn't prevent its being 285 * freed, and we'll pull it off the list in the free path. 286 */ 287 struct list_head inactive_list; 288 289 /** 290 * List of breadcrumbs associated with GPU requests currently 291 * outstanding. 292 */ 293 struct list_head request_list; 294 295 uint32_t next_gem_seqno; 296 297 /** 298 * Waiting sequence number, if any 299 */ 300 uint32_t waiting_gem_seqno; 301 302 /** 303 * Last seq seen at irq time 304 */ 305 uint32_t irq_gem_seqno; 306 307 /** 308 * Flag if the X Server, and thus DRM, is not currently in 309 * control of the device. 310 * 311 * This is set between LeaveVT and EnterVT. It needs to be 312 * replaced with a semaphore. It also needs to be 313 * transitioned away from for kernel modesetting. 314 */ 315 int suspended; 316 317 /** 318 * Flag if the hardware appears to be wedged. 319 * 320 * This is set when attempts to idle the device timeout. 321 * It prevents command submission from occuring and makes 322 * every pending request fail 323 */ 324 int wedged; 325 326 /** Bit 6 swizzling required for X tiling */ 327 uint32_t bit_6_swizzle_x; 328 /** Bit 6 swizzling required for Y tiling */ 329 uint32_t bit_6_swizzle_y; 330 } mm; 331 332 } drm_i915_private_t; 333 334 struct drm_track { 335 struct drm_track *next, *prev; 336 caddr_t contain_ptr; 337 struct drm_gem_object *obj; 338 uint32_t name; 339 uint64_t offset; 340 341 }; 342 343 /** driver private structure attached to each drm_gem_object */ 344 struct drm_i915_gem_object { 345 /** This object's place on the active/flushing/inactive lists */ 346 struct list_head list; 347 348 struct drm_gem_object *obj; 349 350 /** Current space allocated to this object in the GTT, if any. */ 351 struct drm_mm_node *gtt_space; 352 353 354 /** 355 * This is set if the object is on the active or flushing lists 356 * (has pending rendering), and is not set if it's on inactive (ready 357 * to be unbound). 358 */ 359 int active; 360 361 /** 362 * This is set if the object has been written to since last bound 363 * to the GTT 364 */ 365 int dirty; 366 367 /** AGP memory structure for our GTT binding. */ 368 int agp_mem; 369 370 caddr_t *page_list; 371 372 pfn_t *pfnarray; 373 /** 374 * Current offset of the object in GTT space. 375 * 376 * This is the same as gtt_space->start 377 */ 378 uint32_t gtt_offset; 379 380 /** Boolean whether this object has a valid gtt offset. */ 381 int gtt_bound; 382 383 /** How many users have pinned this object in GTT space */ 384 int pin_count; 385 386 /** Breadcrumb of last rendering to the buffer. */ 387 uint32_t last_rendering_seqno; 388 389 /** Current tiling mode for the object. */ 390 uint32_t tiling_mode; 391 uint32_t stride; 392 /** 393 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 394 * GEM_DOMAIN_CPU is not in the object's read domain. 395 */ 396 uint8_t *page_cpu_valid; 397 /** User space pin count and filp owning the pin */ 398 uint32_t user_pin_count; 399 struct drm_file *pin_filp; 400 /** 401 * Used for checking the object doesn't appear more than once 402 * in an execbuffer object list. 403 */ 404 int in_execbuffer; 405 }; 406 407 /** 408 * Request queue structure. 409 * 410 * The request queue allows us to note sequence numbers that have been emitted 411 * and may be associated with active buffers to be retired. 412 * 413 * By keeping this list, we can avoid having to do questionable 414 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 415 * an emission time with seqnos for tracking how far ahead of the GPU we are. 416 */ 417 struct drm_i915_gem_request { 418 struct list_head list; 419 420 /** GEM sequence number associated with this request. */ 421 uint32_t seqno; 422 423 /** Time at which this request was emitted, in jiffies. */ 424 unsigned long emitted_jiffies; 425 426 /** Cache domains that were flushed at the start of the request. */ 427 uint32_t flush_domains; 428 429 }; 430 431 struct drm_i915_file_private { 432 struct { 433 uint32_t last_gem_seqno; 434 uint32_t last_gem_throttle_seqno; 435 } mm; 436 }; 437 438 439 enum intel_chip_family { 440 CHIP_I8XX = 0x01, 441 CHIP_I9XX = 0x02, 442 CHIP_I915 = 0x04, 443 CHIP_I965 = 0x08, 444 }; 445 446 extern drm_ioctl_desc_t i915_ioctls[]; 447 extern int i915_max_ioctl; 448 extern void i915_save_display(struct drm_device *dev); 449 extern void i915_restore_display(struct drm_device *dev); 450 451 /* i915_dma.c */ 452 extern void i915_kernel_lost_context(drm_device_t * dev); 453 extern int i915_driver_load(struct drm_device *, unsigned long flags); 454 extern int i915_driver_unload(struct drm_device *dev); 455 extern int i915_driver_open(drm_device_t * dev, drm_file_t *file_priv); 456 extern void i915_driver_lastclose(drm_device_t * dev); 457 extern void i915_driver_preclose(drm_device_t * dev, drm_file_t *filp); 458 extern void i915_driver_postclose(drm_device_t * dev, 459 struct drm_file *file_priv); 460 extern int i915_driver_device_is_agp(drm_device_t * dev); 461 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 462 unsigned long arg); 463 extern int i915_emit_box(struct drm_device *dev, 464 struct drm_clip_rect __user *boxes, 465 int i, int DR1, int DR4); 466 extern void i915_emit_breadcrumb(struct drm_device *dev); 467 extern void i915_emit_mi_flush(drm_device_t *dev, uint32_t flush); 468 extern void i915_handle_error(struct drm_device *dev); 469 470 /* i915_irq.c */ 471 extern int i915_irq_emit(DRM_IOCTL_ARGS); 472 extern int i915_irq_wait(DRM_IOCTL_ARGS); 473 474 extern int i915_enable_vblank(struct drm_device *dev, int crtc); 475 extern void i915_disable_vblank(struct drm_device *dev, int crtc); 476 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 477 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 478 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 479 extern int i915_driver_irq_preinstall(drm_device_t * dev); 480 extern void i915_driver_irq_postinstall(drm_device_t * dev); 481 extern void i915_driver_irq_uninstall(drm_device_t * dev); 482 extern int i915_emit_irq(drm_device_t * dev); 483 extern int i915_vblank_swap(DRM_IOCTL_ARGS); 484 extern void i915_user_irq_on(drm_device_t * dev); 485 extern void i915_user_irq_off(drm_device_t * dev); 486 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); 487 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); 488 489 /* i915_mem.c */ 490 extern int i915_mem_alloc(DRM_IOCTL_ARGS); 491 extern int i915_mem_free(DRM_IOCTL_ARGS); 492 extern int i915_mem_init_heap(DRM_IOCTL_ARGS); 493 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); 494 extern void i915_mem_takedown(struct mem_block **heap); 495 extern void i915_mem_release(drm_device_t * dev, 496 drm_file_t *filp, struct mem_block *heap); 497 extern struct mem_block **get_heap(drm_i915_private_t *, int); 498 extern struct mem_block *find_block_by_proc(struct mem_block *, drm_file_t *); 499 extern void mark_block(drm_device_t *, struct mem_block *, int); 500 extern void free_block(struct mem_block *); 501 502 /* i915_gem.c */ 503 int i915_gem_init_ioctl(DRM_IOCTL_ARGS); 504 int i915_gem_create_ioctl(DRM_IOCTL_ARGS); 505 int i915_gem_pread_ioctl(DRM_IOCTL_ARGS); 506 int i915_gem_pwrite_ioctl(DRM_IOCTL_ARGS); 507 int i915_gem_mmap_ioctl(DRM_IOCTL_ARGS); 508 int i915_gem_set_domain_ioctl(DRM_IOCTL_ARGS); 509 int i915_gem_sw_finish_ioctl(DRM_IOCTL_ARGS); 510 int i915_gem_execbuffer(DRM_IOCTL_ARGS); 511 int i915_gem_pin_ioctl(DRM_IOCTL_ARGS); 512 int i915_gem_unpin_ioctl(DRM_IOCTL_ARGS); 513 int i915_gem_busy_ioctl(DRM_IOCTL_ARGS); 514 int i915_gem_throttle_ioctl(DRM_IOCTL_ARGS); 515 int i915_gem_entervt_ioctl(DRM_IOCTL_ARGS); 516 int i915_gem_leavevt_ioctl(DRM_IOCTL_ARGS); 517 int i915_gem_set_tiling(DRM_IOCTL_ARGS); 518 int i915_gem_get_tiling(DRM_IOCTL_ARGS); 519 int i915_gem_get_aperture_ioctl(DRM_IOCTL_ARGS); 520 void i915_gem_load(struct drm_device *dev); 521 int i915_gem_init_object(struct drm_gem_object *obj); 522 void i915_gem_free_object(struct drm_gem_object *obj); 523 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 524 void i915_gem_object_unpin(struct drm_gem_object *obj); 525 int i915_gem_object_unbind(struct drm_gem_object *obj, uint32_t type); 526 void i915_gem_lastclose(struct drm_device *dev); 527 uint32_t i915_get_gem_seqno(struct drm_device *dev); 528 void i915_gem_retire_requests(struct drm_device *dev); 529 void i915_gem_retire_work_handler(void *dev); 530 void i915_gem_clflush_object(struct drm_gem_object *obj); 531 int i915_gem_init_ringbuffer(struct drm_device *dev); 532 533 /* i915_gem_tiling.c */ 534 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 535 536 /* i915_gem_debug.c */ 537 void i915_gem_command_decode(uint32_t *data, int count, 538 uint32_t hw_offset, struct drm_device *dev); 539 /* i915_gem_regdump.c */ 540 int i915_reg_dump_show(struct drm_device *dev, void *v); 541 #ifdef I915_HAVE_FENCE 542 /* i915_fence.c */ 543 544 545 extern void i915_fence_handler(drm_device_t *dev); 546 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, 547 uint32_t flags, 548 uint32_t *sequence, 549 uint32_t *native_type); 550 extern void i915_poke_flush(drm_device_t *dev, uint32_t class); 551 extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); 552 #endif 553 554 #ifdef I915_HAVE_BUFFER 555 /* i915_buffer.c */ 556 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); 557 extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); 558 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); 559 extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, 560 drm_mem_type_manager_t *man); 561 extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); 562 extern int i915_move(drm_buffer_object_t *bo, int evict, 563 int no_wait, drm_bo_mem_reg_t *new_mem); 564 565 #endif 566 567 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 568 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 569 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 570 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 571 #define S3_READ(reg) \ 572 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) 573 #define S3_WRITE(reg, val) \ 574 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) = (val) 575 576 #define I915_VERBOSE 0 577 #define I915_RING_VALIDATE 0 578 579 #if I915_RING_VALIDATE 580 void i915_ring_validate(struct drm_device *dev, const char *func, int line); 581 #define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__) 582 #else 583 #define I915_RING_DO_VALIDATE(dev) 584 #endif 585 586 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 587 volatile unsigned char *virt; 588 589 590 #define I915_RING_VALIDATE 0 591 592 #if I915_RING_VALIDATE 593 void i915_ring_validate(struct drm_device *dev, const char *func, int line); 594 #define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__) 595 #else 596 #define I915_RING_DO_VALIDATE(dev) 597 #endif 598 599 #if I915_VERBOSE 600 #define BEGIN_LP_RING(n) do { \ 601 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 602 DRM_DEBUG("dev_priv->ring.virtual_start (%lx)\n", (dev_priv->ring.virtual_start)); \ 603 I915_RING_DO_VALIDATE(dev); \ 604 if (dev_priv->ring.space < (n)*4) \ 605 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 606 outcount = 0; \ 607 outring = dev_priv->ring.tail; \ 608 ringmask = dev_priv->ring.tail_mask; \ 609 virt = dev_priv->ring.virtual_start; \ 610 } while (*"\0") 611 #else 612 #define BEGIN_LP_RING(n) do { \ 613 I915_RING_DO_VALIDATE(dev); \ 614 if (dev_priv->ring.space < (n)*4) \ 615 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 616 outcount = 0; \ 617 outring = dev_priv->ring.tail; \ 618 ringmask = dev_priv->ring.tail_mask; \ 619 virt = dev_priv->ring.virtual_start; \ 620 } while (*"\0") 621 #endif 622 623 #if I915_VERBOSE 624 #define OUT_RING(n) do { \ 625 DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 626 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 627 outcount++; \ 628 outring += 4; \ 629 outring &= ringmask; \ 630 } while (*"\0") 631 #else 632 #define OUT_RING(n) do { \ 633 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 634 outcount++; \ 635 outring += 4; \ 636 outring &= ringmask; \ 637 } while (*"\0") 638 #endif 639 640 #if I915_VERBOSE 641 #define ADVANCE_LP_RING() do { \ 642 DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 643 I915_RING_DO_VALIDATE(dev); \ 644 dev_priv->ring.tail = outring; \ 645 dev_priv->ring.space -= outcount * 4; \ 646 I915_WRITE(PRB0_TAIL, outring); \ 647 } while (*"\0") 648 #else 649 #define ADVANCE_LP_RING() do { \ 650 I915_RING_DO_VALIDATE(dev); \ 651 dev_priv->ring.tail = outring; \ 652 dev_priv->ring.space -= outcount * 4; \ 653 I915_WRITE(PRB0_TAIL, outring); \ 654 } while (*"\0") 655 #endif 656 657 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); 658 659 /* Extended config space */ 660 #define LBB 0xf4 661 #define GDRST 0xc0 662 #define GDRST_FULL (0<<2) 663 #define GDRST_RENDER (1<<2) 664 #define GDRST_MEDIA (3<<2) 665 666 /* VGA stuff */ 667 668 #define VGA_ST01_MDA 0x3ba 669 #define VGA_ST01_CGA 0x3da 670 671 #define VGA_MSR_WRITE 0x3c2 672 #define VGA_MSR_READ 0x3cc 673 #define VGA_MSR_MEM_EN (1<<1) 674 #define VGA_MSR_CGA_MODE (1<<0) 675 676 #define VGA_SR_INDEX 0x3c4 677 #define VGA_SR_DATA 0x3c5 678 679 #define VGA_AR_INDEX 0x3c0 680 #define VGA_AR_VID_EN (1<<5) 681 #define VGA_AR_DATA_WRITE 0x3c0 682 #define VGA_AR_DATA_READ 0x3c1 683 684 #define VGA_GR_INDEX 0x3ce 685 #define VGA_GR_DATA 0x3cf 686 /* GR05 */ 687 #define VGA_GR_MEM_READ_MODE_SHIFT 3 688 #define VGA_GR_MEM_READ_MODE_PLANE 1 689 /* GR06 */ 690 #define VGA_GR_MEM_MODE_MASK 0xc 691 #define VGA_GR_MEM_MODE_SHIFT 2 692 #define VGA_GR_MEM_A0000_AFFFF 0 693 #define VGA_GR_MEM_A0000_BFFFF 1 694 #define VGA_GR_MEM_B0000_B7FFF 2 695 #define VGA_GR_MEM_B0000_BFFFF 3 696 697 #define VGA_DACMASK 0x3c6 698 #define VGA_DACRX 0x3c7 699 #define VGA_DACWX 0x3c8 700 #define VGA_DACDATA 0x3c9 701 702 #define VGA_CR_INDEX_MDA 0x3b4 703 #define VGA_CR_DATA_MDA 0x3b5 704 #define VGA_CR_INDEX_CGA 0x3d4 705 #define VGA_CR_DATA_CGA 0x3d5 706 707 708 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 709 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 710 #define CMD_REPORT_HEAD (7<<23) 711 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 712 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 713 714 #define INST_PARSER_CLIENT 0x00000000 715 #define INST_OP_FLUSH 0x02000000 716 #define INST_FLUSH_MAP_CACHE 0x00000001 717 718 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 719 #define MI_USER_INTERRUPT MI_INSTR(2, (0 << 29)) 720 #define MI_FLUSH (0x04 << 23) 721 #define MI_NO_WRITE_FLUSH (1 << 2) 722 #define MI_READ_FLUSH (1 << 0) 723 #define MI_EXE_FLUSH (1 << 1) 724 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 725 #define MI_STORE_DWORD_INDEX_SHIFT 2 726 727 #define BB1_START_ADDR_MASK (~0x7) 728 #define BB1_PROTECTED (1<<0) 729 #define BB1_UNPROTECTED (0<<0) 730 #define BB2_END_ADDR_MASK (~0x7) 731 732 #define I915REG_PGTBL_CTRL 0x2020 733 #define IPEIR 0x02088 734 #define HWSTAM 0x02098 735 #define IIR 0x020a4 736 #define IMR 0x020a8 737 #define IER 0x020a0 738 #define INSTPM 0x020c0 739 #define ACTHD 0x020c8 740 #define PIPEASTAT 0x70024 741 #define PIPEBSTAT 0x71024 742 #define ACTHD_I965 0x02074 743 #define HWS_PGA 0x02080 744 #define IPEIR_I965 0x02064 745 #define IPEHR_I965 0x02068 746 #define INSTDONE_I965 0x0206c 747 #define INSTPS 0x02070 /* 965+ only */ 748 #define INSTDONE1 0x0207c /* 965+ only */ 749 #define IPEHR 0x0208c 750 #define INSTDONE 0x02090 751 #define EIR 0x020b0 752 #define EMR 0x020b4 753 #define ESR 0x020b8 754 #define GM45_ERROR_PAGE_TABLE (1<<5) 755 #define GM45_ERROR_MEM_PRIV (1<<4) 756 #define I915_ERROR_PAGE_TABLE (1<<4) 757 #define GM45_ERROR_CP_PRIV (1<<3) 758 #define I915_ERROR_MEMORY_REFRESH (1<<1) 759 #define I915_ERROR_INSTRUCTION (1<<0) 760 761 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 762 #define I915_VBLANK_CLEAR (1UL<<1) 763 764 #define SRX_INDEX 0x3c4 765 #define SRX_DATA 0x3c5 766 #define SR01 1 767 #define SR01_SCREEN_OFF (1<<5) 768 769 #define PPCR 0x61204 770 #define PPCR_ON (1<<0) 771 772 #define DVOB 0x61140 773 #define DVOB_ON (1<<31) 774 #define DVOC 0x61160 775 #define DVOC_ON (1<<31) 776 #define LVDS 0x61180 777 #define LVDS_ON (1<<31) 778 779 #define ADPA 0x61100 780 #define ADPA_DPMS_MASK (~(3<<10)) 781 #define ADPA_DPMS_ON (0<<10) 782 #define ADPA_DPMS_SUSPEND (1<<10) 783 #define ADPA_DPMS_STANDBY (2<<10) 784 #define ADPA_DPMS_OFF (3<<10) 785 786 #ifdef NOPID 787 #undef NOPID 788 #endif 789 #define NOPID 0x2094 790 #define LP_RING 0x2030 791 #define HP_RING 0x2040 792 #define TAIL_ADDR 0x001FFFF8 793 #define HEAD_WRAP_COUNT 0xFFE00000 794 #define HEAD_WRAP_ONE 0x00200000 795 #define HEAD_ADDR 0x001FFFFC 796 #define RING_START 0x08 797 #define START_ADDR 0x0xFFFFF000 798 #define RING_LEN 0x0C 799 #define RING_NR_PAGES 0x001FF000 800 #define RING_REPORT_MASK 0x00000006 801 #define RING_REPORT_64K 0x00000002 802 #define RING_REPORT_128K 0x00000004 803 #define RING_NO_REPORT 0x00000000 804 #define RING_VALID_MASK 0x00000001 805 #define RING_VALID 0x00000001 806 #define RING_INVALID 0x00000000 807 #define PGTBL_ER 0x02024 808 #define PRB0_TAIL 0x02030 809 #define PRB0_HEAD 0x02034 810 #define PRB0_START 0x02038 811 #define PRB0_CTL 0x0203c 812 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 813 #define SC_UPDATE_SCISSOR (0x1<<1) 814 #define SC_ENABLE_MASK (0x1<<0) 815 #define SC_ENABLE (0x1<<0) 816 817 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 818 #define SCI_YMIN_MASK (0xffff<<16) 819 #define SCI_XMIN_MASK (0xffff<<0) 820 #define SCI_YMAX_MASK (0xffff<<16) 821 #define SCI_XMAX_MASK (0xffff<<0) 822 823 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 824 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 825 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 826 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 827 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 828 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 829 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 830 831 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 832 833 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 834 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 835 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 836 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 837 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) 838 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) 839 840 #define MI_BATCH_BUFFER ((0x30<<23)|1) 841 #define MI_BATCH_BUFFER_START (0x31<<23) 842 #define MI_BATCH_BUFFER_END (0xA<<23) 843 #define MI_BATCH_NON_SECURE (1) 844 845 #define MI_BATCH_NON_SECURE_I965 (1<<8) 846 847 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 848 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 849 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 850 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 851 852 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 853 854 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 855 #define ASYNC_FLIP (1<<22) 856 #define DISPLAY_PLANE_A (0<<20) 857 #define DISPLAY_PLANE_B (1<<20) 858 859 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 860 861 /** 862 * Reads a dword out of the status page, which is written to from the command 863 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 864 * MI_STORE_DATA_IMM. 865 * 866 * The following dwords have a reserved meaning: 867 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 868 * 0x04: ring 0 head pointer 869 * 0x05: ring 1 head pointer (915-class) 870 * 0x06: ring 2 head pointer (915-class) 871 * 0x10-0x1b: Context status DWords (GM45) 872 * 0x1f: Last written status offset. (GM45) 873 * 874 * The area from dword 0x20 to 0x3ff is available for driver usage. 875 */ 876 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 877 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 878 #define I915_GEM_HWS_INDEX 0x20 879 #define I915_BREADCRUMB_INDEX 0x21 880 881 /* 882 * add here for S3 support 883 */ 884 #define DPLL_A 0x06014 885 #define DPLL_B 0x06018 886 # define DPLL_VCO_ENABLE 0x80000000 /* (1 << 31) */ 887 # define DPLL_DVO_HIGH_SPEED (1 << 30) 888 # define DPLL_SYNCLOCK_ENABLE (1 << 29) 889 # define DPLL_VGA_MODE_DIS (1 << 28) 890 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 891 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 892 # define DPLL_MODE_MASK (3 << 26) 893 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 894 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 895 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 896 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 897 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 898 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 899 900 /** 901 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 902 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 903 */ 904 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 905 /** 906 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 907 * this field (only one bit may be set). 908 */ 909 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 910 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 911 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 912 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 913 # define PLL_REF_INPUT_DREFCLK (0 << 13) 914 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 915 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 916 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 917 # define PLL_REF_INPUT_MASK (3 << 13) 918 # define PLL_LOAD_PULSE_PHASE_SHIFT 9 919 /* 920 * Parallel to Serial Load Pulse phase selection. 921 * Selects the phase for the 10X DPLL clock for the PCIe 922 * digital display port. The range is 4 to 13; 10 or more 923 * is just a flip delay. The default is 6 924 */ 925 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 926 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 927 928 /** 929 * SDVO multiplier for 945G/GM. Not used on 965. 930 * 931 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 932 */ 933 # define SDVO_MULTIPLIER_MASK 0x000000ff 934 # define SDVO_MULTIPLIER_SHIFT_HIRES 4 935 # define SDVO_MULTIPLIER_SHIFT_VGA 0 936 937 /** @defgroup DPLL_MD 938 * @{ 939 */ 940 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 941 #define DPLL_A_MD 0x0601c 942 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 943 #define DPLL_B_MD 0x06020 944 /** 945 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 946 * 947 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 948 */ 949 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 950 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 951 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 952 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 953 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 954 /** 955 * SDVO/UDI pixel multiplier. 956 * 957 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 958 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 959 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 960 * dummy bytes in the datastream at an increased clock rate, with both sides of 961 * the link knowing how many bytes are fill. 962 * 963 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 964 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 965 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 966 * through an SDVO command. 967 * 968 * This register field has values of multiplication factor minus 1, with 969 * a maximum multiplier of 5 for SDVO. 970 */ 971 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 972 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 973 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 974 * This best be set to the default value (3) or the CRT won't work. No, 975 * I don't entirely understand what this does... 976 */ 977 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 978 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 979 /** @} */ 980 981 #define DPLL_TEST 0x606c 982 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 983 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 984 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 985 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 986 # define DPLLB_TEST_N_BYPASS (1 << 19) 987 # define DPLLB_TEST_M_BYPASS (1 << 18) 988 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 989 # define DPLLA_TEST_N_BYPASS (1 << 3) 990 # define DPLLA_TEST_M_BYPASS (1 << 2) 991 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 992 993 /* 994 * Palette registers 995 */ 996 #define PALETTE_A 0x0a000 997 #define PALETTE_B 0x0a800 998 999 /* MCH MMIO space */ 1000 1001 /* 1002 * MCHBAR mirror. 1003 * 1004 * This mirrors the MCHBAR MMIO space whose location is determined by 1005 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1006 * every way. It is not accessible from the CP register read instructions. 1007 * 1008 */ 1009 #define MCHBAR_MIRROR_BASE 0x10000 1010 1011 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 1012 #define DCC 0x10200 1013 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1014 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1015 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1016 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1017 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1018 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1019 1020 /** 965 MCH register controlling DRAM channel configuration */ 1021 #define C0DRB3 0x10206 1022 #define C1DRB3 0x10606 1023 1024 /** GM965 GM45 render standby register */ 1025 #define MCHBAR_RENDER_STANDBY 0x111B8 1026 1027 #define FPA0 0x06040 1028 #define FPA1 0x06044 1029 #define FPB0 0x06048 1030 #define FPB1 0x0604c 1031 1032 #define D_STATE 0x6104 1033 #define CG_2D_DIS 0x6200 1034 #define CG_3D_DIS 0x6204 1035 1036 #define MI_ARB_STATE 0x20e4 1037 1038 /* 1039 * Cache mode 0 reg. 1040 * - Manipulating render cache behaviour is central 1041 * to the concept of zone rendering, tuning this reg can help avoid 1042 * unnecessary render cache reads and even writes (for z/stencil) 1043 * at beginning and end of scene. 1044 * 1045 * - To change a bit, write to this reg with a mask bit set and the 1046 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. 1047 */ 1048 #define CACHE_MODE_0 0x2120 1049 1050 /* I830 CRTC registers */ 1051 #define HTOTAL_A 0x60000 1052 #define HBLANK_A 0x60004 1053 #define HSYNC_A 0x60008 1054 #define VTOTAL_A 0x6000c 1055 #define VBLANK_A 0x60010 1056 #define VSYNC_A 0x60014 1057 #define PIPEASRC 0x6001c 1058 #define BCLRPAT_A 0x60020 1059 #define VSYNCSHIFT_A 0x60028 1060 1061 #define HTOTAL_B 0x61000 1062 #define HBLANK_B 0x61004 1063 #define HSYNC_B 0x61008 1064 #define VTOTAL_B 0x6100c 1065 #define VBLANK_B 0x61010 1066 #define VSYNC_B 0x61014 1067 #define PIPEBSRC 0x6101c 1068 #define BCLRPAT_B 0x61020 1069 #define VSYNCSHIFT_B 0x61028 1070 1071 #define DSPACNTR 0x70180 1072 #define DSPBCNTR 0x71180 1073 #define DISPLAY_PLANE_ENABLE (1<<31) 1074 #define DISPLAY_PLANE_DISABLE 0 1075 #define DISPPLANE_GAMMA_ENABLE (1<<30) 1076 #define DISPPLANE_GAMMA_DISABLE 0 1077 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 1078 #define DISPPLANE_8BPP (0x2<<26) 1079 #define DISPPLANE_15_16BPP (0x4<<26) 1080 #define DISPPLANE_16BPP (0x5<<26) 1081 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1082 #define DISPPLANE_32BPP (0x7<<26) 1083 #define DISPPLANE_STEREO_ENABLE (1<<25) 1084 #define DISPPLANE_STEREO_DISABLE 0 1085 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 1086 #define DISPPLANE_SEL_PIPE_A 0 1087 #define DISPPLANE_SEL_PIPE_B (1<<24) 1088 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 1089 #define DISPPLANE_SRC_KEY_DISABLE 0 1090 #define DISPPLANE_LINE_DOUBLE (1<<20) 1091 #define DISPPLANE_NO_LINE_DOUBLE 0 1092 #define DISPPLANE_STEREO_POLARITY_FIRST 0 1093 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1094 /* plane B only */ 1095 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 1096 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 1097 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 1098 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 1099 1100 #define DSPABASE 0x70184 1101 #define DSPASTRIDE 0x70188 1102 1103 #define DSPBBASE 0x71184 1104 #define DSPBADDR DSPBBASE 1105 #define DSPBSTRIDE 0x71188 1106 1107 #define DSPAKEYVAL 0x70194 1108 #define DSPAKEYMASK 0x70198 1109 1110 #define DSPAPOS 0x7018C /* reserved */ 1111 #define DSPASIZE 0x70190 1112 #define DSPBPOS 0x7118C 1113 #define DSPBSIZE 0x71190 1114 1115 #define DSPASURF 0x7019C 1116 #define DSPATILEOFF 0x701A4 1117 1118 #define DSPBSURF 0x7119C 1119 #define DSPBTILEOFF 0x711A4 1120 1121 #define PIPEACONF 0x70008 1122 #define PIPEACONF_ENABLE (1UL<<31) 1123 #define PIPEACONF_DISABLE 0 1124 #define PIPEACONF_DOUBLE_WIDE (1<<30) 1125 #define I965_PIPECONF_ACTIVE (1<<30) 1126 #define PIPEACONF_SINGLE_WIDE 0 1127 #define PIPEACONF_PIPE_UNLOCKED 0 1128 #define PIPEACONF_PIPE_LOCKED (1<<25) 1129 #define PIPEACONF_PALETTE 0 1130 #define PIPEACONF_GAMMA (1<<24) 1131 #define PIPECONF_FORCE_BORDER (1<<25) 1132 #define PIPECONF_PROGRESSIVE (0 << 21) 1133 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1134 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1135 1136 #define PIPEBCONF 0x71008 1137 #define PIPEBCONF_ENABLE (1UL<<31) 1138 #define PIPEBCONF_DISABLE 0 1139 #define PIPEBCONF_DOUBLE_WIDE (1<<30) 1140 #define PIPEBCONF_DISABLE 0 1141 #define PIPEBCONF_GAMMA (1<<24) 1142 #define PIPEBCONF_PALETTE 0 1143 1144 #define BLC_PWM_CTL 0x61254 1145 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1146 1147 #define BLC_PWM_CTL2 0x61250 1148 1149 #define PFIT_CONTROL 0x61230 1150 #define PFIT_PGM_RATIOS 0x61234 1151 1152 /** 1153 * Indicates that all dependencies of the panel are on: 1154 * 1155 * - PLL enabled 1156 * - pipe enabled 1157 * - LVDS/DVOB/DVOC on 1158 */ 1159 #define PP_READY (1 << 30) 1160 #define PP_SEQUENCE_NONE (0 << 28) 1161 #define PP_SEQUENCE_ON (1 << 28) 1162 #define PP_SEQUENCE_OFF (2 << 28) 1163 #define PP_SEQUENCE_MASK 0x30000000 1164 #define PP_CONTROL 0x61204 1165 #define POWER_TARGET_ON (1 << 0) 1166 1167 #define LVDSPP_ON 0x61208 1168 #define LVDSPP_OFF 0x6120c 1169 #define PP_CYCLE 0x61210 1170 1171 /* Framebuffer compression */ 1172 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1173 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1174 #define FBC_CONTROL 0x03208 1175 1176 #define VGACNTRL 0x71400 1177 1178 #define VCLK_DIVISOR_VGA0 0x6000 1179 #define VCLK_DIVISOR_VGA1 0x6004 1180 #define VCLK_POST_DIV 0x6010 1181 1182 /* Framebuffer compression */ 1183 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1184 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1185 #define FBC_CONTROL 0x03208 1186 #define FBC_CTL_EN (1<<31) 1187 #define FBC_CTL_PERIODIC (1<<30) 1188 #define FBC_CTL_INTERVAL_SHIFT (16) 1189 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 1190 #define FBC_CTL_STRIDE_SHIFT (5) 1191 #define FBC_CTL_FENCENO (1<<0) 1192 #define FBC_COMMAND 0x0320c 1193 #define FBC_CMD_COMPRESS (1<<0) 1194 #define FBC_STATUS 0x03210 1195 #define FBC_STAT_COMPRESSING (1<<31) 1196 #define FBC_STAT_COMPRESSED (1<<30) 1197 #define FBC_STAT_MODIFIED (1<<29) 1198 #define FBC_STAT_CURRENT_LINE (1<<0) 1199 #define FBC_CONTROL2 0x03214 1200 #define FBC_CTL_FENCE_DBL (0<<4) 1201 #define FBC_CTL_IDLE_IMM (0<<2) 1202 #define FBC_CTL_IDLE_FULL (1<<2) 1203 #define FBC_CTL_IDLE_LINE (2<<2) 1204 #define FBC_CTL_IDLE_DEBUG (3<<2) 1205 #define FBC_CTL_CPU_FENCE (1<<1) 1206 #define FBC_CTL_PLANEA (0<<0) 1207 #define FBC_CTL_PLANEB (1<<0) 1208 #define FBC_FENCE_OFF 0x0321b 1209 1210 #define FBC_LL_SIZE (1536) 1211 #define FBC_LL_PAD (32) 1212 1213 #define DSPARB 0x70030 1214 1215 #define PIPEAFRAMEHIGH 0x70040 1216 #define PIPEBFRAMEHIGH 0x71040 1217 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 1218 #define PIPE_FRAME_HIGH_SHIFT 0 1219 #define PIPEAFRAMEPIXEL 0x70044 1220 #define PIPEBFRAMEPIXEL 0x71044 1221 1222 #define PIPE_FRAME_LOW_MASK 0xff000000 1223 #define PIPE_FRAME_LOW_SHIFT 24 1224 1225 /* Interrupt bits: 1226 */ 1227 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 1228 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 1229 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 1230 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 1231 #define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */ 1232 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 1233 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 1234 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 1235 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 1236 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 1237 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 1238 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 1239 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 1240 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 1241 #define I915_DEBUG_INTERRUPT (1<<2) 1242 #define I915_USER_INTERRUPT (1<<1) 1243 #define I915_ASLE_INTERRUPT (1<<0) 1244 1245 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 1246 #define I915_CRC_ERROR_ENABLE (1UL<<29) 1247 #define I915_CRC_DONE_ENABLE (1UL<<28) 1248 #define I915_GMBUS_EVENT_ENABLE (1UL<<27) 1249 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1250 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1251 #define I915_DPST_EVENT_ENABLE (1UL<<23) 1252 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1253 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1254 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1255 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1256 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1257 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 1258 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1259 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1260 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 1261 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 1262 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1263 #define I915_DPST_EVENT_STATUS (1UL<<7) 1264 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1265 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1266 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1267 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1268 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1269 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 1270 1271 /* GM45+ just has to be different */ 1272 #define PIPEA_FRMCOUNT_GM45 0x70040 1273 #define PIPEA_FLIPCOUNT_GM45 0x70044 1274 #define PIPEB_FRMCOUNT_GM45 0x71040 1275 #define PIPEB_FLIPCOUNT_GM45 0x71044 1276 1277 /* 1278 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 1279 * of video memory available to the BIOS in SWF1. 1280 */ 1281 1282 #define SWF0 0x71410 1283 1284 /* 1285 * 855 scratch registers. 1286 */ 1287 #define SWF10 0x70410 1288 1289 #define SWF30 0x72414 1290 1291 #define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 1292 #define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 1293 #define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 1294 #define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 1295 #define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 1296 #define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 1297 #define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 1298 #define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 1299 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 1300 #define PCI_DEVICE_ID_INTEL_82946_GZ 0x2972 1301 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 1302 #define PCI_DEVICE_ID_INTEL_82Q963_IG 0x2992 1303 #define PCI_DEVICE_ID_INTEL_82G965_IG 0x29a2 1304 #define PCI_DEVICE_ID_INTEL_GM965_IG 0x2a02 1305 #define PCI_DEVICE_ID_INTEL_GME965_IG 0x2a12 1306 #define PCI_DEVICE_ID_INTEL_82G33_IG 0x29c2 1307 #define PCI_DEVICE_ID_INTEL_82Q35_IG 0x29b2 1308 #define PCI_DEVICE_ID_INTEL_82Q33_IG 0x29d2 1309 #define PCI_DEVICE_ID_INTEL_CANTIGA_IG 0x2a42 1310 #define PCI_DEVICE_ID_INTEL_EL_IG 0x2e02 1311 #define PCI_DEVICE_ID_INTEL_82Q45_IG 0x2e12 1312 #define PCI_DEVICE_ID_INTEL_82G45_IG 0x2e22 1313 #define PCI_DEVICE_ID_INTEL_82G41_IG 0x2e32 1314 #define PCI_DEVICE_ID_INTEL_82B43_IG 0x2e42 1315 1316 1317 #define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC) 1318 #define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG) 1319 #define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 1320 #define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 1321 #define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG) 1322 1323 #define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG) 1324 #define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG) 1325 #define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG) 1326 #define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG || \ 1327 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GME_IG) 1328 1329 #define IS_I965G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82946_GZ || \ 1330 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G35_IG || \ 1331 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q963_IG || \ 1332 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G965_IG || \ 1333 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG || \ 1334 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GME965_IG || \ 1335 (dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG || \ 1336 (dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1337 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1338 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1339 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82B43_IG || \ 1340 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1341 1342 #define IS_I965GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG) 1343 1344 #define IS_GM45(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG) 1345 1346 #define IS_G4X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1347 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1348 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1349 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82B43_IG || \ 1350 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1351 1352 #define IS_G33(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82G33_IG || \ 1353 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q35_IG || \ 1354 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q33_IG) 1355 1356 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1357 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1358 1359 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1360 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 1361 1362 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1363 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1364 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1365 1366 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 1367 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1368 * rows, which changed the alignment requirements and fence programming. 1369 */ 1370 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 1371 IS_I915GM(dev))) 1372 1373 #endif /* _I915_DRV_H */ 1374