1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. 29 * Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T 30 * All Rights Reserved 31 */ 32 33#pragma ident "%Z%%M% %I% %E% SMI" 34 35/* 36 * General assembly language routines. 37 * It is the intent of this file to contain routines that are 38 * independent of the specific kernel architecture, and those that are 39 * common across kernel architectures. 40 * As architectures diverge, and implementations of specific 41 * architecture-dependent routines change, the routines should be moved 42 * from this file into the respective ../`arch -k`/subr.s file. 43 */ 44 45#include <sys/asm_linkage.h> 46#include <sys/asm_misc.h> 47#include <sys/panic.h> 48#include <sys/ontrap.h> 49#include <sys/regset.h> 50#include <sys/privregs.h> 51#include <sys/reboot.h> 52#include <sys/psw.h> 53#include <sys/x86_archext.h> 54 55#if defined(__lint) 56#include <sys/types.h> 57#include <sys/systm.h> 58#include <sys/thread.h> 59#include <sys/archsystm.h> 60#include <sys/byteorder.h> 61#include <sys/dtrace.h> 62#else /* __lint */ 63#include "assym.h" 64#endif /* __lint */ 65#include <sys/dditypes.h> 66 67/* 68 * on_fault() 69 * Catch lofault faults. Like setjmp except it returns one 70 * if code following causes uncorrectable fault. Turned off 71 * by calling no_fault(). 72 */ 73 74#if defined(__lint) 75 76/* ARGSUSED */ 77int 78on_fault(label_t *ljb) 79{ return (0); } 80 81void 82no_fault(void) 83{} 84 85#else /* __lint */ 86 87#if defined(__amd64) 88 89 ENTRY(on_fault) 90 movq %gs:CPU_THREAD, %rsi 91 leaq catch_fault(%rip), %rdx 92 movq %rdi, T_ONFAULT(%rsi) /* jumpbuf in t_onfault */ 93 movq %rdx, T_LOFAULT(%rsi) /* catch_fault in t_lofault */ 94 jmp setjmp /* let setjmp do the rest */ 95 96catch_fault: 97 movq %gs:CPU_THREAD, %rsi 98 movq T_ONFAULT(%rsi), %rdi /* address of save area */ 99 xorl %eax, %eax 100 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 101 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 102 jmp longjmp /* let longjmp do the rest */ 103 SET_SIZE(on_fault) 104 105 ENTRY(no_fault) 106 movq %gs:CPU_THREAD, %rsi 107 xorl %eax, %eax 108 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 109 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 110 ret 111 SET_SIZE(no_fault) 112 113#elif defined(__i386) 114 115 ENTRY(on_fault) 116 movl %gs:CPU_THREAD, %edx 117 movl 4(%esp), %eax /* jumpbuf address */ 118 leal catch_fault, %ecx 119 movl %eax, T_ONFAULT(%edx) /* jumpbuf in t_onfault */ 120 movl %ecx, T_LOFAULT(%edx) /* catch_fault in t_lofault */ 121 jmp setjmp /* let setjmp do the rest */ 122 123catch_fault: 124 movl %gs:CPU_THREAD, %edx 125 xorl %eax, %eax 126 movl T_ONFAULT(%edx), %ecx /* address of save area */ 127 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 128 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 129 pushl %ecx 130 call longjmp /* let longjmp do the rest */ 131 SET_SIZE(on_fault) 132 133 ENTRY(no_fault) 134 movl %gs:CPU_THREAD, %edx 135 xorl %eax, %eax 136 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 137 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 138 ret 139 SET_SIZE(no_fault) 140 141#endif /* __i386 */ 142#endif /* __lint */ 143 144/* 145 * Default trampoline code for on_trap() (see <sys/ontrap.h>). We just 146 * do a longjmp(&curthread->t_ontrap->ot_jmpbuf) if this is ever called. 147 */ 148 149#if defined(lint) 150 151void 152on_trap_trampoline(void) 153{} 154 155#else /* __lint */ 156 157#if defined(__amd64) 158 159 ENTRY(on_trap_trampoline) 160 movq %gs:CPU_THREAD, %rsi 161 movq T_ONTRAP(%rsi), %rdi 162 addq $OT_JMPBUF, %rdi 163 jmp longjmp 164 SET_SIZE(on_trap_trampoline) 165 166#elif defined(__i386) 167 168 ENTRY(on_trap_trampoline) 169 movl %gs:CPU_THREAD, %eax 170 movl T_ONTRAP(%eax), %eax 171 addl $OT_JMPBUF, %eax 172 pushl %eax 173 call longjmp 174 SET_SIZE(on_trap_trampoline) 175 176#endif /* __i386 */ 177#endif /* __lint */ 178 179/* 180 * Push a new element on to the t_ontrap stack. Refer to <sys/ontrap.h> for 181 * more information about the on_trap() mechanism. If the on_trap_data is the 182 * same as the topmost stack element, we just modify that element. 183 */ 184#if defined(lint) 185 186/*ARGSUSED*/ 187int 188on_trap(on_trap_data_t *otp, uint_t prot) 189{ return (0); } 190 191#else /* __lint */ 192 193#if defined(__amd64) 194 195 ENTRY(on_trap) 196 movw %si, OT_PROT(%rdi) /* ot_prot = prot */ 197 movw $0, OT_TRAP(%rdi) /* ot_trap = 0 */ 198 leaq on_trap_trampoline(%rip), %rdx /* rdx = &on_trap_trampoline */ 199 movq %rdx, OT_TRAMPOLINE(%rdi) /* ot_trampoline = rdx */ 200 xorl %ecx, %ecx 201 movq %rcx, OT_HANDLE(%rdi) /* ot_handle = NULL */ 202 movq %rcx, OT_PAD1(%rdi) /* ot_pad1 = NULL */ 203 movq %gs:CPU_THREAD, %rdx /* rdx = curthread */ 204 movq T_ONTRAP(%rdx), %rcx /* rcx = curthread->t_ontrap */ 205 cmpq %rdi, %rcx /* if (otp == %rcx) */ 206 je 0f /* don't modify t_ontrap */ 207 208 movq %rcx, OT_PREV(%rdi) /* ot_prev = t_ontrap */ 209 movq %rdi, T_ONTRAP(%rdx) /* curthread->t_ontrap = otp */ 210 2110: addq $OT_JMPBUF, %rdi /* &ot_jmpbuf */ 212 jmp setjmp 213 SET_SIZE(on_trap) 214 215#elif defined(__i386) 216 217 ENTRY(on_trap) 218 movl 4(%esp), %eax /* %eax = otp */ 219 movl 8(%esp), %edx /* %edx = prot */ 220 221 movw %dx, OT_PROT(%eax) /* ot_prot = prot */ 222 movw $0, OT_TRAP(%eax) /* ot_trap = 0 */ 223 leal on_trap_trampoline, %edx /* %edx = &on_trap_trampoline */ 224 movl %edx, OT_TRAMPOLINE(%eax) /* ot_trampoline = %edx */ 225 movl $0, OT_HANDLE(%eax) /* ot_handle = NULL */ 226 movl $0, OT_PAD1(%eax) /* ot_pad1 = NULL */ 227 movl %gs:CPU_THREAD, %edx /* %edx = curthread */ 228 movl T_ONTRAP(%edx), %ecx /* %ecx = curthread->t_ontrap */ 229 cmpl %eax, %ecx /* if (otp == %ecx) */ 230 je 0f /* don't modify t_ontrap */ 231 232 movl %ecx, OT_PREV(%eax) /* ot_prev = t_ontrap */ 233 movl %eax, T_ONTRAP(%edx) /* curthread->t_ontrap = otp */ 234 2350: addl $OT_JMPBUF, %eax /* %eax = &ot_jmpbuf */ 236 movl %eax, 4(%esp) /* put %eax back on the stack */ 237 jmp setjmp /* let setjmp do the rest */ 238 SET_SIZE(on_trap) 239 240#endif /* __i386 */ 241#endif /* __lint */ 242 243/* 244 * Setjmp and longjmp implement non-local gotos using state vectors 245 * type label_t. 246 */ 247 248#if defined(__lint) 249 250/* ARGSUSED */ 251int 252setjmp(label_t *lp) 253{ return (0); } 254 255/* ARGSUSED */ 256void 257longjmp(label_t *lp) 258{} 259 260#else /* __lint */ 261 262#if LABEL_PC != 0 263#error LABEL_PC MUST be defined as 0 for setjmp/longjmp to work as coded 264#endif /* LABEL_PC != 0 */ 265 266#if defined(__amd64) 267 268 ENTRY(setjmp) 269 movq %rsp, LABEL_SP(%rdi) 270 movq %rbp, LABEL_RBP(%rdi) 271 movq %rbx, LABEL_RBX(%rdi) 272 movq %r12, LABEL_R12(%rdi) 273 movq %r13, LABEL_R13(%rdi) 274 movq %r14, LABEL_R14(%rdi) 275 movq %r15, LABEL_R15(%rdi) 276 movq (%rsp), %rdx /* return address */ 277 movq %rdx, (%rdi) /* LABEL_PC is 0 */ 278 xorl %eax, %eax /* return 0 */ 279 ret 280 SET_SIZE(setjmp) 281 282 ENTRY(longjmp) 283 movq LABEL_SP(%rdi), %rsp 284 movq LABEL_RBP(%rdi), %rbp 285 movq LABEL_RBX(%rdi), %rbx 286 movq LABEL_R12(%rdi), %r12 287 movq LABEL_R13(%rdi), %r13 288 movq LABEL_R14(%rdi), %r14 289 movq LABEL_R15(%rdi), %r15 290 movq (%rdi), %rdx /* return address; LABEL_PC is 0 */ 291 movq %rdx, (%rsp) 292 xorl %eax, %eax 293 incl %eax /* return 1 */ 294 ret 295 SET_SIZE(longjmp) 296 297#elif defined(__i386) 298 299 ENTRY(setjmp) 300 movl 4(%esp), %edx /* address of save area */ 301 movl %ebp, LABEL_EBP(%edx) 302 movl %ebx, LABEL_EBX(%edx) 303 movl %esi, LABEL_ESI(%edx) 304 movl %edi, LABEL_EDI(%edx) 305 movl %esp, 4(%edx) 306 movl (%esp), %ecx /* %eip (return address) */ 307 movl %ecx, (%edx) /* LABEL_PC is 0 */ 308 subl %eax, %eax /* return 0 */ 309 ret 310 SET_SIZE(setjmp) 311 312 ENTRY(longjmp) 313 movl 4(%esp), %edx /* address of save area */ 314 movl LABEL_EBP(%edx), %ebp 315 movl LABEL_EBX(%edx), %ebx 316 movl LABEL_ESI(%edx), %esi 317 movl LABEL_EDI(%edx), %edi 318 movl 4(%edx), %esp 319 movl (%edx), %ecx /* %eip (return addr); LABEL_PC is 0 */ 320 movl $1, %eax 321 addl $4, %esp /* pop ret adr */ 322 jmp *%ecx /* indirect */ 323 SET_SIZE(longjmp) 324 325#endif /* __i386 */ 326#endif /* __lint */ 327 328/* 329 * if a() calls b() calls caller(), 330 * caller() returns return address in a(). 331 * (Note: We assume a() and b() are C routines which do the normal entry/exit 332 * sequence.) 333 */ 334 335#if defined(__lint) 336 337caddr_t 338caller(void) 339{ return (0); } 340 341#else /* __lint */ 342 343#if defined(__amd64) 344 345 ENTRY(caller) 346 movq 8(%rbp), %rax /* b()'s return pc, in a() */ 347 ret 348 SET_SIZE(caller) 349 350#elif defined(__i386) 351 352 ENTRY(caller) 353 movl 4(%ebp), %eax /* b()'s return pc, in a() */ 354 ret 355 SET_SIZE(caller) 356 357#endif /* __i386 */ 358#endif /* __lint */ 359 360/* 361 * if a() calls callee(), callee() returns the 362 * return address in a(); 363 */ 364 365#if defined(__lint) 366 367caddr_t 368callee(void) 369{ return (0); } 370 371#else /* __lint */ 372 373#if defined(__amd64) 374 375 ENTRY(callee) 376 movq (%rsp), %rax /* callee()'s return pc, in a() */ 377 ret 378 SET_SIZE(callee) 379 380#elif defined(__i386) 381 382 ENTRY(callee) 383 movl (%esp), %eax /* callee()'s return pc, in a() */ 384 ret 385 SET_SIZE(callee) 386 387#endif /* __i386 */ 388#endif /* __lint */ 389 390/* 391 * return the current frame pointer 392 */ 393 394#if defined(__lint) 395 396greg_t 397getfp(void) 398{ return (0); } 399 400#else /* __lint */ 401 402#if defined(__amd64) 403 404 ENTRY(getfp) 405 movq %rbp, %rax 406 ret 407 SET_SIZE(getfp) 408 409#elif defined(__i386) 410 411 ENTRY(getfp) 412 movl %ebp, %eax 413 ret 414 SET_SIZE(getfp) 415 416#endif /* __i386 */ 417#endif /* __lint */ 418 419/* 420 * Invalidate a single page table entry in the TLB 421 */ 422 423#if defined(__lint) 424 425/* ARGSUSED */ 426void 427mmu_tlbflush_entry(caddr_t m) 428{} 429 430#else /* __lint */ 431 432#if defined(__amd64) 433 434 ENTRY(mmu_tlbflush_entry) 435 invlpg (%rdi) 436 ret 437 SET_SIZE(mmu_tlbflush_entry) 438 439#elif defined(__i386) 440 441 ENTRY(mmu_tlbflush_entry) 442 movl 4(%esp), %eax 443 invlpg (%eax) 444 ret 445 SET_SIZE(mmu_tlbflush_entry) 446 447#endif /* __i386 */ 448#endif /* __lint */ 449 450 451/* 452 * Get/Set the value of various control registers 453 */ 454 455#if defined(__lint) 456 457ulong_t 458getcr0(void) 459{ return (0); } 460 461/* ARGSUSED */ 462void 463setcr0(ulong_t value) 464{} 465 466ulong_t 467getcr2(void) 468{ return (0); } 469 470ulong_t 471getcr3(void) 472{ return (0); } 473 474/* ARGSUSED */ 475void 476setcr3(ulong_t val) 477{} 478 479void 480reload_cr3(void) 481{} 482 483ulong_t 484getcr4(void) 485{ return (0); } 486 487/* ARGSUSED */ 488void 489setcr4(ulong_t val) 490{} 491 492#if defined(__amd64) 493 494ulong_t 495getcr8(void) 496{ return (0); } 497 498/* ARGSUSED */ 499void 500setcr8(ulong_t val) 501{} 502 503#endif /* __amd64 */ 504 505#else /* __lint */ 506 507#if defined(__amd64) 508 509 ENTRY(getcr0) 510 movq %cr0, %rax 511 ret 512 SET_SIZE(getcr0) 513 514 ENTRY(setcr0) 515 movq %rdi, %cr0 516 ret 517 SET_SIZE(setcr0) 518 519 ENTRY(getcr2) 520 movq %cr2, %rax 521 ret 522 SET_SIZE(getcr2) 523 524 ENTRY(getcr3) 525 movq %cr3, %rax 526 ret 527 SET_SIZE(getcr3) 528 529 ENTRY(setcr3) 530 movq %rdi, %cr3 531 ret 532 SET_SIZE(setcr3) 533 534 ENTRY(reload_cr3) 535 movq %cr3, %rdi 536 movq %rdi, %cr3 537 ret 538 SET_SIZE(reload_cr3) 539 540 ENTRY(getcr4) 541 movq %cr4, %rax 542 ret 543 SET_SIZE(getcr4) 544 545 ENTRY(setcr4) 546 movq %rdi, %cr4 547 ret 548 SET_SIZE(setcr4) 549 550 ENTRY(getcr8) 551 movq %cr8, %rax 552 ret 553 SET_SIZE(getcr8) 554 555 ENTRY(setcr8) 556 movq %rdi, %cr8 557 ret 558 SET_SIZE(setcr8) 559 560#elif defined(__i386) 561 562 ENTRY(getcr0) 563 movl %cr0, %eax 564 ret 565 SET_SIZE(getcr0) 566 567 ENTRY(setcr0) 568 movl 4(%esp), %eax 569 movl %eax, %cr0 570 ret 571 SET_SIZE(setcr0) 572 573 ENTRY(getcr2) 574 movl %cr2, %eax 575 ret 576 SET_SIZE(getcr2) 577 578 ENTRY(getcr3) 579 movl %cr3, %eax 580 ret 581 SET_SIZE(getcr3) 582 583 ENTRY(setcr3) 584 movl 4(%esp), %eax 585 movl %eax, %cr3 586 ret 587 SET_SIZE(setcr3) 588 589 ENTRY(reload_cr3) 590 movl %cr3, %eax 591 movl %eax, %cr3 592 ret 593 SET_SIZE(reload_cr3) 594 595 ENTRY(getcr4) 596 movl %cr4, %eax 597 ret 598 SET_SIZE(getcr4) 599 600 ENTRY(setcr4) 601 movl 4(%esp), %eax 602 movl %eax, %cr4 603 ret 604 SET_SIZE(setcr4) 605 606#endif /* __i386 */ 607#endif /* __lint */ 608 609#if defined(__lint) 610 611/*ARGSUSED*/ 612uint32_t 613__cpuid_insn(uint32_t eax, uint32_t *ebxp, uint32_t *ecxp, uint32_t *edxp) 614{ return (0); } 615 616#else /* __lint */ 617 618#if defined(__amd64) 619 620 ENTRY(__cpuid_insn) 621 movq %rbx, %r11 622 movq %rdx, %r8 /* r8 = ecxp */ 623 movq %rcx, %r9 /* r9 = edxp */ 624 movl %edi, %eax 625 cpuid 626 movl %ebx, (%rsi) 627 movl %ecx, (%r8) 628 movl %edx, (%r9) 629 movq %r11, %rbx 630 ret 631 SET_SIZE(__cpuid_insn) 632 633#elif defined(__i386) 634 635 ENTRY(__cpuid_insn) 636 pushl %ebp 637 movl %esp, %ebp 638 pushl %ebx 639 movl 8(%ebp), %eax 640 cpuid 641 pushl %eax 642 movl 0x0c(%ebp), %eax 643 movl %ebx, (%eax) 644 movl 0x10(%ebp), %eax 645 movl %ecx, (%eax) 646 movl 0x14(%ebp), %eax 647 movl %edx, (%eax) 648 popl %eax 649 popl %ebx 650 popl %ebp 651 ret 652 SET_SIZE(__cpuid_insn) 653 654#endif /* __i386 */ 655#endif /* __lint */ 656 657/* 658 * Insert entryp after predp in a doubly linked list. 659 */ 660 661#if defined(__lint) 662 663/*ARGSUSED*/ 664void 665_insque(caddr_t entryp, caddr_t predp) 666{} 667 668#else /* __lint */ 669 670#if defined(__amd64) 671 672 ENTRY(_insque) 673 movq (%rsi), %rax /* predp->forw */ 674 movq %rsi, CPTRSIZE(%rdi) /* entryp->back = predp */ 675 movq %rax, (%rdi) /* entryp->forw = predp->forw */ 676 movq %rdi, (%rsi) /* predp->forw = entryp */ 677 movq %rdi, CPTRSIZE(%rax) /* predp->forw->back = entryp */ 678 ret 679 SET_SIZE(_insque) 680 681#elif defined(__i386) 682 683 ENTRY(_insque) 684 movl 8(%esp), %edx 685 movl 4(%esp), %ecx 686 movl (%edx), %eax /* predp->forw */ 687 movl %edx, CPTRSIZE(%ecx) /* entryp->back = predp */ 688 movl %eax, (%ecx) /* entryp->forw = predp->forw */ 689 movl %ecx, (%edx) /* predp->forw = entryp */ 690 movl %ecx, CPTRSIZE(%eax) /* predp->forw->back = entryp */ 691 ret 692 SET_SIZE(_insque) 693 694#endif /* __i386 */ 695#endif /* __lint */ 696 697/* 698 * Remove entryp from a doubly linked list 699 */ 700 701#if defined(__lint) 702 703/*ARGSUSED*/ 704void 705_remque(caddr_t entryp) 706{} 707 708#else /* __lint */ 709 710#if defined(__amd64) 711 712 ENTRY(_remque) 713 movq (%rdi), %rax /* entry->forw */ 714 movq CPTRSIZE(%rdi), %rdx /* entry->back */ 715 movq %rax, (%rdx) /* entry->back->forw = entry->forw */ 716 movq %rdx, CPTRSIZE(%rax) /* entry->forw->back = entry->back */ 717 ret 718 SET_SIZE(_remque) 719 720#elif defined(__i386) 721 722 ENTRY(_remque) 723 movl 4(%esp), %ecx 724 movl (%ecx), %eax /* entry->forw */ 725 movl CPTRSIZE(%ecx), %edx /* entry->back */ 726 movl %eax, (%edx) /* entry->back->forw = entry->forw */ 727 movl %edx, CPTRSIZE(%eax) /* entry->forw->back = entry->back */ 728 ret 729 SET_SIZE(_remque) 730 731#endif /* __i386 */ 732#endif /* __lint */ 733 734/* 735 * Returns the number of 736 * non-NULL bytes in string argument. 737 */ 738 739#if defined(__lint) 740 741/* ARGSUSED */ 742size_t 743strlen(const char *str) 744{ return (0); } 745 746#else /* __lint */ 747 748#if defined(__amd64) 749 750/* 751 * This is close to a simple transliteration of a C version of this 752 * routine. We should either just -make- this be a C version, or 753 * justify having it in assembler by making it significantly faster. 754 * 755 * size_t 756 * strlen(const char *s) 757 * { 758 * const char *s0; 759 * #if defined(DEBUG) 760 * if ((uintptr_t)s < KERNELBASE) 761 * panic(.str_panic_msg); 762 * #endif 763 * for (s0 = s; *s; s++) 764 * ; 765 * return (s - s0); 766 * } 767 */ 768 769 ENTRY(strlen) 770#ifdef DEBUG 771 movq kernelbase(%rip), %rax 772 cmpq %rax, %rdi 773 jae str_valid 774 pushq %rbp 775 movq %rsp, %rbp 776 leaq .str_panic_msg(%rip), %rdi 777 xorl %eax, %eax 778 call panic 779#endif /* DEBUG */ 780str_valid: 781 cmpb $0, (%rdi) 782 movq %rdi, %rax 783 je .null_found 784 .align 4 785.strlen_loop: 786 incq %rdi 787 cmpb $0, (%rdi) 788 jne .strlen_loop 789.null_found: 790 subq %rax, %rdi 791 movq %rdi, %rax 792 ret 793 SET_SIZE(strlen) 794 795#elif defined(__i386) 796 797 ENTRY(strlen) 798#ifdef DEBUG 799 movl kernelbase, %eax 800 cmpl %eax, 4(%esp) 801 jae str_valid 802 pushl %ebp 803 movl %esp, %ebp 804 pushl $.str_panic_msg 805 call panic 806#endif /* DEBUG */ 807 808str_valid: 809 movl 4(%esp), %eax /* %eax = string address */ 810 testl $3, %eax /* if %eax not word aligned */ 811 jnz .not_word_aligned /* goto .not_word_aligned */ 812 .align 4 813.word_aligned: 814 movl (%eax), %edx /* move 1 word from (%eax) to %edx */ 815 movl $0x7f7f7f7f, %ecx 816 andl %edx, %ecx /* %ecx = %edx & 0x7f7f7f7f */ 817 addl $4, %eax /* next word */ 818 addl $0x7f7f7f7f, %ecx /* %ecx += 0x7f7f7f7f */ 819 orl %edx, %ecx /* %ecx |= %edx */ 820 andl $0x80808080, %ecx /* %ecx &= 0x80808080 */ 821 cmpl $0x80808080, %ecx /* if no null byte in this word */ 822 je .word_aligned /* goto .word_aligned */ 823 subl $4, %eax /* post-incremented */ 824.not_word_aligned: 825 cmpb $0, (%eax) /* if a byte in (%eax) is null */ 826 je .null_found /* goto .null_found */ 827 incl %eax /* next byte */ 828 testl $3, %eax /* if %eax not word aligned */ 829 jnz .not_word_aligned /* goto .not_word_aligned */ 830 jmp .word_aligned /* goto .word_aligned */ 831 .align 4 832.null_found: 833 subl 4(%esp), %eax /* %eax -= string address */ 834 ret 835 SET_SIZE(strlen) 836 837#endif /* __i386 */ 838 839#ifdef DEBUG 840 .text 841.str_panic_msg: 842 .string "strlen: argument below kernelbase" 843#endif /* DEBUG */ 844 845#endif /* __lint */ 846 847 /* 848 * Berkley 4.3 introduced symbolically named interrupt levels 849 * as a way deal with priority in a machine independent fashion. 850 * Numbered priorities are machine specific, and should be 851 * discouraged where possible. 852 * 853 * Note, for the machine specific priorities there are 854 * examples listed for devices that use a particular priority. 855 * It should not be construed that all devices of that 856 * type should be at that priority. It is currently were 857 * the current devices fit into the priority scheme based 858 * upon time criticalness. 859 * 860 * The underlying assumption of these assignments is that 861 * IPL 10 is the highest level from which a device 862 * routine can call wakeup. Devices that interrupt from higher 863 * levels are restricted in what they can do. If they need 864 * kernels services they should schedule a routine at a lower 865 * level (via software interrupt) to do the required 866 * processing. 867 * 868 * Examples of this higher usage: 869 * Level Usage 870 * 14 Profiling clock (and PROM uart polling clock) 871 * 12 Serial ports 872 * 873 * The serial ports request lower level processing on level 6. 874 * 875 * Also, almost all splN routines (where N is a number or a 876 * mnemonic) will do a RAISE(), on the assumption that they are 877 * never used to lower our priority. 878 * The exceptions are: 879 * spl8() Because you can't be above 15 to begin with! 880 * splzs() Because this is used at boot time to lower our 881 * priority, to allow the PROM to poll the uart. 882 * spl0() Used to lower priority to 0. 883 */ 884 885#if defined(__lint) 886 887int spl0(void) { return (0); } 888int spl6(void) { return (0); } 889int spl7(void) { return (0); } 890int spl8(void) { return (0); } 891int splhigh(void) { return (0); } 892int splhi(void) { return (0); } 893int splzs(void) { return (0); } 894 895#else /* __lint */ 896 897/* reg = cpu->cpu_m.cpu_pri; */ 898#define GETIPL_NOGS(reg, cpup) \ 899 movl CPU_PRI(cpup), reg; 900 901/* cpu->cpu_m.cpu_pri; */ 902#define SETIPL_NOGS(val, cpup) \ 903 movl val, CPU_PRI(cpup); 904 905/* reg = cpu->cpu_m.cpu_pri; */ 906#define GETIPL(reg) \ 907 movl %gs:CPU_PRI, reg; 908 909/* cpu->cpu_m.cpu_pri; */ 910#define SETIPL(val) \ 911 movl val, %gs:CPU_PRI; 912 913/* 914 * Macro to raise processor priority level. 915 * Avoid dropping processor priority if already at high level. 916 * Also avoid going below CPU->cpu_base_spl, which could've just been set by 917 * a higher-level interrupt thread that just blocked. 918 */ 919#if defined(__amd64) 920 921#define RAISE(level) \ 922 cli; \ 923 LOADCPU(%rcx); \ 924 movl $/**/level, %edi;\ 925 GETIPL_NOGS(%eax, %rcx);\ 926 cmpl %eax, %edi; \ 927 jg spl; \ 928 jmp setsplhisti 929 930#elif defined(__i386) 931 932#define RAISE(level) \ 933 cli; \ 934 LOADCPU(%ecx); \ 935 movl $/**/level, %edx;\ 936 GETIPL_NOGS(%eax, %ecx);\ 937 cmpl %eax, %edx; \ 938 jg spl; \ 939 jmp setsplhisti 940 941#endif /* __i386 */ 942 943/* 944 * Macro to set the priority to a specified level. 945 * Avoid dropping the priority below CPU->cpu_base_spl. 946 */ 947#if defined(__amd64) 948 949#define SETPRI(level) \ 950 cli; \ 951 LOADCPU(%rcx); \ 952 movl $/**/level, %edi; \ 953 jmp spl 954 955#elif defined(__i386) 956 957#define SETPRI(level) \ 958 cli; \ 959 LOADCPU(%ecx); \ 960 movl $/**/level, %edx; \ 961 jmp spl 962 963#endif /* __i386 */ 964 965 /* locks out all interrupts, including memory errors */ 966 ENTRY(spl8) 967 SETPRI(15) 968 SET_SIZE(spl8) 969 970 /* just below the level that profiling runs */ 971 ENTRY(spl7) 972 RAISE(13) 973 SET_SIZE(spl7) 974 975 /* sun specific - highest priority onboard serial i/o asy ports */ 976 ENTRY(splzs) 977 SETPRI(12) /* Can't be a RAISE, as it's used to lower us */ 978 SET_SIZE(splzs) 979 980 /* 981 * should lock out clocks and all interrupts, 982 * as you can see, there are exceptions 983 */ 984 985#if defined(__amd64) 986 987 .align 16 988 ENTRY(splhi) 989 ALTENTRY(splhigh) 990 ALTENTRY(spl6) 991 ALTENTRY(i_ddi_splhigh) 992 cli 993 LOADCPU(%rcx) 994 movl $DISP_LEVEL, %edi 995 movl CPU_PRI(%rcx), %eax 996 cmpl %eax, %edi 997 jle setsplhisti 998 SETIPL_NOGS(%edi, %rcx) 999 /* 1000 * If we aren't using cr8 to control ipl then we patch this 1001 * with a jump to slow_setsplhi 1002 */ 1003 ALTENTRY(setsplhi_patch) 1004 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1005 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1006 movq %rdx, %cr8 /* set new apic priority */ 1007 /* 1008 * enable interrupts 1009 */ 1010setsplhisti: 1011 nop /* patch this to a sti when a proper setspl routine appears */ 1012 ret 1013 1014 ALTENTRY(slow_setsplhi) 1015 pushq %rbp 1016 movq %rsp, %rbp 1017 subq $16, %rsp 1018 movl %eax, -4(%rbp) /* save old ipl */ 1019 call *setspl(%rip) 1020 movl -4(%rbp), %eax /* return old ipl */ 1021 leave 1022 jmp setsplhisti 1023 1024 SET_SIZE(i_ddi_splhigh) 1025 SET_SIZE(spl6) 1026 SET_SIZE(splhigh) 1027 SET_SIZE(splhi) 1028 1029#elif defined(__i386) 1030 1031 .align 16 1032 ENTRY(splhi) 1033 ALTENTRY(splhigh) 1034 ALTENTRY(spl6) 1035 ALTENTRY(i_ddi_splhigh) 1036 cli 1037 LOADCPU(%ecx) 1038 movl $DISP_LEVEL, %edx 1039 movl CPU_PRI(%ecx), %eax 1040 cmpl %eax, %edx 1041 jle setsplhisti 1042 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1043 1044 pushl %eax /* save old ipl */ 1045 pushl %edx /* pass new ipl */ 1046 call *setspl 1047 popl %ecx /* dummy pop */ 1048 popl %eax /* return old ipl */ 1049 /* 1050 * enable interrupts 1051 * 1052 * (we patch this to an sti once a proper setspl routine 1053 * is installed) 1054 */ 1055setsplhisti: 1056 nop /* patch this to a sti when a proper setspl routine appears */ 1057 ret 1058 SET_SIZE(i_ddi_splhigh) 1059 SET_SIZE(spl6) 1060 SET_SIZE(splhigh) 1061 SET_SIZE(splhi) 1062 1063#endif /* __i386 */ 1064 1065 /* allow all interrupts */ 1066 ENTRY(spl0) 1067 SETPRI(0) 1068 SET_SIZE(spl0) 1069 1070#endif /* __lint */ 1071 1072/* 1073 * splr is like splx but will only raise the priority and never drop it 1074 */ 1075#if defined(__lint) 1076 1077/* ARGSUSED */ 1078int 1079splr(int level) 1080{ return (0); } 1081 1082#else /* __lint */ 1083 1084#if defined(__amd64) 1085 1086 ENTRY(splr) 1087 cli 1088 LOADCPU(%rcx) 1089 GETIPL_NOGS(%eax, %rcx) 1090 cmpl %eax, %edi /* if new level > current level */ 1091 jg spl /* then set ipl to new level */ 1092splr_setsti: 1093 nop /* patch this to a sti when a proper setspl routine appears */ 1094 ret /* else return the current level */ 1095 SET_SIZE(splr) 1096 1097#elif defined(__i386) 1098 1099 ENTRY(splr) 1100 cli 1101 LOADCPU(%ecx) 1102 movl 4(%esp), %edx /* get new spl level */ 1103 GETIPL_NOGS(%eax, %ecx) 1104 cmpl %eax, %edx /* if new level > current level */ 1105 jg spl /* then set ipl to new level */ 1106splr_setsti: 1107 nop /* patch this to a sti when a proper setspl routine appears */ 1108 ret /* else return the current level */ 1109 SET_SIZE(splr) 1110 1111#endif /* __i386 */ 1112#endif /* __lint */ 1113 1114 1115 1116/* 1117 * splx - set PIL back to that indicated by the level passed as an argument, 1118 * or to the CPU's base priority, whichever is higher. 1119 * Needs to be fall through to spl to save cycles. 1120 * Algorithm for spl: 1121 * 1122 * turn off interrupts 1123 * 1124 * if (CPU->cpu_base_spl > newipl) 1125 * newipl = CPU->cpu_base_spl; 1126 * oldipl = CPU->cpu_pridata->c_ipl; 1127 * CPU->cpu_pridata->c_ipl = newipl; 1128 * 1129 * /indirectly call function to set spl values (usually setpicmasks) 1130 * setspl(); // load new masks into pics 1131 * 1132 * Be careful not to set priority lower than CPU->cpu_base_pri, 1133 * even though it seems we're raising the priority, it could be set 1134 * higher at any time by an interrupt routine, so we must block interrupts 1135 * and look at CPU->cpu_base_pri 1136 */ 1137#if defined(__lint) 1138 1139/* ARGSUSED */ 1140void 1141splx(int level) 1142{} 1143 1144#else /* __lint */ 1145 1146#if defined(__amd64) 1147 1148 ENTRY(splx) 1149 ALTENTRY(i_ddi_splx) 1150 cli /* disable interrupts */ 1151 LOADCPU(%rcx) 1152 /*FALLTHRU*/ 1153 .align 4 1154spl: 1155 /* 1156 * New priority level is in %edi, cpu struct pointer is in %rcx 1157 */ 1158 GETIPL_NOGS(%eax, %rcx) /* get current ipl */ 1159 cmpl %edi, CPU_BASE_SPL(%rcx) /* if (base spl > new ipl) */ 1160 ja set_to_base_spl /* then use base_spl */ 1161 1162setprilev: 1163 SETIPL_NOGS(%edi, %rcx) /* set new ipl */ 1164 /* 1165 * If we aren't using cr8 to control ipl then we patch this 1166 * with a jump to slow_spl 1167 */ 1168 ALTENTRY(spl_patch) 1169 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1170 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1171 movq %rdx, %cr8 /* set new apic priority */ 1172 xorl %edx, %edx 1173 bsrl CPU_SOFTINFO(%rcx), %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1174 cmpl %edi, %edx /* new ipl vs. st_pending */ 1175 jle setsplsti 1176 1177 pushq %rbp 1178 movq %rsp, %rbp 1179 /* stack now 16-byte aligned */ 1180 pushq %rax /* save old spl */ 1181 pushq %rdi /* save new ipl too */ 1182 jmp fakesoftint 1183 1184setsplsti: 1185 nop /* patch this to a sti when a proper setspl routine appears */ 1186 ret 1187 1188 ALTENTRY(slow_spl) 1189 pushq %rbp 1190 movq %rsp, %rbp 1191 /* stack now 16-byte aligned */ 1192 1193 pushq %rax /* save old spl */ 1194 pushq %rdi /* save new ipl too */ 1195 1196 call *setspl(%rip) 1197 1198 LOADCPU(%rcx) 1199 movl CPU_SOFTINFO(%rcx), %eax 1200 orl %eax, %eax 1201 jz slow_setsplsti 1202 1203 bsrl %eax, %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1204 cmpl 0(%rsp), %edx /* new ipl vs. st_pending */ 1205 jg fakesoftint 1206 1207 ALTENTRY(fakesoftint_return) 1208 /* 1209 * enable interrupts 1210 */ 1211slow_setsplsti: 1212 nop /* patch this to a sti when a proper setspl routine appears */ 1213 popq %rdi 1214 popq %rax /* return old ipl */ 1215 leave 1216 ret 1217 SET_SIZE(fakesoftint_return) 1218 1219set_to_base_spl: 1220 movl CPU_BASE_SPL(%rcx), %edi 1221 jmp setprilev 1222 SET_SIZE(spl) 1223 SET_SIZE(i_ddi_splx) 1224 SET_SIZE(splx) 1225 1226#elif defined(__i386) 1227 1228 ENTRY(splx) 1229 ALTENTRY(i_ddi_splx) 1230 cli /* disable interrupts */ 1231 LOADCPU(%ecx) 1232 movl 4(%esp), %edx /* get new spl level */ 1233 /*FALLTHRU*/ 1234 1235 .align 4 1236 ALTENTRY(spl) 1237 /* 1238 * New priority level is in %edx 1239 * (doing this early to avoid an AGI in the next instruction) 1240 */ 1241 GETIPL_NOGS(%eax, %ecx) /* get current ipl */ 1242 cmpl %edx, CPU_BASE_SPL(%ecx) /* if ( base spl > new ipl) */ 1243 ja set_to_base_spl /* then use base_spl */ 1244 1245setprilev: 1246 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1247 1248 pushl %eax /* save old ipl */ 1249 pushl %edx /* pass new ipl */ 1250 call *setspl 1251 1252 LOADCPU(%ecx) 1253 movl CPU_SOFTINFO(%ecx), %eax 1254 orl %eax, %eax 1255 jz setsplsti 1256 1257 /* 1258 * Before dashing off, check that setsplsti has been patched. 1259 */ 1260 cmpl $NOP_INSTR, setsplsti 1261 je setsplsti 1262 1263 bsrl %eax, %edx 1264 cmpl 0(%esp), %edx 1265 jg fakesoftint 1266 1267 ALTENTRY(fakesoftint_return) 1268 /* 1269 * enable interrupts 1270 */ 1271setsplsti: 1272 nop /* patch this to a sti when a proper setspl routine appears */ 1273 popl %eax 1274 popl %eax / return old ipl 1275 ret 1276 SET_SIZE(fakesoftint_return) 1277 1278set_to_base_spl: 1279 movl CPU_BASE_SPL(%ecx), %edx 1280 jmp setprilev 1281 SET_SIZE(spl) 1282 SET_SIZE(i_ddi_splx) 1283 SET_SIZE(splx) 1284 1285#endif /* __i386 */ 1286#endif /* __lint */ 1287 1288#if defined(__lint) 1289 1290void 1291install_spl(void) 1292{} 1293 1294#else /* __lint */ 1295 1296#if defined(__amd64) 1297 1298 ENTRY_NP(install_spl) 1299 movq %cr0, %rax 1300 movq %rax, %rdx 1301 movl $_BITNOT(CR0_WP), %ecx 1302 movslq %ecx, %rcx 1303 andq %rcx, %rax /* we don't want to take a fault */ 1304 movq %rax, %cr0 1305 jmp 1f 13061: movb $STI_INSTR, setsplsti(%rip) 1307 movb $STI_INSTR, slow_setsplsti(%rip) 1308 movb $STI_INSTR, setsplhisti(%rip) 1309 movb $STI_INSTR, splr_setsti(%rip) 1310 testl $1, intpri_use_cr8(%rip) /* are using %cr8 ? */ 1311 jz 2f /* no, go patch more */ 1312 movq %rdx, %cr0 1313 ret 13142: 1315 /* 1316 * Patch spl functions to use slow spl method 1317 */ 1318 leaq setsplhi_patch(%rip), %rdi /* get patch point addr */ 1319 leaq slow_setsplhi(%rip), %rax /* jmp target */ 1320 subq %rdi, %rax /* calculate jmp distance */ 1321 subq $2, %rax /* minus size of jmp instr */ 1322 shlq $8, %rax /* construct jmp instr */ 1323 addq $JMP_INSTR, %rax 1324 movw %ax, setsplhi_patch(%rip) /* patch in the jmp */ 1325 leaq spl_patch(%rip), %rdi /* get patch point addr */ 1326 leaq slow_spl(%rip), %rax /* jmp target */ 1327 subq %rdi, %rax /* calculate jmp distance */ 1328 subq $2, %rax /* minus size of jmp instr */ 1329 shlq $8, %rax /* construct jmp instr */ 1330 addq $JMP_INSTR, %rax 1331 movw %ax, spl_patch(%rip) /* patch in the jmp */ 1332 /* 1333 * Ensure %cr8 is zero since we aren't using it 1334 */ 1335 xorl %eax, %eax 1336 movq %rax, %cr8 1337 movq %rdx, %cr0 1338 ret 1339 SET_SIZE(install_spl) 1340 1341#elif defined(__i386) 1342 1343 ENTRY_NP(install_spl) 1344 movl %cr0, %eax 1345 movl %eax, %edx 1346 andl $_BITNOT(CR0_WP), %eax /* we don't want to take a fault */ 1347 movl %eax, %cr0 1348 jmp 1f 13491: movb $STI_INSTR, setsplsti 1350 movb $STI_INSTR, setsplhisti 1351 movb $STI_INSTR, splr_setsti 1352 movl %edx, %cr0 1353 ret 1354 SET_SIZE(install_spl) 1355 1356#endif /* __i386 */ 1357#endif /* __lint */ 1358 1359 1360/* 1361 * Get current processor interrupt level 1362 */ 1363 1364#if defined(__lint) 1365 1366int 1367getpil(void) 1368{ return (0); } 1369 1370#else /* __lint */ 1371 1372#if defined(__amd64) 1373 1374 ENTRY(getpil) 1375 GETIPL(%eax) /* priority level into %eax */ 1376 ret 1377 SET_SIZE(getpil) 1378 1379#elif defined(__i386) 1380 1381 ENTRY(getpil) 1382 GETIPL(%eax) /* priority level into %eax */ 1383 ret 1384 SET_SIZE(getpil) 1385 1386#endif /* __i386 */ 1387#endif /* __lint */ 1388 1389#if defined(__i386) 1390 1391/* 1392 * Read and write the %gs register 1393 */ 1394 1395#if defined(__lint) 1396 1397/*ARGSUSED*/ 1398uint16_t 1399getgs(void) 1400{ return (0); } 1401 1402/*ARGSUSED*/ 1403void 1404setgs(uint16_t sel) 1405{} 1406 1407#else /* __lint */ 1408 1409 ENTRY(getgs) 1410 clr %eax 1411 movw %gs, %ax 1412 ret 1413 SET_SIZE(getgs) 1414 1415 ENTRY(setgs) 1416 movw 4(%esp), %gs 1417 ret 1418 SET_SIZE(setgs) 1419 1420#endif /* __lint */ 1421#endif /* __i386 */ 1422 1423#if defined(__lint) 1424 1425void 1426pc_reset(void) 1427{} 1428 1429#else /* __lint */ 1430 1431 ENTRY(pc_reset) 1432 / Try the PCI (soft) reset vector (should work on all modern systems) 1433 / When resetting via this method, 2 writes are required. The first 1434 / targets bit 1 (0=hard reset without power cycle, 1=hard reset with power 1435 / cycle). 1436 / The reset occurs on the second write, during bit 2's transition from 0->1. 1437 movw $0xcf9, %dx 1438 movb $0x2, %al / Reset mode = hard, no power cycle 1439 outb (%dx) 1440 movb $0x6, %al 1441 outb (%dx) 1442 1443 / 1444 / Try the classic keyboard controller-triggered reset. 1445 / 1446 movw $0x64, %dx 1447 movb $0xfe, %al 1448 outb (%dx) 1449 1450 / 1451 / Try port 0x92 fast reset 1452 / 1453 movw $0x92, %dx 1454 inb (%dx) 1455 cmpb $0xff, %al / If port's not there, we should get back 0xFF 1456 je 1f 1457 testb $1, %al / If bit 0 1458 jz 2f / is clear, jump to perform the reset 1459 andb $0xfe, %al / otherwise, 1460 outb (%dx) / clear bit 0 first, then 14612: 1462 orb $1, %al / Set bit 0 1463 outb (%dx) / and reset the system 14641: 1465 / 1466 / port 0x92 failed also. Last-ditch effort is to 1467 / triple-fault the CPU. 1468 / 1469#if defined(__amd64) 1470 pushq $0x0 1471 pushq $0x0 / IDT base of 0, limit of 0 + 2 unused bytes 1472 lidt (%rsp) 1473#elif defined(__i386) 1474 pushl $0x0 1475 pushl $0x0 / IDT base of 0, limit of 0 + 2 unused bytes 1476 lidt (%esp) 1477#endif 1478 int $0x0 / Trigger interrupt, generate triple-fault 1479 hlt 1480 /*NOTREACHED*/ 1481 SET_SIZE(pc_reset) 1482 1483#endif /* __lint */ 1484 1485/* 1486 * C callable in and out routines 1487 */ 1488 1489#if defined(__lint) 1490 1491/* ARGSUSED */ 1492void 1493outl(int port_address, uint32_t val) 1494{} 1495 1496#else /* __lint */ 1497 1498#if defined(__amd64) 1499 1500 ENTRY(outl) 1501 movw %di, %dx 1502 movl %esi, %eax 1503 outl (%dx) 1504 ret 1505 SET_SIZE(outl) 1506 1507#elif defined(__i386) 1508 1509 .set PORT, 4 1510 .set VAL, 8 1511 1512 ENTRY(outl) 1513 movw PORT(%esp), %dx 1514 movl VAL(%esp), %eax 1515 outl (%dx) 1516 ret 1517 SET_SIZE(outl) 1518 1519#endif /* __i386 */ 1520#endif /* __lint */ 1521 1522#if defined(__lint) 1523 1524/* ARGSUSED */ 1525void 1526outw(int port_address, uint16_t val) 1527{} 1528 1529#else /* __lint */ 1530 1531#if defined(__amd64) 1532 1533 ENTRY(outw) 1534 movw %di, %dx 1535 movw %si, %ax 1536 D16 outl (%dx) /* XX64 why not outw? */ 1537 ret 1538 SET_SIZE(outw) 1539 1540#elif defined(__i386) 1541 1542 ENTRY(outw) 1543 movw PORT(%esp), %dx 1544 movw VAL(%esp), %ax 1545 D16 outl (%dx) 1546 ret 1547 SET_SIZE(outw) 1548 1549#endif /* __i386 */ 1550#endif /* __lint */ 1551 1552#if defined(__lint) 1553 1554/* ARGSUSED */ 1555void 1556outb(int port_address, uint8_t val) 1557{} 1558 1559#else /* __lint */ 1560 1561#if defined(__amd64) 1562 1563 ENTRY(outb) 1564 movw %di, %dx 1565 movb %sil, %al 1566 outb (%dx) 1567 ret 1568 SET_SIZE(outb) 1569 1570#elif defined(__i386) 1571 1572 ENTRY(outb) 1573 movw PORT(%esp), %dx 1574 movb VAL(%esp), %al 1575 outb (%dx) 1576 ret 1577 SET_SIZE(outb) 1578 1579#endif /* __i386 */ 1580#endif /* __lint */ 1581 1582#if defined(__lint) 1583 1584/* ARGSUSED */ 1585uint32_t 1586inl(int port_address) 1587{ return (0); } 1588 1589#else /* __lint */ 1590 1591#if defined(__amd64) 1592 1593 ENTRY(inl) 1594 xorl %eax, %eax 1595 movw %di, %dx 1596 inl (%dx) 1597 ret 1598 SET_SIZE(inl) 1599 1600#elif defined(__i386) 1601 1602 ENTRY(inl) 1603 movw PORT(%esp), %dx 1604 inl (%dx) 1605 ret 1606 SET_SIZE(inl) 1607 1608#endif /* __i386 */ 1609#endif /* __lint */ 1610 1611#if defined(__lint) 1612 1613/* ARGSUSED */ 1614uint16_t 1615inw(int port_address) 1616{ return (0); } 1617 1618#else /* __lint */ 1619 1620#if defined(__amd64) 1621 1622 ENTRY(inw) 1623 xorl %eax, %eax 1624 movw %di, %dx 1625 D16 inl (%dx) 1626 ret 1627 SET_SIZE(inw) 1628 1629#elif defined(__i386) 1630 1631 ENTRY(inw) 1632 subl %eax, %eax 1633 movw PORT(%esp), %dx 1634 D16 inl (%dx) 1635 ret 1636 SET_SIZE(inw) 1637 1638#endif /* __i386 */ 1639#endif /* __lint */ 1640 1641 1642#if defined(__lint) 1643 1644/* ARGSUSED */ 1645uint8_t 1646inb(int port_address) 1647{ return (0); } 1648 1649#else /* __lint */ 1650 1651#if defined(__amd64) 1652 1653 ENTRY(inb) 1654 xorl %eax, %eax 1655 movw %di, %dx 1656 inb (%dx) 1657 ret 1658 SET_SIZE(inb) 1659 1660#elif defined(__i386) 1661 1662 ENTRY(inb) 1663 subl %eax, %eax 1664 movw PORT(%esp), %dx 1665 inb (%dx) 1666 ret 1667 SET_SIZE(inb) 1668 1669#endif /* __i386 */ 1670#endif /* __lint */ 1671 1672 1673#if defined(__lint) 1674 1675/* ARGSUSED */ 1676void 1677repoutsw(int port, uint16_t *addr, int cnt) 1678{} 1679 1680#else /* __lint */ 1681 1682#if defined(__amd64) 1683 1684 ENTRY(repoutsw) 1685 movl %edx, %ecx 1686 movw %di, %dx 1687 rep 1688 D16 outsl 1689 ret 1690 SET_SIZE(repoutsw) 1691 1692#elif defined(__i386) 1693 1694 /* 1695 * The arguments and saved registers are on the stack in the 1696 * following order: 1697 * | cnt | +16 1698 * | *addr | +12 1699 * | port | +8 1700 * | eip | +4 1701 * | esi | <-- %esp 1702 * If additional values are pushed onto the stack, make sure 1703 * to adjust the following constants accordingly. 1704 */ 1705 .set PORT, 8 1706 .set ADDR, 12 1707 .set COUNT, 16 1708 1709 ENTRY(repoutsw) 1710 pushl %esi 1711 movl PORT(%esp), %edx 1712 movl ADDR(%esp), %esi 1713 movl COUNT(%esp), %ecx 1714 rep 1715 D16 outsl 1716 popl %esi 1717 ret 1718 SET_SIZE(repoutsw) 1719 1720#endif /* __i386 */ 1721#endif /* __lint */ 1722 1723 1724#if defined(__lint) 1725 1726/* ARGSUSED */ 1727void 1728repinsw(int port_addr, uint16_t *addr, int cnt) 1729{} 1730 1731#else /* __lint */ 1732 1733#if defined(__amd64) 1734 1735 ENTRY(repinsw) 1736 movl %edx, %ecx 1737 movw %di, %dx 1738 rep 1739 D16 insl 1740 ret 1741 SET_SIZE(repinsw) 1742 1743#elif defined(__i386) 1744 1745 ENTRY(repinsw) 1746 pushl %edi 1747 movl PORT(%esp), %edx 1748 movl ADDR(%esp), %edi 1749 movl COUNT(%esp), %ecx 1750 rep 1751 D16 insl 1752 popl %edi 1753 ret 1754 SET_SIZE(repinsw) 1755 1756#endif /* __i386 */ 1757#endif /* __lint */ 1758 1759 1760#if defined(__lint) 1761 1762/* ARGSUSED */ 1763void 1764repinsb(int port, uint8_t *addr, int count) 1765{} 1766 1767#else /* __lint */ 1768 1769#if defined(__amd64) 1770 1771 ENTRY(repinsb) 1772 movl %edx, %ecx 1773 movw %di, %dx 1774 movq %rsi, %rdi 1775 rep 1776 insb 1777 ret 1778 SET_SIZE(repinsb) 1779 1780#elif defined(__i386) 1781 1782 /* 1783 * The arguments and saved registers are on the stack in the 1784 * following order: 1785 * | cnt | +16 1786 * | *addr | +12 1787 * | port | +8 1788 * | eip | +4 1789 * | esi | <-- %esp 1790 * If additional values are pushed onto the stack, make sure 1791 * to adjust the following constants accordingly. 1792 */ 1793 .set IO_PORT, 8 1794 .set IO_ADDR, 12 1795 .set IO_COUNT, 16 1796 1797 ENTRY(repinsb) 1798 pushl %edi 1799 movl IO_ADDR(%esp), %edi 1800 movl IO_COUNT(%esp), %ecx 1801 movl IO_PORT(%esp), %edx 1802 rep 1803 insb 1804 popl %edi 1805 ret 1806 SET_SIZE(repinsb) 1807 1808#endif /* __i386 */ 1809#endif /* __lint */ 1810 1811 1812/* 1813 * Input a stream of 32-bit words. 1814 * NOTE: count is a DWORD count. 1815 */ 1816#if defined(__lint) 1817 1818/* ARGSUSED */ 1819void 1820repinsd(int port, uint32_t *addr, int count) 1821{} 1822 1823#else /* __lint */ 1824 1825#if defined(__amd64) 1826 1827 ENTRY(repinsd) 1828 movl %edx, %ecx 1829 movw %di, %dx 1830 movq %rsi, %rdi 1831 rep 1832 insl 1833 ret 1834 SET_SIZE(repinsd) 1835 1836#elif defined(__i386) 1837 1838 ENTRY(repinsd) 1839 pushl %edi 1840 movl IO_ADDR(%esp), %edi 1841 movl IO_COUNT(%esp), %ecx 1842 movl IO_PORT(%esp), %edx 1843 rep 1844 insl 1845 popl %edi 1846 ret 1847 SET_SIZE(repinsd) 1848 1849#endif /* __i386 */ 1850#endif /* __lint */ 1851 1852/* 1853 * Output a stream of bytes 1854 * NOTE: count is a byte count 1855 */ 1856#if defined(__lint) 1857 1858/* ARGSUSED */ 1859void 1860repoutsb(int port, uint8_t *addr, int count) 1861{} 1862 1863#else /* __lint */ 1864 1865#if defined(__amd64) 1866 1867 ENTRY(repoutsb) 1868 movl %edx, %ecx 1869 movw %di, %dx 1870 rep 1871 outsb 1872 ret 1873 SET_SIZE(repoutsb) 1874 1875#elif defined(__i386) 1876 1877 ENTRY(repoutsb) 1878 pushl %esi 1879 movl IO_ADDR(%esp), %esi 1880 movl IO_COUNT(%esp), %ecx 1881 movl IO_PORT(%esp), %edx 1882 rep 1883 outsb 1884 popl %esi 1885 ret 1886 SET_SIZE(repoutsb) 1887 1888#endif /* __i386 */ 1889#endif /* __lint */ 1890 1891/* 1892 * Output a stream of 32-bit words 1893 * NOTE: count is a DWORD count 1894 */ 1895#if defined(__lint) 1896 1897/* ARGSUSED */ 1898void 1899repoutsd(int port, uint32_t *addr, int count) 1900{} 1901 1902#else /* __lint */ 1903 1904#if defined(__amd64) 1905 1906 ENTRY(repoutsd) 1907 movl %edx, %ecx 1908 movw %di, %dx 1909 rep 1910 outsl 1911 ret 1912 SET_SIZE(repoutsd) 1913 1914#elif defined(__i386) 1915 1916 ENTRY(repoutsd) 1917 pushl %esi 1918 movl IO_ADDR(%esp), %esi 1919 movl IO_COUNT(%esp), %ecx 1920 movl IO_PORT(%esp), %edx 1921 rep 1922 outsl 1923 popl %esi 1924 ret 1925 SET_SIZE(repoutsd) 1926 1927#endif /* __i386 */ 1928#endif /* __lint */ 1929 1930/* 1931 * void int20(void) 1932 */ 1933 1934#if defined(__lint) 1935 1936void 1937int20(void) 1938{} 1939 1940#else /* __lint */ 1941 1942 ENTRY(int20) 1943 movl boothowto, %eax 1944 andl $RB_DEBUG, %eax 1945 jz 1f 1946 1947 int $20 19481: 1949 rep; ret /* use 2 byte return instruction when branch target */ 1950 /* AMD Software Optimization Guide - Section 6.2 */ 1951 SET_SIZE(int20) 1952 1953#endif /* __lint */ 1954 1955#if defined(__lint) 1956 1957/* ARGSUSED */ 1958int 1959scanc(size_t size, uchar_t *cp, uchar_t *table, uchar_t mask) 1960{ return (0); } 1961 1962#else /* __lint */ 1963 1964#if defined(__amd64) 1965 1966 ENTRY(scanc) 1967 /* rdi == size */ 1968 /* rsi == cp */ 1969 /* rdx == table */ 1970 /* rcx == mask */ 1971 addq %rsi, %rdi /* end = &cp[size] */ 1972.scanloop: 1973 cmpq %rdi, %rsi /* while (cp < end */ 1974 jnb .scandone 1975 movzbq (%rsi), %r8 /* %r8 = *cp */ 1976 incq %rsi /* cp++ */ 1977 testb %cl, (%r8, %rdx) 1978 jz .scanloop /* && (table[*cp] & mask) == 0) */ 1979 decq %rsi /* (fix post-increment) */ 1980.scandone: 1981 movl %edi, %eax 1982 subl %esi, %eax /* return (end - cp) */ 1983 ret 1984 SET_SIZE(scanc) 1985 1986#elif defined(__i386) 1987 1988 ENTRY(scanc) 1989 pushl %edi 1990 pushl %esi 1991 movb 24(%esp), %cl /* mask = %cl */ 1992 movl 16(%esp), %esi /* cp = %esi */ 1993 movl 20(%esp), %edx /* table = %edx */ 1994 movl %esi, %edi 1995 addl 12(%esp), %edi /* end = &cp[size]; */ 1996.scanloop: 1997 cmpl %edi, %esi /* while (cp < end */ 1998 jnb .scandone 1999 movzbl (%esi), %eax /* %al = *cp */ 2000 incl %esi /* cp++ */ 2001 movb (%edx, %eax), %al /* %al = table[*cp] */ 2002 testb %al, %cl 2003 jz .scanloop /* && (table[*cp] & mask) == 0) */ 2004 dec %esi /* post-incremented */ 2005.scandone: 2006 movl %edi, %eax 2007 subl %esi, %eax /* return (end - cp) */ 2008 popl %esi 2009 popl %edi 2010 ret 2011 SET_SIZE(scanc) 2012 2013#endif /* __i386 */ 2014#endif /* __lint */ 2015 2016/* 2017 * Replacement functions for ones that are normally inlined. 2018 * In addition to the copy in i86.il, they are defined here just in case. 2019 */ 2020 2021#if defined(__lint) 2022 2023int 2024intr_clear(void) 2025{ return 0; } 2026 2027int 2028clear_int_flag(void) 2029{ return 0; } 2030 2031#else /* __lint */ 2032 2033#if defined(__amd64) 2034 2035 ENTRY(intr_clear) 2036 ENTRY(clear_int_flag) 2037 pushfq 2038 cli 2039 popq %rax 2040 ret 2041 SET_SIZE(clear_int_flag) 2042 SET_SIZE(intr_clear) 2043 2044#elif defined(__i386) 2045 2046 ENTRY(intr_clear) 2047 ENTRY(clear_int_flag) 2048 pushfl 2049 cli 2050 popl %eax 2051 ret 2052 SET_SIZE(clear_int_flag) 2053 SET_SIZE(intr_clear) 2054 2055#endif /* __i386 */ 2056#endif /* __lint */ 2057 2058#if defined(__lint) 2059 2060struct cpu * 2061curcpup(void) 2062{ return 0; } 2063 2064#else /* __lint */ 2065 2066#if defined(__amd64) 2067 2068 ENTRY(curcpup) 2069 movq %gs:CPU_SELF, %rax 2070 ret 2071 SET_SIZE(curcpup) 2072 2073#elif defined(__i386) 2074 2075 ENTRY(curcpup) 2076 movl %gs:CPU_SELF, %eax 2077 ret 2078 SET_SIZE(curcpup) 2079 2080#endif /* __i386 */ 2081#endif /* __lint */ 2082 2083#if defined(__lint) 2084 2085/* ARGSUSED */ 2086uint32_t 2087htonl(uint32_t i) 2088{ return (0); } 2089 2090/* ARGSUSED */ 2091uint32_t 2092ntohl(uint32_t i) 2093{ return (0); } 2094 2095#else /* __lint */ 2096 2097#if defined(__amd64) 2098 2099 /* XX64 there must be shorter sequences for this */ 2100 ENTRY(htonl) 2101 ALTENTRY(ntohl) 2102 movl %edi, %eax 2103 bswap %eax 2104 ret 2105 SET_SIZE(ntohl) 2106 SET_SIZE(htonl) 2107 2108#elif defined(__i386) 2109 2110 ENTRY(htonl) 2111 ALTENTRY(ntohl) 2112 movl 4(%esp), %eax 2113 bswap %eax 2114 ret 2115 SET_SIZE(ntohl) 2116 SET_SIZE(htonl) 2117 2118#endif /* __i386 */ 2119#endif /* __lint */ 2120 2121#if defined(__lint) 2122 2123/* ARGSUSED */ 2124uint16_t 2125htons(uint16_t i) 2126{ return (0); } 2127 2128/* ARGSUSED */ 2129uint16_t 2130ntohs(uint16_t i) 2131{ return (0); } 2132 2133 2134#else /* __lint */ 2135 2136#if defined(__amd64) 2137 2138 /* XX64 there must be better sequences for this */ 2139 ENTRY(htons) 2140 ALTENTRY(ntohs) 2141 movl %edi, %eax 2142 bswap %eax 2143 shrl $16, %eax 2144 ret 2145 SET_SIZE(ntohs) 2146 SET_SIZE(htons) 2147 2148#elif defined(__i386) 2149 2150 ENTRY(htons) 2151 ALTENTRY(ntohs) 2152 movl 4(%esp), %eax 2153 bswap %eax 2154 shrl $16, %eax 2155 ret 2156 SET_SIZE(ntohs) 2157 SET_SIZE(htons) 2158 2159#endif /* __i386 */ 2160#endif /* __lint */ 2161 2162 2163#if defined(__lint) 2164 2165/* ARGSUSED */ 2166void 2167intr_restore(uint_t i) 2168{ return; } 2169 2170/* ARGSUSED */ 2171void 2172restore_int_flag(int i) 2173{ return; } 2174 2175#else /* __lint */ 2176 2177#if defined(__amd64) 2178 2179 ENTRY(intr_restore) 2180 ENTRY(restore_int_flag) 2181 pushq %rdi 2182 popfq 2183 ret 2184 SET_SIZE(restore_int_flag) 2185 SET_SIZE(intr_restore) 2186 2187#elif defined(__i386) 2188 2189 ENTRY(intr_restore) 2190 ENTRY(restore_int_flag) 2191 pushl 4(%esp) 2192 popfl 2193 ret 2194 SET_SIZE(restore_int_flag) 2195 SET_SIZE(intr_restore) 2196 2197#endif /* __i386 */ 2198#endif /* __lint */ 2199 2200#if defined(__lint) 2201 2202void 2203sti(void) 2204{} 2205 2206#else /* __lint */ 2207 2208 ENTRY(sti) 2209 sti 2210 ret 2211 SET_SIZE(sti) 2212 2213#endif /* __lint */ 2214 2215#if defined(__lint) 2216 2217dtrace_icookie_t 2218dtrace_interrupt_disable(void) 2219{ return (0); } 2220 2221#else /* __lint */ 2222 2223#if defined(__amd64) 2224 2225 ENTRY(dtrace_interrupt_disable) 2226 pushfq 2227 popq %rax 2228 cli 2229 ret 2230 SET_SIZE(dtrace_interrupt_disable) 2231 2232#elif defined(__i386) 2233 2234 ENTRY(dtrace_interrupt_disable) 2235 pushfl 2236 popl %eax 2237 cli 2238 ret 2239 SET_SIZE(dtrace_interrupt_disable) 2240 2241#endif /* __i386 */ 2242#endif /* __lint */ 2243 2244#if defined(__lint) 2245 2246/*ARGSUSED*/ 2247void 2248dtrace_interrupt_enable(dtrace_icookie_t cookie) 2249{} 2250 2251#else /* __lint */ 2252 2253#if defined(__amd64) 2254 2255 ENTRY(dtrace_interrupt_enable) 2256 pushq %rdi 2257 popfq 2258 ret 2259 SET_SIZE(dtrace_interrupt_enable) 2260 2261#elif defined(__i386) 2262 2263 ENTRY(dtrace_interrupt_enable) 2264 movl 4(%esp), %eax 2265 pushl %eax 2266 popfl 2267 ret 2268 SET_SIZE(dtrace_interrupt_enable) 2269 2270#endif /* __i386 */ 2271#endif /* __lint */ 2272 2273 2274#if defined(lint) 2275 2276void 2277dtrace_membar_producer(void) 2278{} 2279 2280void 2281dtrace_membar_consumer(void) 2282{} 2283 2284#else /* __lint */ 2285 2286 ENTRY(dtrace_membar_producer) 2287 rep; ret /* use 2 byte return instruction when branch target */ 2288 /* AMD Software Optimization Guide - Section 6.2 */ 2289 SET_SIZE(dtrace_membar_producer) 2290 2291 ENTRY(dtrace_membar_consumer) 2292 rep; ret /* use 2 byte return instruction when branch target */ 2293 /* AMD Software Optimization Guide - Section 6.2 */ 2294 SET_SIZE(dtrace_membar_consumer) 2295 2296#endif /* __lint */ 2297 2298#if defined(__lint) 2299 2300kthread_id_t 2301threadp(void) 2302{ return ((kthread_id_t)0); } 2303 2304#else /* __lint */ 2305 2306#if defined(__amd64) 2307 2308 ENTRY(threadp) 2309 movq %gs:CPU_THREAD, %rax 2310 ret 2311 SET_SIZE(threadp) 2312 2313#elif defined(__i386) 2314 2315 ENTRY(threadp) 2316 movl %gs:CPU_THREAD, %eax 2317 ret 2318 SET_SIZE(threadp) 2319 2320#endif /* __i386 */ 2321#endif /* __lint */ 2322 2323/* 2324 * Checksum routine for Internet Protocol Headers 2325 */ 2326 2327#if defined(__lint) 2328 2329/* ARGSUSED */ 2330unsigned int 2331ip_ocsum( 2332 ushort_t *address, /* ptr to 1st message buffer */ 2333 int halfword_count, /* length of data */ 2334 unsigned int sum) /* partial checksum */ 2335{ 2336 int i; 2337 unsigned int psum = 0; /* partial sum */ 2338 2339 for (i = 0; i < halfword_count; i++, address++) { 2340 psum += *address; 2341 } 2342 2343 while ((psum >> 16) != 0) { 2344 psum = (psum & 0xffff) + (psum >> 16); 2345 } 2346 2347 psum += sum; 2348 2349 while ((psum >> 16) != 0) { 2350 psum = (psum & 0xffff) + (psum >> 16); 2351 } 2352 2353 return (psum); 2354} 2355 2356#else /* __lint */ 2357 2358#if defined(__amd64) 2359 2360 ENTRY(ip_ocsum) 2361 pushq %rbp 2362 movq %rsp, %rbp 2363#ifdef DEBUG 2364 movq kernelbase(%rip), %rax 2365 cmpq %rax, %rdi 2366 jnb 1f 2367 xorl %eax, %eax 2368 movq %rdi, %rsi 2369 leaq .ip_ocsum_panic_msg(%rip), %rdi 2370 call panic 2371 /*NOTREACHED*/ 2372.ip_ocsum_panic_msg: 2373 .string "ip_ocsum: address 0x%p below kernelbase\n" 23741: 2375#endif 2376 movl %esi, %ecx /* halfword_count */ 2377 movq %rdi, %rsi /* address */ 2378 /* partial sum in %edx */ 2379 xorl %eax, %eax 2380 testl %ecx, %ecx 2381 jz .ip_ocsum_done 2382 testq $3, %rsi 2383 jnz .ip_csum_notaligned 2384.ip_csum_aligned: /* XX64 opportunities for 8-byte operations? */ 2385.next_iter: 2386 /* XX64 opportunities for prefetch? */ 2387 /* XX64 compute csum with 64 bit quantities? */ 2388 subl $32, %ecx 2389 jl .less_than_32 2390 2391 addl 0(%rsi), %edx 2392.only60: 2393 adcl 4(%rsi), %eax 2394.only56: 2395 adcl 8(%rsi), %edx 2396.only52: 2397 adcl 12(%rsi), %eax 2398.only48: 2399 adcl 16(%rsi), %edx 2400.only44: 2401 adcl 20(%rsi), %eax 2402.only40: 2403 adcl 24(%rsi), %edx 2404.only36: 2405 adcl 28(%rsi), %eax 2406.only32: 2407 adcl 32(%rsi), %edx 2408.only28: 2409 adcl 36(%rsi), %eax 2410.only24: 2411 adcl 40(%rsi), %edx 2412.only20: 2413 adcl 44(%rsi), %eax 2414.only16: 2415 adcl 48(%rsi), %edx 2416.only12: 2417 adcl 52(%rsi), %eax 2418.only8: 2419 adcl 56(%rsi), %edx 2420.only4: 2421 adcl 60(%rsi), %eax /* could be adding -1 and -1 with a carry */ 2422.only0: 2423 adcl $0, %eax /* could be adding -1 in eax with a carry */ 2424 adcl $0, %eax 2425 2426 addq $64, %rsi 2427 testl %ecx, %ecx 2428 jnz .next_iter 2429 2430.ip_ocsum_done: 2431 addl %eax, %edx 2432 adcl $0, %edx 2433 movl %edx, %eax /* form a 16 bit checksum by */ 2434 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2435 addw %dx, %ax 2436 adcw $0, %ax 2437 andl $0xffff, %eax 2438 leave 2439 ret 2440 2441.ip_csum_notaligned: 2442 xorl %edi, %edi 2443 movw (%rsi), %di 2444 addl %edi, %edx 2445 adcl $0, %edx 2446 addq $2, %rsi 2447 decl %ecx 2448 jmp .ip_csum_aligned 2449 2450.less_than_32: 2451 addl $32, %ecx 2452 testl $1, %ecx 2453 jz .size_aligned 2454 andl $0xfe, %ecx 2455 movzwl (%rsi, %rcx, 2), %edi 2456 addl %edi, %edx 2457 adcl $0, %edx 2458.size_aligned: 2459 movl %ecx, %edi 2460 shrl $1, %ecx 2461 shl $1, %edi 2462 subq $64, %rdi 2463 addq %rdi, %rsi 2464 leaq .ip_ocsum_jmptbl(%rip), %rdi 2465 leaq (%rdi, %rcx, 8), %rdi 2466 xorl %ecx, %ecx 2467 clc 2468 jmp *(%rdi) 2469 2470 .align 8 2471.ip_ocsum_jmptbl: 2472 .quad .only0, .only4, .only8, .only12, .only16, .only20 2473 .quad .only24, .only28, .only32, .only36, .only40, .only44 2474 .quad .only48, .only52, .only56, .only60 2475 SET_SIZE(ip_ocsum) 2476 2477#elif defined(__i386) 2478 2479 ENTRY(ip_ocsum) 2480 pushl %ebp 2481 movl %esp, %ebp 2482 pushl %ebx 2483 pushl %esi 2484 pushl %edi 2485 movl 12(%ebp), %ecx /* count of half words */ 2486 movl 16(%ebp), %edx /* partial checksum */ 2487 movl 8(%ebp), %esi 2488 xorl %eax, %eax 2489 testl %ecx, %ecx 2490 jz .ip_ocsum_done 2491 2492 testl $3, %esi 2493 jnz .ip_csum_notaligned 2494.ip_csum_aligned: 2495.next_iter: 2496 subl $32, %ecx 2497 jl .less_than_32 2498 2499 addl 0(%esi), %edx 2500.only60: 2501 adcl 4(%esi), %eax 2502.only56: 2503 adcl 8(%esi), %edx 2504.only52: 2505 adcl 12(%esi), %eax 2506.only48: 2507 adcl 16(%esi), %edx 2508.only44: 2509 adcl 20(%esi), %eax 2510.only40: 2511 adcl 24(%esi), %edx 2512.only36: 2513 adcl 28(%esi), %eax 2514.only32: 2515 adcl 32(%esi), %edx 2516.only28: 2517 adcl 36(%esi), %eax 2518.only24: 2519 adcl 40(%esi), %edx 2520.only20: 2521 adcl 44(%esi), %eax 2522.only16: 2523 adcl 48(%esi), %edx 2524.only12: 2525 adcl 52(%esi), %eax 2526.only8: 2527 adcl 56(%esi), %edx 2528.only4: 2529 adcl 60(%esi), %eax /* We could be adding -1 and -1 with a carry */ 2530.only0: 2531 adcl $0, %eax /* we could be adding -1 in eax with a carry */ 2532 adcl $0, %eax 2533 2534 addl $64, %esi 2535 andl %ecx, %ecx 2536 jnz .next_iter 2537 2538.ip_ocsum_done: 2539 addl %eax, %edx 2540 adcl $0, %edx 2541 movl %edx, %eax /* form a 16 bit checksum by */ 2542 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2543 addw %dx, %ax 2544 adcw $0, %ax 2545 andl $0xffff, %eax 2546 popl %edi /* restore registers */ 2547 popl %esi 2548 popl %ebx 2549 leave 2550 ret 2551 2552.ip_csum_notaligned: 2553 xorl %edi, %edi 2554 movw (%esi), %di 2555 addl %edi, %edx 2556 adcl $0, %edx 2557 addl $2, %esi 2558 decl %ecx 2559 jmp .ip_csum_aligned 2560 2561.less_than_32: 2562 addl $32, %ecx 2563 testl $1, %ecx 2564 jz .size_aligned 2565 andl $0xfe, %ecx 2566 movzwl (%esi, %ecx, 2), %edi 2567 addl %edi, %edx 2568 adcl $0, %edx 2569.size_aligned: 2570 movl %ecx, %edi 2571 shrl $1, %ecx 2572 shl $1, %edi 2573 subl $64, %edi 2574 addl %edi, %esi 2575 movl $.ip_ocsum_jmptbl, %edi 2576 lea (%edi, %ecx, 4), %edi 2577 xorl %ecx, %ecx 2578 clc 2579 jmp *(%edi) 2580 SET_SIZE(ip_ocsum) 2581 2582 .data 2583 .align 4 2584 2585.ip_ocsum_jmptbl: 2586 .long .only0, .only4, .only8, .only12, .only16, .only20 2587 .long .only24, .only28, .only32, .only36, .only40, .only44 2588 .long .only48, .only52, .only56, .only60 2589 2590 2591#endif /* __i386 */ 2592#endif /* __lint */ 2593 2594/* 2595 * multiply two long numbers and yield a u_longlong_t result, callable from C. 2596 * Provided to manipulate hrtime_t values. 2597 */ 2598#if defined(__lint) 2599 2600/* result = a * b; */ 2601 2602/* ARGSUSED */ 2603unsigned long long 2604mul32(uint_t a, uint_t b) 2605{ return (0); } 2606 2607#else /* __lint */ 2608 2609#if defined(__amd64) 2610 2611 ENTRY(mul32) 2612 xorl %edx, %edx /* XX64 joe, paranoia? */ 2613 movl %edi, %eax 2614 mull %esi 2615 shlq $32, %rdx 2616 orq %rdx, %rax 2617 ret 2618 SET_SIZE(mul32) 2619 2620#elif defined(__i386) 2621 2622 ENTRY(mul32) 2623 movl 8(%esp), %eax 2624 movl 4(%esp), %ecx 2625 mull %ecx 2626 ret 2627 SET_SIZE(mul32) 2628 2629#endif /* __i386 */ 2630#endif /* __lint */ 2631 2632#if defined(notused) 2633#if defined(__lint) 2634/* ARGSUSED */ 2635void 2636load_pte64(uint64_t *pte, uint64_t pte_value) 2637{} 2638#else /* __lint */ 2639 .globl load_pte64 2640load_pte64: 2641 movl 4(%esp), %eax 2642 movl 8(%esp), %ecx 2643 movl 12(%esp), %edx 2644 movl %edx, 4(%eax) 2645 movl %ecx, (%eax) 2646 ret 2647#endif /* __lint */ 2648#endif /* notused */ 2649 2650#if defined(__lint) 2651 2652/*ARGSUSED*/ 2653void 2654scan_memory(caddr_t addr, size_t size) 2655{} 2656 2657#else /* __lint */ 2658 2659#if defined(__amd64) 2660 2661 ENTRY(scan_memory) 2662 shrq $3, %rsi /* convert %rsi from byte to quadword count */ 2663 jz .scanm_done 2664 movq %rsi, %rcx /* move count into rep control register */ 2665 movq %rdi, %rsi /* move addr into lodsq control reg. */ 2666 rep lodsq /* scan the memory range */ 2667.scanm_done: 2668 rep; ret /* use 2 byte return instruction when branch target */ 2669 /* AMD Software Optimization Guide - Section 6.2 */ 2670 SET_SIZE(scan_memory) 2671 2672#elif defined(__i386) 2673 2674 ENTRY(scan_memory) 2675 pushl %ecx 2676 pushl %esi 2677 movl 16(%esp), %ecx /* move 2nd arg into rep control register */ 2678 shrl $2, %ecx /* convert from byte count to word count */ 2679 jz .scanm_done 2680 movl 12(%esp), %esi /* move 1st arg into lodsw control register */ 2681 .byte 0xf3 /* rep prefix. lame assembler. sigh. */ 2682 lodsl 2683.scanm_done: 2684 popl %esi 2685 popl %ecx 2686 ret 2687 SET_SIZE(scan_memory) 2688 2689#endif /* __i386 */ 2690#endif /* __lint */ 2691 2692 2693#if defined(__lint) 2694 2695/*ARGSUSED */ 2696int 2697lowbit(ulong_t i) 2698{ return (0); } 2699 2700#else /* __lint */ 2701 2702#if defined(__amd64) 2703 2704 ENTRY(lowbit) 2705 movl $-1, %eax 2706 bsfq %rdi, %rax 2707 incl %eax 2708 ret 2709 SET_SIZE(lowbit) 2710 2711#elif defined(__i386) 2712 2713 ENTRY(lowbit) 2714 movl $-1, %eax 2715 bsfl 4(%esp), %eax 2716 incl %eax 2717 ret 2718 SET_SIZE(lowbit) 2719 2720#endif /* __i386 */ 2721#endif /* __lint */ 2722 2723#if defined(__lint) 2724 2725/*ARGSUSED*/ 2726int 2727highbit(ulong_t i) 2728{ return (0); } 2729 2730#else /* __lint */ 2731 2732#if defined(__amd64) 2733 2734 ENTRY(highbit) 2735 movl $-1, %eax 2736 bsrq %rdi, %rax 2737 incl %eax 2738 ret 2739 SET_SIZE(highbit) 2740 2741#elif defined(__i386) 2742 2743 ENTRY(highbit) 2744 movl $-1, %eax 2745 bsrl 4(%esp), %eax 2746 incl %eax 2747 ret 2748 SET_SIZE(highbit) 2749 2750#endif /* __i386 */ 2751#endif /* __lint */ 2752 2753#if defined(__lint) 2754 2755/*ARGSUSED*/ 2756uint64_t 2757rdmsr(uint_t r) 2758{ return (0); } 2759 2760/*ARGSUSED*/ 2761void 2762wrmsr(uint_t r, const uint64_t val) 2763{} 2764 2765void 2766invalidate_cache(void) 2767{} 2768 2769#else /* __lint */ 2770 2771#if defined(__amd64) 2772 2773 ENTRY(rdmsr) 2774 movl %edi, %ecx 2775 rdmsr 2776 shlq $32, %rdx 2777 orq %rdx, %rax 2778 ret 2779 SET_SIZE(rdmsr) 2780 2781 ENTRY(wrmsr) 2782 movq %rsi, %rdx 2783 shrq $32, %rdx 2784 movl %esi, %eax 2785 movl %edi, %ecx 2786 wrmsr 2787 ret 2788 SET_SIZE(wrmsr) 2789 2790#elif defined(__i386) 2791 2792 ENTRY(rdmsr) 2793 movl 4(%esp), %ecx 2794 rdmsr 2795 ret 2796 SET_SIZE(rdmsr) 2797 2798 ENTRY(wrmsr) 2799 movl 4(%esp), %ecx 2800 movl 8(%esp), %eax 2801 movl 12(%esp), %edx 2802 wrmsr 2803 ret 2804 SET_SIZE(wrmsr) 2805 2806#endif /* __i386 */ 2807 2808 ENTRY(invalidate_cache) 2809 wbinvd 2810 ret 2811 SET_SIZE(invalidate_cache) 2812 2813#endif /* __lint */ 2814 2815#if defined(__lint) 2816 2817/*ARGSUSED*/ 2818void getcregs(struct cregs *crp) 2819{} 2820 2821#else /* __lint */ 2822 2823#if defined(__amd64) 2824 2825#define GETMSR(r, off, d) \ 2826 movl $r, %ecx; \ 2827 rdmsr; \ 2828 movl %eax, off(d); \ 2829 movl %edx, off+4(d) 2830 2831 ENTRY_NP(getcregs) 2832 xorl %eax, %eax 2833 movq %rax, CREG_GDT+8(%rdi) 2834 sgdt CREG_GDT(%rdi) /* 10 bytes */ 2835 movq %rax, CREG_IDT+8(%rdi) 2836 sidt CREG_IDT(%rdi) /* 10 bytes */ 2837 movq %rax, CREG_LDT(%rdi) 2838 sldt CREG_LDT(%rdi) /* 2 bytes */ 2839 movq %rax, CREG_TASKR(%rdi) 2840 str CREG_TASKR(%rdi) /* 2 bytes */ 2841 movq %cr0, %rax 2842 movq %rax, CREG_CR0(%rdi) /* cr0 */ 2843 movq %cr2, %rax 2844 movq %rax, CREG_CR2(%rdi) /* cr2 */ 2845 movq %cr3, %rax 2846 movq %rax, CREG_CR3(%rdi) /* cr3 */ 2847 movq %cr4, %rax 2848 movq %rax, CREG_CR8(%rdi) /* cr4 */ 2849 movq %cr8, %rax 2850 movq %rax, CREG_CR8(%rdi) /* cr8 */ 2851 GETMSR(MSR_AMD_KGSBASE, CREG_KGSBASE, %rdi) 2852 GETMSR(MSR_AMD_EFER, CREG_EFER, %rdi) 2853 SET_SIZE(getcregs) 2854 2855#undef GETMSR 2856 2857#elif defined(__i386) 2858 2859 ENTRY_NP(getcregs) 2860 movl 4(%esp), %edx 2861 movw $0, CREG_GDT+6(%edx) 2862 movw $0, CREG_IDT+6(%edx) 2863 sgdt CREG_GDT(%edx) /* gdt */ 2864 sidt CREG_IDT(%edx) /* idt */ 2865 sldt CREG_LDT(%edx) /* ldt */ 2866 str CREG_TASKR(%edx) /* task */ 2867 movl %cr0, %eax 2868 movl %eax, CREG_CR0(%edx) /* cr0 */ 2869 movl %cr2, %eax 2870 movl %eax, CREG_CR2(%edx) /* cr2 */ 2871 movl %cr3, %eax 2872 movl %eax, CREG_CR3(%edx) /* cr3 */ 2873 testl $X86_LARGEPAGE, x86_feature 2874 jz .nocr4 2875 movl %cr4, %eax 2876 movl %eax, CREG_CR4(%edx) /* cr4 */ 2877 jmp .skip 2878.nocr4: 2879 movl $0, CREG_CR4(%edx) 2880.skip: 2881 rep; ret /* use 2 byte return instruction when branch target */ 2882 /* AMD Software Optimization Guide - Section 6.2 */ 2883 SET_SIZE(getcregs) 2884 2885#endif /* __i386 */ 2886#endif /* __lint */ 2887 2888 2889/* 2890 * A panic trigger is a word which is updated atomically and can only be set 2891 * once. We atomically store 0xDEFACEDD and load the old value. If the 2892 * previous value was 0, we succeed and return 1; otherwise return 0. 2893 * This allows a partially corrupt trigger to still trigger correctly. DTrace 2894 * has its own version of this function to allow it to panic correctly from 2895 * probe context. 2896 */ 2897#if defined(__lint) 2898 2899/*ARGSUSED*/ 2900int 2901panic_trigger(int *tp) 2902{ return (0); } 2903 2904/*ARGSUSED*/ 2905int 2906dtrace_panic_trigger(int *tp) 2907{ return (0); } 2908 2909#else /* __lint */ 2910 2911#if defined(__amd64) 2912 2913 ENTRY_NP(panic_trigger) 2914 xorl %eax, %eax 2915 movl $0xdefacedd, %edx 2916 lock 2917 xchgl %edx, (%rdi) 2918 cmpl $0, %edx 2919 je 0f 2920 movl $0, %eax 2921 ret 29220: movl $1, %eax 2923 ret 2924 SET_SIZE(panic_trigger) 2925 2926 ENTRY_NP(dtrace_panic_trigger) 2927 xorl %eax, %eax 2928 movl $0xdefacedd, %edx 2929 lock 2930 xchgl %edx, (%rdi) 2931 cmpl $0, %edx 2932 je 0f 2933 movl $0, %eax 2934 ret 29350: movl $1, %eax 2936 ret 2937 SET_SIZE(dtrace_panic_trigger) 2938 2939#elif defined(__i386) 2940 2941 ENTRY_NP(panic_trigger) 2942 movl 4(%esp), %edx / %edx = address of trigger 2943 movl $0xdefacedd, %eax / %eax = 0xdefacedd 2944 lock / assert lock 2945 xchgl %eax, (%edx) / exchange %eax and the trigger 2946 cmpl $0, %eax / if (%eax == 0x0) 2947 je 0f / return (1); 2948 movl $0, %eax / else 2949 ret / return (0); 29500: movl $1, %eax 2951 ret 2952 SET_SIZE(panic_trigger) 2953 2954 ENTRY_NP(dtrace_panic_trigger) 2955 movl 4(%esp), %edx / %edx = address of trigger 2956 movl $0xdefacedd, %eax / %eax = 0xdefacedd 2957 lock / assert lock 2958 xchgl %eax, (%edx) / exchange %eax and the trigger 2959 cmpl $0, %eax / if (%eax == 0x0) 2960 je 0f / return (1); 2961 movl $0, %eax / else 2962 ret / return (0); 29630: movl $1, %eax 2964 ret 2965 SET_SIZE(dtrace_panic_trigger) 2966 2967#endif /* __i386 */ 2968#endif /* __lint */ 2969 2970/* 2971 * The panic() and cmn_err() functions invoke vpanic() as a common entry point 2972 * into the panic code implemented in panicsys(). vpanic() is responsible 2973 * for passing through the format string and arguments, and constructing a 2974 * regs structure on the stack into which it saves the current register 2975 * values. If we are not dying due to a fatal trap, these registers will 2976 * then be preserved in panicbuf as the current processor state. Before 2977 * invoking panicsys(), vpanic() activates the first panic trigger (see 2978 * common/os/panic.c) and switches to the panic_stack if successful. Note that 2979 * DTrace takes a slightly different panic path if it must panic from probe 2980 * context. Instead of calling panic, it calls into dtrace_vpanic(), which 2981 * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and 2982 * branches back into vpanic(). 2983 */ 2984#if defined(__lint) 2985 2986/*ARGSUSED*/ 2987void 2988vpanic(const char *format, va_list alist) 2989{} 2990 2991/*ARGSUSED*/ 2992void 2993dtrace_vpanic(const char *format, va_list alist) 2994{} 2995 2996#else /* __lint */ 2997 2998#if defined(__amd64) 2999 3000 ENTRY_NP(vpanic) /* Initial stack layout: */ 3001 3002 pushq %rbp /* | %rip | 0x60 */ 3003 movq %rsp, %rbp /* | %rbp | 0x58 */ 3004 pushfq /* | rfl | 0x50 */ 3005 pushq %r11 /* | %r11 | 0x48 */ 3006 pushq %r10 /* | %r10 | 0x40 */ 3007 pushq %rbx /* | %rbx | 0x38 */ 3008 pushq %rax /* | %rax | 0x30 */ 3009 pushq %r9 /* | %r9 | 0x28 */ 3010 pushq %r8 /* | %r8 | 0x20 */ 3011 pushq %rcx /* | %rcx | 0x18 */ 3012 pushq %rdx /* | %rdx | 0x10 */ 3013 pushq %rsi /* | %rsi | 0x8 alist */ 3014 pushq %rdi /* | %rdi | 0x0 format */ 3015 3016 movq %rsp, %rbx /* %rbx = current %rsp */ 3017 3018 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 3019 call panic_trigger /* %eax = panic_trigger() */ 3020 3021vpanic_common: 3022 cmpl $0, %eax 3023 je 0f 3024 3025 /* 3026 * If panic_trigger() was successful, we are the first to initiate a 3027 * panic: we now switch to the reserved panic_stack before continuing. 3028 */ 3029 leaq panic_stack(%rip), %rsp 3030 addq $PANICSTKSIZE, %rsp 30310: subq $REGSIZE, %rsp 3032 /* 3033 * Now that we've got everything set up, store the register values as 3034 * they were when we entered vpanic() to the designated location in 3035 * the regs structure we allocated on the stack. 3036 */ 3037 movq 0x0(%rbx), %rcx 3038 movq %rcx, REGOFF_RDI(%rsp) 3039 movq 0x8(%rbx), %rcx 3040 movq %rcx, REGOFF_RSI(%rsp) 3041 movq 0x10(%rbx), %rcx 3042 movq %rcx, REGOFF_RDX(%rsp) 3043 movq 0x18(%rbx), %rcx 3044 movq %rcx, REGOFF_RCX(%rsp) 3045 movq 0x20(%rbx), %rcx 3046 3047 movq %rcx, REGOFF_R8(%rsp) 3048 movq 0x28(%rbx), %rcx 3049 movq %rcx, REGOFF_R9(%rsp) 3050 movq 0x30(%rbx), %rcx 3051 movq %rcx, REGOFF_RAX(%rsp) 3052 movq 0x38(%rbx), %rcx 3053 movq %rbx, REGOFF_RBX(%rsp) 3054 movq 0x58(%rbx), %rcx 3055 3056 movq %rcx, REGOFF_RBP(%rsp) 3057 movq 0x40(%rbx), %rcx 3058 movq %rcx, REGOFF_R10(%rsp) 3059 movq 0x48(%rbx), %rcx 3060 movq %rcx, REGOFF_R11(%rsp) 3061 movq %r12, REGOFF_R12(%rsp) 3062 3063 movq %r13, REGOFF_R13(%rsp) 3064 movq %r14, REGOFF_R14(%rsp) 3065 movq %r15, REGOFF_R15(%rsp) 3066 3067 movl $MSR_AMD_FSBASE, %ecx 3068 rdmsr 3069 movl %eax, REGOFF_FSBASE(%rsp) 3070 movl %edx, REGOFF_FSBASE+4(%rsp) 3071 3072 movl $MSR_AMD_GSBASE, %ecx 3073 rdmsr 3074 movl %eax, REGOFF_GSBASE(%rsp) 3075 movl %edx, REGOFF_GSBASE+4(%rsp) 3076 3077 xorl %ecx, %ecx 3078 movw %ds, %cx 3079 movq %rcx, REGOFF_DS(%rsp) 3080 movw %es, %cx 3081 movq %rcx, REGOFF_ES(%rsp) 3082 movw %fs, %cx 3083 movq %rcx, REGOFF_FS(%rsp) 3084 movw %gs, %cx 3085 movq %rcx, REGOFF_GS(%rsp) 3086 3087 movq $0, REGOFF_TRAPNO(%rsp) 3088 3089 movq $0, REGOFF_ERR(%rsp) 3090 leaq vpanic(%rip), %rcx 3091 movq %rcx, REGOFF_RIP(%rsp) 3092 movw %cs, %cx 3093 movzwq %cx, %rcx 3094 movq %rcx, REGOFF_CS(%rsp) 3095 movq 0x50(%rbx), %rcx 3096 movq %rcx, REGOFF_RFL(%rsp) 3097 movq %rbx, %rcx 3098 addq $0x60, %rcx 3099 movq %rcx, REGOFF_RSP(%rsp) 3100 movw %ss, %cx 3101 movzwq %cx, %rcx 3102 movq %rcx, REGOFF_SS(%rsp) 3103 3104 /* 3105 * panicsys(format, alist, rp, on_panic_stack) 3106 */ 3107 movq REGOFF_RDI(%rsp), %rdi /* format */ 3108 movq REGOFF_RSI(%rsp), %rsi /* alist */ 3109 movq %rsp, %rdx /* struct regs */ 3110 movl %eax, %ecx /* on_panic_stack */ 3111 call panicsys 3112 addq $REGSIZE, %rsp 3113 popq %rdi 3114 popq %rsi 3115 popq %rdx 3116 popq %rcx 3117 popq %r8 3118 popq %r9 3119 popq %rax 3120 popq %rbx 3121 popq %r10 3122 popq %r11 3123 popfq 3124 leave 3125 ret 3126 SET_SIZE(vpanic) 3127 3128 ENTRY_NP(dtrace_vpanic) /* Initial stack layout: */ 3129 3130 pushq %rbp /* | %rip | 0x60 */ 3131 movq %rsp, %rbp /* | %rbp | 0x58 */ 3132 pushfq /* | rfl | 0x50 */ 3133 pushq %r11 /* | %r11 | 0x48 */ 3134 pushq %r10 /* | %r10 | 0x40 */ 3135 pushq %rbx /* | %rbx | 0x38 */ 3136 pushq %rax /* | %rax | 0x30 */ 3137 pushq %r9 /* | %r9 | 0x28 */ 3138 pushq %r8 /* | %r8 | 0x20 */ 3139 pushq %rcx /* | %rcx | 0x18 */ 3140 pushq %rdx /* | %rdx | 0x10 */ 3141 pushq %rsi /* | %rsi | 0x8 alist */ 3142 pushq %rdi /* | %rdi | 0x0 format */ 3143 3144 movq %rsp, %rbx /* %rbx = current %rsp */ 3145 3146 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 3147 call dtrace_panic_trigger /* %eax = dtrace_panic_trigger() */ 3148 jmp vpanic_common 3149 3150 SET_SIZE(dtrace_vpanic) 3151 3152#elif defined(__i386) 3153 3154 ENTRY_NP(vpanic) / Initial stack layout: 3155 3156 pushl %ebp / | %eip | 20 3157 movl %esp, %ebp / | %ebp | 16 3158 pushl %eax / | %eax | 12 3159 pushl %ebx / | %ebx | 8 3160 pushl %ecx / | %ecx | 4 3161 pushl %edx / | %edx | 0 3162 3163 movl %esp, %ebx / %ebx = current stack pointer 3164 3165 lea panic_quiesce, %eax / %eax = &panic_quiesce 3166 pushl %eax / push &panic_quiesce 3167 call panic_trigger / %eax = panic_trigger() 3168 addl $4, %esp / reset stack pointer 3169 3170vpanic_common: 3171 cmpl $0, %eax / if (%eax == 0) 3172 je 0f / goto 0f; 3173 3174 /* 3175 * If panic_trigger() was successful, we are the first to initiate a 3176 * panic: we now switch to the reserved panic_stack before continuing. 3177 */ 3178 lea panic_stack, %esp / %esp = panic_stack 3179 addl $PANICSTKSIZE, %esp / %esp += PANICSTKSIZE 3180 31810: subl $REGSIZE, %esp / allocate struct regs 3182 3183 /* 3184 * Now that we've got everything set up, store the register values as 3185 * they were when we entered vpanic() to the designated location in 3186 * the regs structure we allocated on the stack. 3187 */ 3188#if !defined(__GNUC_AS__) 3189 movw %gs, %edx 3190 movl %edx, REGOFF_GS(%esp) 3191 movw %fs, %edx 3192 movl %edx, REGOFF_FS(%esp) 3193 movw %es, %edx 3194 movl %edx, REGOFF_ES(%esp) 3195 movw %ds, %edx 3196 movl %edx, REGOFF_DS(%esp) 3197#else /* __GNUC_AS__ */ 3198 mov %gs, %edx 3199 mov %edx, REGOFF_GS(%esp) 3200 mov %fs, %edx 3201 mov %edx, REGOFF_FS(%esp) 3202 mov %es, %edx 3203 mov %edx, REGOFF_ES(%esp) 3204 mov %ds, %edx 3205 mov %edx, REGOFF_DS(%esp) 3206#endif /* __GNUC_AS__ */ 3207 movl %edi, REGOFF_EDI(%esp) 3208 movl %esi, REGOFF_ESI(%esp) 3209 movl 16(%ebx), %ecx 3210 movl %ecx, REGOFF_EBP(%esp) 3211 movl %ebx, %ecx 3212 addl $20, %ecx 3213 movl %ecx, REGOFF_ESP(%esp) 3214 movl 8(%ebx), %ecx 3215 movl %ecx, REGOFF_EBX(%esp) 3216 movl 0(%ebx), %ecx 3217 movl %ecx, REGOFF_EDX(%esp) 3218 movl 4(%ebx), %ecx 3219 movl %ecx, REGOFF_ECX(%esp) 3220 movl 12(%ebx), %ecx 3221 movl %ecx, REGOFF_EAX(%esp) 3222 movl $0, REGOFF_TRAPNO(%esp) 3223 movl $0, REGOFF_ERR(%esp) 3224 lea vpanic, %ecx 3225 movl %ecx, REGOFF_EIP(%esp) 3226#if !defined(__GNUC_AS__) 3227 movw %cs, %edx 3228#else /* __GNUC_AS__ */ 3229 mov %cs, %edx 3230#endif /* __GNUC_AS__ */ 3231 movl %edx, REGOFF_CS(%esp) 3232 pushfl 3233 popl %ecx 3234 movl %ecx, REGOFF_EFL(%esp) 3235 movl $0, REGOFF_UESP(%esp) 3236#if !defined(__GNUC_AS__) 3237 movw %ss, %edx 3238#else /* __GNUC_AS__ */ 3239 mov %ss, %edx 3240#endif /* __GNUC_AS__ */ 3241 movl %edx, REGOFF_SS(%esp) 3242 3243 movl %esp, %ecx / %ecx = ®s 3244 pushl %eax / push on_panic_stack 3245 pushl %ecx / push ®s 3246 movl 12(%ebp), %ecx / %ecx = alist 3247 pushl %ecx / push alist 3248 movl 8(%ebp), %ecx / %ecx = format 3249 pushl %ecx / push format 3250 call panicsys / panicsys(); 3251 addl $16, %esp / pop arguments 3252 3253 addl $REGSIZE, %esp 3254 popl %edx 3255 popl %ecx 3256 popl %ebx 3257 popl %eax 3258 leave 3259 ret 3260 SET_SIZE(vpanic) 3261 3262 ENTRY_NP(dtrace_vpanic) / Initial stack layout: 3263 3264 pushl %ebp / | %eip | 20 3265 movl %esp, %ebp / | %ebp | 16 3266 pushl %eax / | %eax | 12 3267 pushl %ebx / | %ebx | 8 3268 pushl %ecx / | %ecx | 4 3269 pushl %edx / | %edx | 0 3270 3271 movl %esp, %ebx / %ebx = current stack pointer 3272 3273 lea panic_quiesce, %eax / %eax = &panic_quiesce 3274 pushl %eax / push &panic_quiesce 3275 call dtrace_panic_trigger / %eax = dtrace_panic_trigger() 3276 addl $4, %esp / reset stack pointer 3277 jmp vpanic_common / jump back to common code 3278 3279 SET_SIZE(dtrace_vpanic) 3280 3281#endif /* __i386 */ 3282#endif /* __lint */ 3283 3284#if defined(__lint) 3285 3286void 3287hres_tick(void) 3288{} 3289 3290int64_t timedelta; 3291hrtime_t hres_last_tick; 3292timestruc_t hrestime; 3293int64_t hrestime_adj; 3294volatile int hres_lock; 3295uint_t nsec_scale; 3296hrtime_t hrtime_base; 3297 3298#else /* __lint */ 3299 3300 DGDEF3(hrestime, _MUL(2, CLONGSIZE), 8) 3301 .NWORD 0, 0 3302 3303 DGDEF3(hrestime_adj, 8, 8) 3304 .long 0, 0 3305 3306 DGDEF3(hres_last_tick, 8, 8) 3307 .long 0, 0 3308 3309 DGDEF3(timedelta, 8, 8) 3310 .long 0, 0 3311 3312 DGDEF3(hres_lock, 4, 8) 3313 .long 0 3314 3315 /* 3316 * initialized to a non zero value to make pc_gethrtime() 3317 * work correctly even before clock is initialized 3318 */ 3319 DGDEF3(hrtime_base, 8, 8) 3320 .long _MUL(NSEC_PER_CLOCK_TICK, 6), 0 3321 3322 DGDEF3(adj_shift, 4, 4) 3323 .long ADJ_SHIFT 3324 3325#if defined(__amd64) 3326 3327 ENTRY_NP(hres_tick) 3328 pushq %rbp 3329 movq %rsp, %rbp 3330 3331 /* 3332 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3333 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3334 * At worst, performing this now instead of under CLOCK_LOCK may 3335 * introduce some jitter in pc_gethrestime(). 3336 */ 3337 call *gethrtimef(%rip) 3338 movq %rax, %r8 3339 3340 leaq hres_lock(%rip), %rax 3341 movb $-1, %dl 3342.CL1: 3343 xchgb %dl, (%rax) 3344 testb %dl, %dl 3345 jz .CL3 /* got it */ 3346.CL2: 3347 cmpb $0, (%rax) /* possible to get lock? */ 3348 pause 3349 jne .CL2 3350 jmp .CL1 /* yes, try again */ 3351.CL3: 3352 /* 3353 * compute the interval since last time hres_tick was called 3354 * and adjust hrtime_base and hrestime accordingly 3355 * hrtime_base is an 8 byte value (in nsec), hrestime is 3356 * a timestruc_t (sec, nsec) 3357 */ 3358 leaq hres_last_tick(%rip), %rax 3359 movq %r8, %r11 3360 subq (%rax), %r8 3361 addq %r8, hrtime_base(%rip) /* add interval to hrtime_base */ 3362 addq %r8, hrestime+8(%rip) /* add interval to hrestime.tv_nsec */ 3363 /* 3364 * Now that we have CLOCK_LOCK, we can update hres_last_tick 3365 */ 3366 movq %r11, (%rax) 3367 3368 call __adj_hrestime 3369 3370 /* 3371 * release the hres_lock 3372 */ 3373 incl hres_lock(%rip) 3374 leave 3375 ret 3376 SET_SIZE(hres_tick) 3377 3378#elif defined(__i386) 3379 3380 ENTRY_NP(hres_tick) 3381 pushl %ebp 3382 movl %esp, %ebp 3383 pushl %esi 3384 pushl %ebx 3385 3386 /* 3387 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3388 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3389 * At worst, performing this now instead of under CLOCK_LOCK may 3390 * introduce some jitter in pc_gethrestime(). 3391 */ 3392 call *gethrtimef 3393 movl %eax, %ebx 3394 movl %edx, %esi 3395 3396 movl $hres_lock, %eax 3397 movl $-1, %edx 3398.CL1: 3399 xchgb %dl, (%eax) 3400 testb %dl, %dl 3401 jz .CL3 / got it 3402.CL2: 3403 cmpb $0, (%eax) / possible to get lock? 3404 pause 3405 jne .CL2 3406 jmp .CL1 / yes, try again 3407.CL3: 3408 /* 3409 * compute the interval since last time hres_tick was called 3410 * and adjust hrtime_base and hrestime accordingly 3411 * hrtime_base is an 8 byte value (in nsec), hrestime is 3412 * timestruc_t (sec, nsec) 3413 */ 3414 3415 lea hres_last_tick, %eax 3416 3417 movl %ebx, %edx 3418 movl %esi, %ecx 3419 3420 subl (%eax), %edx 3421 sbbl 4(%eax), %ecx 3422 3423 addl %edx, hrtime_base / add interval to hrtime_base 3424 adcl %ecx, hrtime_base+4 3425 3426 addl %edx, hrestime+4 / add interval to hrestime.tv_nsec 3427 3428 / 3429 / Now that we have CLOCK_LOCK, we can update hres_last_tick. 3430 / 3431 movl %ebx, (%eax) 3432 movl %esi, 4(%eax) 3433 3434 / get hrestime at this moment. used as base for pc_gethrestime 3435 / 3436 / Apply adjustment, if any 3437 / 3438 / #define HRES_ADJ (NSEC_PER_CLOCK_TICK >> ADJ_SHIFT) 3439 / (max_hres_adj) 3440 / 3441 / void 3442 / adj_hrestime() 3443 / { 3444 / long long adj; 3445 / 3446 / if (hrestime_adj == 0) 3447 / adj = 0; 3448 / else if (hrestime_adj > 0) { 3449 / if (hrestime_adj < HRES_ADJ) 3450 / adj = hrestime_adj; 3451 / else 3452 / adj = HRES_ADJ; 3453 / } 3454 / else { 3455 / if (hrestime_adj < -(HRES_ADJ)) 3456 / adj = -(HRES_ADJ); 3457 / else 3458 / adj = hrestime_adj; 3459 / } 3460 / 3461 / timedelta -= adj; 3462 / hrestime_adj = timedelta; 3463 / hrestime.tv_nsec += adj; 3464 / 3465 / while (hrestime.tv_nsec >= NANOSEC) { 3466 / one_sec++; 3467 / hrestime.tv_sec++; 3468 / hrestime.tv_nsec -= NANOSEC; 3469 / } 3470 / } 3471__adj_hrestime: 3472 movl hrestime_adj, %esi / if (hrestime_adj == 0) 3473 movl hrestime_adj+4, %edx 3474 andl %esi, %esi 3475 jne .CL4 / no 3476 andl %edx, %edx 3477 jne .CL4 / no 3478 subl %ecx, %ecx / yes, adj = 0; 3479 subl %edx, %edx 3480 jmp .CL5 3481.CL4: 3482 subl %ecx, %ecx 3483 subl %eax, %eax 3484 subl %esi, %ecx 3485 sbbl %edx, %eax 3486 andl %eax, %eax / if (hrestime_adj > 0) 3487 jge .CL6 3488 3489 / In the following comments, HRES_ADJ is used, while in the code 3490 / max_hres_adj is used. 3491 / 3492 / The test for "hrestime_adj < HRES_ADJ" is complicated because 3493 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3494 / on the logical equivalence of: 3495 / 3496 / !(hrestime_adj < HRES_ADJ) 3497 / 3498 / and the two step sequence: 3499 / 3500 / (HRES_ADJ - lsw(hrestime_adj)) generates a Borrow/Carry 3501 / 3502 / which computes whether or not the least significant 32-bits 3503 / of hrestime_adj is greater than HRES_ADJ, followed by: 3504 / 3505 / Previous Borrow/Carry + -1 + msw(hrestime_adj) generates a Carry 3506 / 3507 / which generates a carry whenever step 1 is true or the most 3508 / significant long of the longlong hrestime_adj is non-zero. 3509 3510 movl max_hres_adj, %ecx / hrestime_adj is positive 3511 subl %esi, %ecx 3512 movl %edx, %eax 3513 adcl $-1, %eax 3514 jnc .CL7 3515 movl max_hres_adj, %ecx / adj = HRES_ADJ; 3516 subl %edx, %edx 3517 jmp .CL5 3518 3519 / The following computation is similar to the one above. 3520 / 3521 / The test for "hrestime_adj < -(HRES_ADJ)" is complicated because 3522 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3523 / on the logical equivalence of: 3524 / 3525 / (hrestime_adj > -HRES_ADJ) 3526 / 3527 / and the two step sequence: 3528 / 3529 / (HRES_ADJ + lsw(hrestime_adj)) generates a Carry 3530 / 3531 / which means the least significant 32-bits of hrestime_adj is 3532 / greater than -HRES_ADJ, followed by: 3533 / 3534 / Previous Carry + 0 + msw(hrestime_adj) generates a Carry 3535 / 3536 / which generates a carry only when step 1 is true and the most 3537 / significant long of the longlong hrestime_adj is -1. 3538 3539.CL6: / hrestime_adj is negative 3540 movl %esi, %ecx 3541 addl max_hres_adj, %ecx 3542 movl %edx, %eax 3543 adcl $0, %eax 3544 jc .CL7 3545 xor %ecx, %ecx 3546 subl max_hres_adj, %ecx / adj = -(HRES_ADJ); 3547 movl $-1, %edx 3548 jmp .CL5 3549.CL7: 3550 movl %esi, %ecx / adj = hrestime_adj; 3551.CL5: 3552 movl timedelta, %esi 3553 subl %ecx, %esi 3554 movl timedelta+4, %eax 3555 sbbl %edx, %eax 3556 movl %esi, timedelta 3557 movl %eax, timedelta+4 / timedelta -= adj; 3558 movl %esi, hrestime_adj 3559 movl %eax, hrestime_adj+4 / hrestime_adj = timedelta; 3560 addl hrestime+4, %ecx 3561 3562 movl %ecx, %eax / eax = tv_nsec 35631: 3564 cmpl $NANOSEC, %eax / if ((unsigned long)tv_nsec >= NANOSEC) 3565 jb .CL8 / no 3566 incl one_sec / yes, one_sec++; 3567 incl hrestime / hrestime.tv_sec++; 3568 addl $-NANOSEC, %eax / tv_nsec -= NANOSEC 3569 jmp 1b / check for more seconds 3570 3571.CL8: 3572 movl %eax, hrestime+4 / store final into hrestime.tv_nsec 3573 incl hres_lock / release the hres_lock 3574 3575 popl %ebx 3576 popl %esi 3577 leave 3578 ret 3579 SET_SIZE(hres_tick) 3580 3581#endif /* __i386 */ 3582#endif /* __lint */ 3583 3584/* 3585 * void prefetch_smap_w(void *) 3586 * 3587 * Prefetch ahead within a linear list of smap structures. 3588 * Not implemented for ia32. Stub for compatibility. 3589 */ 3590 3591#if defined(__lint) 3592 3593/*ARGSUSED*/ 3594void prefetch_smap_w(void *smp) 3595{} 3596 3597#else /* __lint */ 3598 3599 ENTRY(prefetch_smap_w) 3600 rep; ret /* use 2 byte return instruction when branch target */ 3601 /* AMD Software Optimization Guide - Section 6.2 */ 3602 SET_SIZE(prefetch_smap_w) 3603 3604#endif /* __lint */ 3605 3606/* 3607 * prefetch_page_r(page_t *) 3608 * issue prefetch instructions for a page_t 3609 */ 3610#if defined(__lint) 3611 3612/*ARGSUSED*/ 3613void 3614prefetch_page_r(void *pp) 3615{} 3616 3617#else /* __lint */ 3618 3619 ENTRY(prefetch_page_r) 3620 rep; ret /* use 2 byte return instruction when branch target */ 3621 /* AMD Software Optimization Guide - Section 6.2 */ 3622 SET_SIZE(prefetch_page_r) 3623 3624#endif /* __lint */ 3625 3626#if defined(__lint) 3627 3628/*ARGSUSED*/ 3629int 3630bcmp(const void *s1, const void *s2, size_t count) 3631{ return (0); } 3632 3633#else /* __lint */ 3634 3635#if defined(__amd64) 3636 3637 ENTRY(bcmp) 3638 pushq %rbp 3639 movq %rsp, %rbp 3640#ifdef DEBUG 3641 movq kernelbase(%rip), %r11 3642 cmpq %r11, %rdi 3643 jb 0f 3644 cmpq %r11, %rsi 3645 jnb 1f 36460: leaq .bcmp_panic_msg(%rip), %rdi 3647 xorl %eax, %eax 3648 call panic 36491: 3650#endif /* DEBUG */ 3651 call memcmp 3652 testl %eax, %eax 3653 setne %dl 3654 leave 3655 movzbl %dl, %eax 3656 ret 3657 SET_SIZE(bcmp) 3658 3659#elif defined(__i386) 3660 3661#define ARG_S1 8 3662#define ARG_S2 12 3663#define ARG_LENGTH 16 3664 3665 ENTRY(bcmp) 3666#ifdef DEBUG 3667 pushl %ebp 3668 movl %esp, %ebp 3669 movl kernelbase, %eax 3670 cmpl %eax, ARG_S1(%ebp) 3671 jb 0f 3672 cmpl %eax, ARG_S2(%ebp) 3673 jnb 1f 36740: pushl $.bcmp_panic_msg 3675 call panic 36761: popl %ebp 3677#endif /* DEBUG */ 3678 3679 pushl %edi / save register variable 3680 movl ARG_S1(%esp), %eax / %eax = address of string 1 3681 movl ARG_S2(%esp), %ecx / %ecx = address of string 2 3682 cmpl %eax, %ecx / if the same string 3683 je .equal / goto .equal 3684 movl ARG_LENGTH(%esp), %edi / %edi = length in bytes 3685 cmpl $4, %edi / if %edi < 4 3686 jb .byte_check / goto .byte_check 3687 .align 4 3688.word_loop: 3689 movl (%ecx), %edx / move 1 word from (%ecx) to %edx 3690 leal -4(%edi), %edi / %edi -= 4 3691 cmpl (%eax), %edx / compare 1 word from (%eax) with %edx 3692 jne .word_not_equal / if not equal, goto .word_not_equal 3693 leal 4(%ecx), %ecx / %ecx += 4 (next word) 3694 leal 4(%eax), %eax / %eax += 4 (next word) 3695 cmpl $4, %edi / if %edi >= 4 3696 jae .word_loop / goto .word_loop 3697.byte_check: 3698 cmpl $0, %edi / if %edi == 0 3699 je .equal / goto .equal 3700 jmp .byte_loop / goto .byte_loop (checks in bytes) 3701.word_not_equal: 3702 leal 4(%edi), %edi / %edi += 4 (post-decremented) 3703 .align 4 3704.byte_loop: 3705 movb (%ecx), %dl / move 1 byte from (%ecx) to %dl 3706 cmpb %dl, (%eax) / compare %dl with 1 byte from (%eax) 3707 jne .not_equal / if not equal, goto .not_equal 3708 incl %ecx / %ecx++ (next byte) 3709 incl %eax / %eax++ (next byte) 3710 decl %edi / %edi-- 3711 jnz .byte_loop / if not zero, goto .byte_loop 3712.equal: 3713 xorl %eax, %eax / %eax = 0 3714 popl %edi / restore register variable 3715 ret / return (NULL) 3716 .align 4 3717.not_equal: 3718 movl $1, %eax / return 1 3719 popl %edi / restore register variable 3720 ret / return (NULL) 3721 SET_SIZE(bcmp) 3722 3723#endif /* __i386 */ 3724 3725#ifdef DEBUG 3726 .text 3727.bcmp_panic_msg: 3728 .string "bcmp: arguments below kernelbase" 3729#endif /* DEBUG */ 3730 3731#endif /* __lint */ 3732