1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. 29 * Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T 30 * All Rights Reserved 31 */ 32 33#pragma ident "%Z%%M% %I% %E% SMI" 34 35/* 36 * General assembly language routines. 37 * It is the intent of this file to contain routines that are 38 * independent of the specific kernel architecture, and those that are 39 * common across kernel architectures. 40 * As architectures diverge, and implementations of specific 41 * architecture-dependent routines change, the routines should be moved 42 * from this file into the respective ../`arch -k`/subr.s file. 43 */ 44 45#include <sys/asm_linkage.h> 46#include <sys/asm_misc.h> 47#include <sys/panic.h> 48#include <sys/ontrap.h> 49#include <sys/regset.h> 50#include <sys/privregs.h> 51#include <sys/reboot.h> 52#include <sys/psw.h> 53#include <sys/x86_archext.h> 54 55#if defined(__lint) 56#include <sys/types.h> 57#include <sys/systm.h> 58#include <sys/thread.h> 59#include <sys/archsystm.h> 60#include <sys/byteorder.h> 61#include <sys/dtrace.h> 62#else /* __lint */ 63#include "assym.h" 64#endif /* __lint */ 65#include <sys/dditypes.h> 66 67/* 68 * on_fault() 69 * Catch lofault faults. Like setjmp except it returns one 70 * if code following causes uncorrectable fault. Turned off 71 * by calling no_fault(). 72 */ 73 74#if defined(__lint) 75 76/* ARGSUSED */ 77int 78on_fault(label_t *ljb) 79{ return (0); } 80 81void 82no_fault(void) 83{} 84 85#else /* __lint */ 86 87#if defined(__amd64) 88 89 ENTRY(on_fault) 90 movq %gs:CPU_THREAD, %rsi 91 leaq catch_fault(%rip), %rdx 92 movq %rdi, T_ONFAULT(%rsi) /* jumpbuf in t_onfault */ 93 movq %rdx, T_LOFAULT(%rsi) /* catch_fault in t_lofault */ 94 jmp setjmp /* let setjmp do the rest */ 95 96catch_fault: 97 movq %gs:CPU_THREAD, %rsi 98 movq T_ONFAULT(%rsi), %rdi /* address of save area */ 99 xorl %eax, %eax 100 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 101 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 102 jmp longjmp /* let longjmp do the rest */ 103 SET_SIZE(on_fault) 104 105 ENTRY(no_fault) 106 movq %gs:CPU_THREAD, %rsi 107 xorl %eax, %eax 108 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 109 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 110 ret 111 SET_SIZE(no_fault) 112 113#elif defined(__i386) 114 115 ENTRY(on_fault) 116 movl %gs:CPU_THREAD, %edx 117 movl 4(%esp), %eax /* jumpbuf address */ 118 leal catch_fault, %ecx 119 movl %eax, T_ONFAULT(%edx) /* jumpbuf in t_onfault */ 120 movl %ecx, T_LOFAULT(%edx) /* catch_fault in t_lofault */ 121 jmp setjmp /* let setjmp do the rest */ 122 123catch_fault: 124 movl %gs:CPU_THREAD, %edx 125 xorl %eax, %eax 126 movl T_ONFAULT(%edx), %ecx /* address of save area */ 127 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 128 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 129 pushl %ecx 130 call longjmp /* let longjmp do the rest */ 131 SET_SIZE(on_fault) 132 133 ENTRY(no_fault) 134 movl %gs:CPU_THREAD, %edx 135 xorl %eax, %eax 136 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 137 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 138 ret 139 SET_SIZE(no_fault) 140 141#endif /* __i386 */ 142#endif /* __lint */ 143 144/* 145 * Default trampoline code for on_trap() (see <sys/ontrap.h>). We just 146 * do a longjmp(&curthread->t_ontrap->ot_jmpbuf) if this is ever called. 147 */ 148 149#if defined(lint) 150 151void 152on_trap_trampoline(void) 153{} 154 155#else /* __lint */ 156 157#if defined(__amd64) 158 159 ENTRY(on_trap_trampoline) 160 movq %gs:CPU_THREAD, %rsi 161 movq T_ONTRAP(%rsi), %rdi 162 addq $OT_JMPBUF, %rdi 163 jmp longjmp 164 SET_SIZE(on_trap_trampoline) 165 166#elif defined(__i386) 167 168 ENTRY(on_trap_trampoline) 169 movl %gs:CPU_THREAD, %eax 170 movl T_ONTRAP(%eax), %eax 171 addl $OT_JMPBUF, %eax 172 pushl %eax 173 call longjmp 174 SET_SIZE(on_trap_trampoline) 175 176#endif /* __i386 */ 177#endif /* __lint */ 178 179/* 180 * Push a new element on to the t_ontrap stack. Refer to <sys/ontrap.h> for 181 * more information about the on_trap() mechanism. If the on_trap_data is the 182 * same as the topmost stack element, we just modify that element. 183 */ 184#if defined(lint) 185 186/*ARGSUSED*/ 187int 188on_trap(on_trap_data_t *otp, uint_t prot) 189{ return (0); } 190 191#else /* __lint */ 192 193#if defined(__amd64) 194 195 ENTRY(on_trap) 196 movw %si, OT_PROT(%rdi) /* ot_prot = prot */ 197 movw $0, OT_TRAP(%rdi) /* ot_trap = 0 */ 198 leaq on_trap_trampoline(%rip), %rdx /* rdx = &on_trap_trampoline */ 199 movq %rdx, OT_TRAMPOLINE(%rdi) /* ot_trampoline = rdx */ 200 xorl %ecx, %ecx 201 movq %rcx, OT_HANDLE(%rdi) /* ot_handle = NULL */ 202 movq %rcx, OT_PAD1(%rdi) /* ot_pad1 = NULL */ 203 movq %gs:CPU_THREAD, %rdx /* rdx = curthread */ 204 movq T_ONTRAP(%rdx), %rcx /* rcx = curthread->t_ontrap */ 205 cmpq %rdi, %rcx /* if (otp == %rcx) */ 206 je 0f /* don't modify t_ontrap */ 207 208 movq %rcx, OT_PREV(%rdi) /* ot_prev = t_ontrap */ 209 movq %rdi, T_ONTRAP(%rdx) /* curthread->t_ontrap = otp */ 210 2110: addq $OT_JMPBUF, %rdi /* &ot_jmpbuf */ 212 jmp setjmp 213 SET_SIZE(on_trap) 214 215#elif defined(__i386) 216 217 ENTRY(on_trap) 218 movl 4(%esp), %eax /* %eax = otp */ 219 movl 8(%esp), %edx /* %edx = prot */ 220 221 movw %dx, OT_PROT(%eax) /* ot_prot = prot */ 222 movw $0, OT_TRAP(%eax) /* ot_trap = 0 */ 223 leal on_trap_trampoline, %edx /* %edx = &on_trap_trampoline */ 224 movl %edx, OT_TRAMPOLINE(%eax) /* ot_trampoline = %edx */ 225 movl $0, OT_HANDLE(%eax) /* ot_handle = NULL */ 226 movl $0, OT_PAD1(%eax) /* ot_pad1 = NULL */ 227 movl %gs:CPU_THREAD, %edx /* %edx = curthread */ 228 movl T_ONTRAP(%edx), %ecx /* %ecx = curthread->t_ontrap */ 229 cmpl %eax, %ecx /* if (otp == %ecx) */ 230 je 0f /* don't modify t_ontrap */ 231 232 movl %ecx, OT_PREV(%eax) /* ot_prev = t_ontrap */ 233 movl %eax, T_ONTRAP(%edx) /* curthread->t_ontrap = otp */ 234 2350: addl $OT_JMPBUF, %eax /* %eax = &ot_jmpbuf */ 236 movl %eax, 4(%esp) /* put %eax back on the stack */ 237 jmp setjmp /* let setjmp do the rest */ 238 SET_SIZE(on_trap) 239 240#endif /* __i386 */ 241#endif /* __lint */ 242 243/* 244 * Setjmp and longjmp implement non-local gotos using state vectors 245 * type label_t. 246 */ 247 248#if defined(__lint) 249 250/* ARGSUSED */ 251int 252setjmp(label_t *lp) 253{ return (0); } 254 255/* ARGSUSED */ 256void 257longjmp(label_t *lp) 258{} 259 260#else /* __lint */ 261 262#if LABEL_PC != 0 263#error LABEL_PC MUST be defined as 0 for setjmp/longjmp to work as coded 264#endif /* LABEL_PC != 0 */ 265 266#if defined(__amd64) 267 268 ENTRY(setjmp) 269 movq %rsp, LABEL_SP(%rdi) 270 movq %rbp, LABEL_RBP(%rdi) 271 movq %rbx, LABEL_RBX(%rdi) 272 movq %r12, LABEL_R12(%rdi) 273 movq %r13, LABEL_R13(%rdi) 274 movq %r14, LABEL_R14(%rdi) 275 movq %r15, LABEL_R15(%rdi) 276 movq (%rsp), %rdx /* return address */ 277 movq %rdx, (%rdi) /* LABEL_PC is 0 */ 278 xorl %eax, %eax /* return 0 */ 279 ret 280 SET_SIZE(setjmp) 281 282 ENTRY(longjmp) 283 movq LABEL_SP(%rdi), %rsp 284 movq LABEL_RBP(%rdi), %rbp 285 movq LABEL_RBX(%rdi), %rbx 286 movq LABEL_R12(%rdi), %r12 287 movq LABEL_R13(%rdi), %r13 288 movq LABEL_R14(%rdi), %r14 289 movq LABEL_R15(%rdi), %r15 290 movq (%rdi), %rdx /* return address; LABEL_PC is 0 */ 291 movq %rdx, (%rsp) 292 xorl %eax, %eax 293 incl %eax /* return 1 */ 294 ret 295 SET_SIZE(longjmp) 296 297#elif defined(__i386) 298 299 ENTRY(setjmp) 300 movl 4(%esp), %edx /* address of save area */ 301 movl %ebp, LABEL_EBP(%edx) 302 movl %ebx, LABEL_EBX(%edx) 303 movl %esi, LABEL_ESI(%edx) 304 movl %edi, LABEL_EDI(%edx) 305 movl %esp, 4(%edx) 306 movl (%esp), %ecx /* %eip (return address) */ 307 movl %ecx, (%edx) /* LABEL_PC is 0 */ 308 subl %eax, %eax /* return 0 */ 309 ret 310 SET_SIZE(setjmp) 311 312 ENTRY(longjmp) 313 movl 4(%esp), %edx /* address of save area */ 314 movl LABEL_EBP(%edx), %ebp 315 movl LABEL_EBX(%edx), %ebx 316 movl LABEL_ESI(%edx), %esi 317 movl LABEL_EDI(%edx), %edi 318 movl 4(%edx), %esp 319 movl (%edx), %ecx /* %eip (return addr); LABEL_PC is 0 */ 320 movl $1, %eax 321 addl $4, %esp /* pop ret adr */ 322 jmp *%ecx /* indirect */ 323 SET_SIZE(longjmp) 324 325#endif /* __i386 */ 326#endif /* __lint */ 327 328/* 329 * if a() calls b() calls caller(), 330 * caller() returns return address in a(). 331 * (Note: We assume a() and b() are C routines which do the normal entry/exit 332 * sequence.) 333 */ 334 335#if defined(__lint) 336 337caddr_t 338caller(void) 339{ return (0); } 340 341#else /* __lint */ 342 343#if defined(__amd64) 344 345 ENTRY(caller) 346 movq 8(%rbp), %rax /* b()'s return pc, in a() */ 347 ret 348 SET_SIZE(caller) 349 350#elif defined(__i386) 351 352 ENTRY(caller) 353 movl 4(%ebp), %eax /* b()'s return pc, in a() */ 354 ret 355 SET_SIZE(caller) 356 357#endif /* __i386 */ 358#endif /* __lint */ 359 360/* 361 * if a() calls callee(), callee() returns the 362 * return address in a(); 363 */ 364 365#if defined(__lint) 366 367caddr_t 368callee(void) 369{ return (0); } 370 371#else /* __lint */ 372 373#if defined(__amd64) 374 375 ENTRY(callee) 376 movq (%rsp), %rax /* callee()'s return pc, in a() */ 377 ret 378 SET_SIZE(callee) 379 380#elif defined(__i386) 381 382 ENTRY(callee) 383 movl (%esp), %eax /* callee()'s return pc, in a() */ 384 ret 385 SET_SIZE(callee) 386 387#endif /* __i386 */ 388#endif /* __lint */ 389 390/* 391 * return the current frame pointer 392 */ 393 394#if defined(__lint) 395 396greg_t 397getfp(void) 398{ return (0); } 399 400#else /* __lint */ 401 402#if defined(__amd64) 403 404 ENTRY(getfp) 405 movq %rbp, %rax 406 ret 407 SET_SIZE(getfp) 408 409#elif defined(__i386) 410 411 ENTRY(getfp) 412 movl %ebp, %eax 413 ret 414 SET_SIZE(getfp) 415 416#endif /* __i386 */ 417#endif /* __lint */ 418 419/* 420 * Invalidate a single page table entry in the TLB 421 */ 422 423#if defined(__lint) 424 425/* ARGSUSED */ 426void 427mmu_tlbflush_entry(caddr_t m) 428{} 429 430#else /* __lint */ 431 432#if defined(__amd64) 433 434 ENTRY(mmu_tlbflush_entry) 435 invlpg (%rdi) 436 ret 437 SET_SIZE(mmu_tlbflush_entry) 438 439#elif defined(__i386) 440 441 ENTRY(mmu_tlbflush_entry) 442 movl 4(%esp), %eax 443 invlpg (%eax) 444 ret 445 SET_SIZE(mmu_tlbflush_entry) 446 447#endif /* __i386 */ 448#endif /* __lint */ 449 450 451/* 452 * Get/Set the value of various control registers 453 */ 454 455#if defined(__lint) 456 457ulong_t 458getcr0(void) 459{ return (0); } 460 461/* ARGSUSED */ 462void 463setcr0(ulong_t value) 464{} 465 466ulong_t 467getcr2(void) 468{ return (0); } 469 470ulong_t 471getcr3(void) 472{ return (0); } 473 474/* ARGSUSED */ 475void 476setcr3(ulong_t val) 477{} 478 479void 480reload_cr3(void) 481{} 482 483ulong_t 484getcr4(void) 485{ return (0); } 486 487/* ARGSUSED */ 488void 489setcr4(ulong_t val) 490{} 491 492#if defined(__amd64) 493 494ulong_t 495getcr8(void) 496{ return (0); } 497 498/* ARGSUSED */ 499void 500setcr8(ulong_t val) 501{} 502 503#endif /* __amd64 */ 504 505#else /* __lint */ 506 507#if defined(__amd64) 508 509 ENTRY(getcr0) 510 movq %cr0, %rax 511 ret 512 SET_SIZE(getcr0) 513 514 ENTRY(setcr0) 515 movq %rdi, %cr0 516 ret 517 SET_SIZE(setcr0) 518 519 ENTRY(getcr2) 520 movq %cr2, %rax 521 ret 522 SET_SIZE(getcr2) 523 524 ENTRY(getcr3) 525 movq %cr3, %rax 526 ret 527 SET_SIZE(getcr3) 528 529 ENTRY(setcr3) 530 movq %rdi, %cr3 531 ret 532 SET_SIZE(setcr3) 533 534 ENTRY(reload_cr3) 535 movq %cr3, %rdi 536 movq %rdi, %cr3 537 ret 538 SET_SIZE(reload_cr3) 539 540 ENTRY(getcr4) 541 movq %cr4, %rax 542 ret 543 SET_SIZE(getcr4) 544 545 ENTRY(setcr4) 546 movq %rdi, %cr4 547 ret 548 SET_SIZE(setcr4) 549 550 ENTRY(getcr8) 551 movq %cr8, %rax 552 ret 553 SET_SIZE(getcr8) 554 555 ENTRY(setcr8) 556 movq %rdi, %cr8 557 ret 558 SET_SIZE(setcr8) 559 560#elif defined(__i386) 561 562 ENTRY(getcr0) 563 movl %cr0, %eax 564 ret 565 SET_SIZE(getcr0) 566 567 ENTRY(setcr0) 568 movl 4(%esp), %eax 569 movl %eax, %cr0 570 ret 571 SET_SIZE(setcr0) 572 573 ENTRY(getcr2) 574 movl %cr2, %eax 575 ret 576 SET_SIZE(getcr2) 577 578 ENTRY(getcr3) 579 movl %cr3, %eax 580 ret 581 SET_SIZE(getcr3) 582 583 ENTRY(setcr3) 584 movl 4(%esp), %eax 585 movl %eax, %cr3 586 ret 587 SET_SIZE(setcr3) 588 589 ENTRY(reload_cr3) 590 movl %cr3, %eax 591 movl %eax, %cr3 592 ret 593 SET_SIZE(reload_cr3) 594 595 ENTRY(getcr4) 596 movl %cr4, %eax 597 ret 598 SET_SIZE(getcr4) 599 600 ENTRY(setcr4) 601 movl 4(%esp), %eax 602 movl %eax, %cr4 603 ret 604 SET_SIZE(setcr4) 605 606#endif /* __i386 */ 607#endif /* __lint */ 608 609#if defined(__lint) 610 611/*ARGSUSED*/ 612uint32_t 613__cpuid_insn(uint32_t eax, uint32_t *ebxp, uint32_t *ecxp, uint32_t *edxp) 614{ return (0); } 615 616#else /* __lint */ 617 618#if defined(__amd64) 619 620 ENTRY(__cpuid_insn) 621 movq %rbx, %r11 622 movq %rdx, %r8 /* r8 = ecxp */ 623 movq %rcx, %r9 /* r9 = edxp */ 624 movl %edi, %eax 625 cpuid 626 movl %ebx, (%rsi) 627 movl %ecx, (%r8) 628 movl %edx, (%r9) 629 movq %r11, %rbx 630 ret 631 SET_SIZE(__cpuid_insn) 632 633#elif defined(__i386) 634 635 ENTRY(__cpuid_insn) 636 pushl %ebp 637 movl %esp, %ebp 638 pushl %ebx 639 movl 8(%ebp), %eax 640 cpuid 641 pushl %eax 642 movl 0x0c(%ebp), %eax 643 movl %ebx, (%eax) 644 movl 0x10(%ebp), %eax 645 movl %ecx, (%eax) 646 movl 0x14(%ebp), %eax 647 movl %edx, (%eax) 648 popl %eax 649 popl %ebx 650 popl %ebp 651 ret 652 SET_SIZE(__cpuid_insn) 653 654#endif /* __i386 */ 655#endif /* __lint */ 656 657/* 658 * Insert entryp after predp in a doubly linked list. 659 */ 660 661#if defined(__lint) 662 663/*ARGSUSED*/ 664void 665_insque(caddr_t entryp, caddr_t predp) 666{} 667 668#else /* __lint */ 669 670#if defined(__amd64) 671 672 ENTRY(_insque) 673 movq (%rsi), %rax /* predp->forw */ 674 movq %rsi, CPTRSIZE(%rdi) /* entryp->back = predp */ 675 movq %rax, (%rdi) /* entryp->forw = predp->forw */ 676 movq %rdi, (%rsi) /* predp->forw = entryp */ 677 movq %rdi, CPTRSIZE(%rax) /* predp->forw->back = entryp */ 678 ret 679 SET_SIZE(_insque) 680 681#elif defined(__i386) 682 683 ENTRY(_insque) 684 movl 8(%esp), %edx 685 movl 4(%esp), %ecx 686 movl (%edx), %eax /* predp->forw */ 687 movl %edx, CPTRSIZE(%ecx) /* entryp->back = predp */ 688 movl %eax, (%ecx) /* entryp->forw = predp->forw */ 689 movl %ecx, (%edx) /* predp->forw = entryp */ 690 movl %ecx, CPTRSIZE(%eax) /* predp->forw->back = entryp */ 691 ret 692 SET_SIZE(_insque) 693 694#endif /* __i386 */ 695#endif /* __lint */ 696 697/* 698 * Remove entryp from a doubly linked list 699 */ 700 701#if defined(__lint) 702 703/*ARGSUSED*/ 704void 705_remque(caddr_t entryp) 706{} 707 708#else /* __lint */ 709 710#if defined(__amd64) 711 712 ENTRY(_remque) 713 movq (%rdi), %rax /* entry->forw */ 714 movq CPTRSIZE(%rdi), %rdx /* entry->back */ 715 movq %rax, (%rdx) /* entry->back->forw = entry->forw */ 716 movq %rdx, CPTRSIZE(%rax) /* entry->forw->back = entry->back */ 717 ret 718 SET_SIZE(_remque) 719 720#elif defined(__i386) 721 722 ENTRY(_remque) 723 movl 4(%esp), %ecx 724 movl (%ecx), %eax /* entry->forw */ 725 movl CPTRSIZE(%ecx), %edx /* entry->back */ 726 movl %eax, (%edx) /* entry->back->forw = entry->forw */ 727 movl %edx, CPTRSIZE(%eax) /* entry->forw->back = entry->back */ 728 ret 729 SET_SIZE(_remque) 730 731#endif /* __i386 */ 732#endif /* __lint */ 733 734/* 735 * Returns the number of 736 * non-NULL bytes in string argument. 737 */ 738 739#if defined(__lint) 740 741/* ARGSUSED */ 742size_t 743strlen(const char *str) 744{ return (0); } 745 746#else /* __lint */ 747 748#if defined(__amd64) 749 750/* 751 * This is close to a simple transliteration of a C version of this 752 * routine. We should either just -make- this be a C version, or 753 * justify having it in assembler by making it significantly faster. 754 * 755 * size_t 756 * strlen(const char *s) 757 * { 758 * const char *s0; 759 * #if defined(DEBUG) 760 * if ((uintptr_t)s < KERNELBASE) 761 * panic(.str_panic_msg); 762 * #endif 763 * for (s0 = s; *s; s++) 764 * ; 765 * return (s - s0); 766 * } 767 */ 768 769 ENTRY(strlen) 770#ifdef DEBUG 771 movq kernelbase(%rip), %rax 772 cmpq %rax, %rdi 773 jae str_valid 774 pushq %rbp 775 movq %rsp, %rbp 776 leaq .str_panic_msg(%rip), %rdi 777 xorl %eax, %eax 778 call panic 779#endif /* DEBUG */ 780str_valid: 781 cmpb $0, (%rdi) 782 movq %rdi, %rax 783 je .null_found 784 .align 4 785.strlen_loop: 786 incq %rdi 787 cmpb $0, (%rdi) 788 jne .strlen_loop 789.null_found: 790 subq %rax, %rdi 791 movq %rdi, %rax 792 ret 793 SET_SIZE(strlen) 794 795#elif defined(__i386) 796 797 ENTRY(strlen) 798#ifdef DEBUG 799 movl kernelbase, %eax 800 cmpl %eax, 4(%esp) 801 jae str_valid 802 pushl %ebp 803 movl %esp, %ebp 804 pushl $.str_panic_msg 805 call panic 806#endif /* DEBUG */ 807 808str_valid: 809 movl 4(%esp), %eax /* %eax = string address */ 810 testl $3, %eax /* if %eax not word aligned */ 811 jnz .not_word_aligned /* goto .not_word_aligned */ 812 .align 4 813.word_aligned: 814 movl (%eax), %edx /* move 1 word from (%eax) to %edx */ 815 movl $0x7f7f7f7f, %ecx 816 andl %edx, %ecx /* %ecx = %edx & 0x7f7f7f7f */ 817 addl $4, %eax /* next word */ 818 addl $0x7f7f7f7f, %ecx /* %ecx += 0x7f7f7f7f */ 819 orl %edx, %ecx /* %ecx |= %edx */ 820 andl $0x80808080, %ecx /* %ecx &= 0x80808080 */ 821 cmpl $0x80808080, %ecx /* if no null byte in this word */ 822 je .word_aligned /* goto .word_aligned */ 823 subl $4, %eax /* post-incremented */ 824.not_word_aligned: 825 cmpb $0, (%eax) /* if a byte in (%eax) is null */ 826 je .null_found /* goto .null_found */ 827 incl %eax /* next byte */ 828 testl $3, %eax /* if %eax not word aligned */ 829 jnz .not_word_aligned /* goto .not_word_aligned */ 830 jmp .word_aligned /* goto .word_aligned */ 831 .align 4 832.null_found: 833 subl 4(%esp), %eax /* %eax -= string address */ 834 ret 835 SET_SIZE(strlen) 836 837#endif /* __i386 */ 838 839#ifdef DEBUG 840 .text 841.str_panic_msg: 842 .string "strlen: argument below kernelbase" 843#endif /* DEBUG */ 844 845#endif /* __lint */ 846 847 /* 848 * Berkley 4.3 introduced symbolically named interrupt levels 849 * as a way deal with priority in a machine independent fashion. 850 * Numbered priorities are machine specific, and should be 851 * discouraged where possible. 852 * 853 * Note, for the machine specific priorities there are 854 * examples listed for devices that use a particular priority. 855 * It should not be construed that all devices of that 856 * type should be at that priority. It is currently were 857 * the current devices fit into the priority scheme based 858 * upon time criticalness. 859 * 860 * The underlying assumption of these assignments is that 861 * IPL 10 is the highest level from which a device 862 * routine can call wakeup. Devices that interrupt from higher 863 * levels are restricted in what they can do. If they need 864 * kernels services they should schedule a routine at a lower 865 * level (via software interrupt) to do the required 866 * processing. 867 * 868 * Examples of this higher usage: 869 * Level Usage 870 * 14 Profiling clock (and PROM uart polling clock) 871 * 12 Serial ports 872 * 873 * The serial ports request lower level processing on level 6. 874 * 875 * Also, almost all splN routines (where N is a number or a 876 * mnemonic) will do a RAISE(), on the assumption that they are 877 * never used to lower our priority. 878 * The exceptions are: 879 * spl8() Because you can't be above 15 to begin with! 880 * splzs() Because this is used at boot time to lower our 881 * priority, to allow the PROM to poll the uart. 882 * spl0() Used to lower priority to 0. 883 */ 884 885#if defined(__lint) 886 887int spl0(void) { return (0); } 888int spl6(void) { return (0); } 889int spl7(void) { return (0); } 890int spl8(void) { return (0); } 891int splhigh(void) { return (0); } 892int splhi(void) { return (0); } 893int splzs(void) { return (0); } 894 895#else /* __lint */ 896 897/* reg = cpu->cpu_m.cpu_pri; */ 898#define GETIPL_NOGS(reg, cpup) \ 899 movl CPU_PRI(cpup), reg; 900 901/* cpu->cpu_m.cpu_pri; */ 902#define SETIPL_NOGS(val, cpup) \ 903 movl val, CPU_PRI(cpup); 904 905/* reg = cpu->cpu_m.cpu_pri; */ 906#define GETIPL(reg) \ 907 movl %gs:CPU_PRI, reg; 908 909/* cpu->cpu_m.cpu_pri; */ 910#define SETIPL(val) \ 911 movl val, %gs:CPU_PRI; 912 913/* 914 * Macro to raise processor priority level. 915 * Avoid dropping processor priority if already at high level. 916 * Also avoid going below CPU->cpu_base_spl, which could've just been set by 917 * a higher-level interrupt thread that just blocked. 918 */ 919#if defined(__amd64) 920 921#define RAISE(level) \ 922 cli; \ 923 LOADCPU(%rcx); \ 924 movl $/**/level, %edi;\ 925 GETIPL_NOGS(%eax, %rcx);\ 926 cmpl %eax, %edi; \ 927 jg spl; \ 928 jmp setsplhisti 929 930#elif defined(__i386) 931 932#define RAISE(level) \ 933 cli; \ 934 LOADCPU(%ecx); \ 935 movl $/**/level, %edx;\ 936 GETIPL_NOGS(%eax, %ecx);\ 937 cmpl %eax, %edx; \ 938 jg spl; \ 939 jmp setsplhisti 940 941#endif /* __i386 */ 942 943/* 944 * Macro to set the priority to a specified level. 945 * Avoid dropping the priority below CPU->cpu_base_spl. 946 */ 947#if defined(__amd64) 948 949#define SETPRI(level) \ 950 cli; \ 951 LOADCPU(%rcx); \ 952 movl $/**/level, %edi; \ 953 jmp spl 954 955#elif defined(__i386) 956 957#define SETPRI(level) \ 958 cli; \ 959 LOADCPU(%ecx); \ 960 movl $/**/level, %edx; \ 961 jmp spl 962 963#endif /* __i386 */ 964 965 /* locks out all interrupts, including memory errors */ 966 ENTRY(spl8) 967 SETPRI(15) 968 SET_SIZE(spl8) 969 970 /* just below the level that profiling runs */ 971 ENTRY(spl7) 972 RAISE(13) 973 SET_SIZE(spl7) 974 975 /* sun specific - highest priority onboard serial i/o asy ports */ 976 ENTRY(splzs) 977 SETPRI(12) /* Can't be a RAISE, as it's used to lower us */ 978 SET_SIZE(splzs) 979 980 /* 981 * should lock out clocks and all interrupts, 982 * as you can see, there are exceptions 983 */ 984 985#if defined(__amd64) 986 987 .align 16 988 ENTRY(splhi) 989 ALTENTRY(splhigh) 990 ALTENTRY(spl6) 991 ALTENTRY(i_ddi_splhigh) 992 cli 993 LOADCPU(%rcx) 994 movl $DISP_LEVEL, %edi 995 movl CPU_PRI(%rcx), %eax 996 cmpl %eax, %edi 997 jle setsplhisti 998 SETIPL_NOGS(%edi, %rcx) 999 /* 1000 * If we aren't using cr8 to control ipl then we patch this 1001 * with a jump to slow_setsplhi 1002 */ 1003 ALTENTRY(setsplhi_patch) 1004 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1005 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1006 movq %rdx, %cr8 /* set new apic priority */ 1007 /* 1008 * enable interrupts 1009 */ 1010setsplhisti: 1011 nop /* patch this to a sti when a proper setspl routine appears */ 1012 ret 1013 1014 ALTENTRY(slow_setsplhi) 1015 pushq %rbp 1016 movq %rsp, %rbp 1017 subq $16, %rsp 1018 movl %eax, -4(%rbp) /* save old ipl */ 1019 call *setspl(%rip) 1020 movl -4(%rbp), %eax /* return old ipl */ 1021 leave 1022 jmp setsplhisti 1023 1024 SET_SIZE(i_ddi_splhigh) 1025 SET_SIZE(spl6) 1026 SET_SIZE(splhigh) 1027 SET_SIZE(splhi) 1028 1029#elif defined(__i386) 1030 1031 .align 16 1032 ENTRY(splhi) 1033 ALTENTRY(splhigh) 1034 ALTENTRY(spl6) 1035 ALTENTRY(i_ddi_splhigh) 1036 cli 1037 LOADCPU(%ecx) 1038 movl $DISP_LEVEL, %edx 1039 movl CPU_PRI(%ecx), %eax 1040 cmpl %eax, %edx 1041 jle setsplhisti 1042 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1043 1044 pushl %eax /* save old ipl */ 1045 pushl %edx /* pass new ipl */ 1046 call *setspl 1047 popl %ecx /* dummy pop */ 1048 popl %eax /* return old ipl */ 1049 /* 1050 * enable interrupts 1051 * 1052 * (we patch this to an sti once a proper setspl routine 1053 * is installed) 1054 */ 1055setsplhisti: 1056 nop /* patch this to a sti when a proper setspl routine appears */ 1057 ret 1058 SET_SIZE(i_ddi_splhigh) 1059 SET_SIZE(spl6) 1060 SET_SIZE(splhigh) 1061 SET_SIZE(splhi) 1062 1063#endif /* __i386 */ 1064 1065 /* allow all interrupts */ 1066 ENTRY(spl0) 1067 SETPRI(0) 1068 SET_SIZE(spl0) 1069 1070#endif /* __lint */ 1071 1072/* 1073 * splr is like splx but will only raise the priority and never drop it 1074 */ 1075#if defined(__lint) 1076 1077/* ARGSUSED */ 1078int 1079splr(int level) 1080{ return (0); } 1081 1082#else /* __lint */ 1083 1084#if defined(__amd64) 1085 1086 ENTRY(splr) 1087 cli 1088 LOADCPU(%rcx) 1089 GETIPL_NOGS(%eax, %rcx) 1090 cmpl %eax, %edi /* if new level > current level */ 1091 jg spl /* then set ipl to new level */ 1092splr_setsti: 1093 nop /* patch this to a sti when a proper setspl routine appears */ 1094 ret /* else return the current level */ 1095 SET_SIZE(splr) 1096 1097#elif defined(__i386) 1098 1099 ENTRY(splr) 1100 cli 1101 LOADCPU(%ecx) 1102 movl 4(%esp), %edx /* get new spl level */ 1103 GETIPL_NOGS(%eax, %ecx) 1104 cmpl %eax, %edx /* if new level > current level */ 1105 jg spl /* then set ipl to new level */ 1106splr_setsti: 1107 nop /* patch this to a sti when a proper setspl routine appears */ 1108 ret /* else return the current level */ 1109 SET_SIZE(splr) 1110 1111#endif /* __i386 */ 1112#endif /* __lint */ 1113 1114 1115 1116/* 1117 * splx - set PIL back to that indicated by the level passed as an argument, 1118 * or to the CPU's base priority, whichever is higher. 1119 * Needs to be fall through to spl to save cycles. 1120 * Algorithm for spl: 1121 * 1122 * turn off interrupts 1123 * 1124 * if (CPU->cpu_base_spl > newipl) 1125 * newipl = CPU->cpu_base_spl; 1126 * oldipl = CPU->cpu_pridata->c_ipl; 1127 * CPU->cpu_pridata->c_ipl = newipl; 1128 * 1129 * /indirectly call function to set spl values (usually setpicmasks) 1130 * setspl(); // load new masks into pics 1131 * 1132 * Be careful not to set priority lower than CPU->cpu_base_pri, 1133 * even though it seems we're raising the priority, it could be set 1134 * higher at any time by an interrupt routine, so we must block interrupts 1135 * and look at CPU->cpu_base_pri 1136 */ 1137#if defined(__lint) 1138 1139/* ARGSUSED */ 1140void 1141splx(int level) 1142{} 1143 1144#else /* __lint */ 1145 1146#if defined(__amd64) 1147 1148 ENTRY(splx) 1149 ALTENTRY(i_ddi_splx) 1150 cli /* disable interrupts */ 1151 LOADCPU(%rcx) 1152 /*FALLTHRU*/ 1153 .align 4 1154spl: 1155 /* 1156 * New priority level is in %edi, cpu struct pointer is in %rcx 1157 */ 1158 GETIPL_NOGS(%eax, %rcx) /* get current ipl */ 1159 cmpl %edi, CPU_BASE_SPL(%rcx) /* if (base spl > new ipl) */ 1160 ja set_to_base_spl /* then use base_spl */ 1161 1162setprilev: 1163 SETIPL_NOGS(%edi, %rcx) /* set new ipl */ 1164 /* 1165 * If we aren't using cr8 to control ipl then we patch this 1166 * with a jump to slow_spl 1167 */ 1168 ALTENTRY(spl_patch) 1169 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1170 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1171 movq %rdx, %cr8 /* set new apic priority */ 1172 xorl %edx, %edx 1173 bsrl CPU_SOFTINFO(%rcx), %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1174 cmpl %edi, %edx /* new ipl vs. st_pending */ 1175 jle setsplsti 1176 1177 pushq %rbp 1178 movq %rsp, %rbp 1179 /* stack now 16-byte aligned */ 1180 pushq %rax /* save old spl */ 1181 pushq %rdi /* save new ipl too */ 1182 jmp fakesoftint 1183 1184setsplsti: 1185 nop /* patch this to a sti when a proper setspl routine appears */ 1186 ret 1187 1188 ALTENTRY(slow_spl) 1189 pushq %rbp 1190 movq %rsp, %rbp 1191 /* stack now 16-byte aligned */ 1192 1193 pushq %rax /* save old spl */ 1194 pushq %rdi /* save new ipl too */ 1195 1196 call *setspl(%rip) 1197 1198 LOADCPU(%rcx) 1199 movl CPU_SOFTINFO(%rcx), %eax 1200 orl %eax, %eax 1201 jz slow_setsplsti 1202 1203 bsrl %eax, %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1204 cmpl 0(%rsp), %edx /* new ipl vs. st_pending */ 1205 jg fakesoftint 1206 1207 ALTENTRY(fakesoftint_return) 1208 /* 1209 * enable interrupts 1210 */ 1211slow_setsplsti: 1212 nop /* patch this to a sti when a proper setspl routine appears */ 1213 popq %rdi 1214 popq %rax /* return old ipl */ 1215 leave 1216 ret 1217 SET_SIZE(fakesoftint_return) 1218 1219set_to_base_spl: 1220 movl CPU_BASE_SPL(%rcx), %edi 1221 jmp setprilev 1222 SET_SIZE(spl) 1223 SET_SIZE(i_ddi_splx) 1224 SET_SIZE(splx) 1225 1226#elif defined(__i386) 1227 1228 ENTRY(splx) 1229 ALTENTRY(i_ddi_splx) 1230 cli /* disable interrupts */ 1231 LOADCPU(%ecx) 1232 movl 4(%esp), %edx /* get new spl level */ 1233 /*FALLTHRU*/ 1234 1235 .align 4 1236 ALTENTRY(spl) 1237 /* 1238 * New priority level is in %edx 1239 * (doing this early to avoid an AGI in the next instruction) 1240 */ 1241 GETIPL_NOGS(%eax, %ecx) /* get current ipl */ 1242 cmpl %edx, CPU_BASE_SPL(%ecx) /* if ( base spl > new ipl) */ 1243 ja set_to_base_spl /* then use base_spl */ 1244 1245setprilev: 1246 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1247 1248 pushl %eax /* save old ipl */ 1249 pushl %edx /* pass new ipl */ 1250 call *setspl 1251 1252 LOADCPU(%ecx) 1253 movl CPU_SOFTINFO(%ecx), %eax 1254 orl %eax, %eax 1255 jz setsplsti 1256 1257 /* 1258 * Before dashing off, check that setsplsti has been patched. 1259 */ 1260 cmpl $NOP_INSTR, setsplsti 1261 je setsplsti 1262 1263 bsrl %eax, %edx 1264 cmpl 0(%esp), %edx 1265 jg fakesoftint 1266 1267 ALTENTRY(fakesoftint_return) 1268 /* 1269 * enable interrupts 1270 */ 1271setsplsti: 1272 nop /* patch this to a sti when a proper setspl routine appears */ 1273 popl %eax 1274 popl %eax / return old ipl 1275 ret 1276 SET_SIZE(fakesoftint_return) 1277 1278set_to_base_spl: 1279 movl CPU_BASE_SPL(%ecx), %edx 1280 jmp setprilev 1281 SET_SIZE(spl) 1282 SET_SIZE(i_ddi_splx) 1283 SET_SIZE(splx) 1284 1285#endif /* __i386 */ 1286#endif /* __lint */ 1287 1288#if defined(__lint) 1289 1290void 1291install_spl(void) 1292{} 1293 1294#else /* __lint */ 1295 1296#if defined(__amd64) 1297 1298 ENTRY_NP(install_spl) 1299 movq %cr0, %rax 1300 movq %rax, %rdx 1301 movl $_BITNOT(CR0_WP), %ecx 1302 movslq %ecx, %rcx 1303 andq %rcx, %rax /* we don't want to take a fault */ 1304 movq %rax, %cr0 1305 jmp 1f 13061: movb $STI_INSTR, setsplsti(%rip) 1307 movb $STI_INSTR, slow_setsplsti(%rip) 1308 movb $STI_INSTR, setsplhisti(%rip) 1309 movb $STI_INSTR, splr_setsti(%rip) 1310 testl $1, intpri_use_cr8(%rip) /* are using %cr8 ? */ 1311 jz 2f /* no, go patch more */ 1312 movq %rdx, %cr0 1313 ret 13142: 1315 /* 1316 * Patch spl functions to use slow spl method 1317 */ 1318 leaq setsplhi_patch(%rip), %rdi /* get patch point addr */ 1319 leaq slow_setsplhi(%rip), %rax /* jmp target */ 1320 subq %rdi, %rax /* calculate jmp distance */ 1321 subq $2, %rax /* minus size of jmp instr */ 1322 shlq $8, %rax /* construct jmp instr */ 1323 addq $JMP_INSTR, %rax 1324 movw %ax, setsplhi_patch(%rip) /* patch in the jmp */ 1325 leaq spl_patch(%rip), %rdi /* get patch point addr */ 1326 leaq slow_spl(%rip), %rax /* jmp target */ 1327 subq %rdi, %rax /* calculate jmp distance */ 1328 subq $2, %rax /* minus size of jmp instr */ 1329 shlq $8, %rax /* construct jmp instr */ 1330 addq $JMP_INSTR, %rax 1331 movw %ax, spl_patch(%rip) /* patch in the jmp */ 1332 /* 1333 * Ensure %cr8 is zero since we aren't using it 1334 */ 1335 xorl %eax, %eax 1336 movq %rax, %cr8 1337 movq %rdx, %cr0 1338 ret 1339 SET_SIZE(install_spl) 1340 1341#elif defined(__i386) 1342 1343 ENTRY_NP(install_spl) 1344 movl %cr0, %eax 1345 movl %eax, %edx 1346 andl $_BITNOT(CR0_WP), %eax /* we don't want to take a fault */ 1347 movl %eax, %cr0 1348 jmp 1f 13491: movb $STI_INSTR, setsplsti 1350 movb $STI_INSTR, setsplhisti 1351 movb $STI_INSTR, splr_setsti 1352 movl %edx, %cr0 1353 ret 1354 SET_SIZE(install_spl) 1355 1356#endif /* __i386 */ 1357#endif /* __lint */ 1358 1359 1360/* 1361 * Get current processor interrupt level 1362 */ 1363 1364#if defined(__lint) 1365 1366int 1367getpil(void) 1368{ return (0); } 1369 1370#else /* __lint */ 1371 1372#if defined(__amd64) 1373 1374 ENTRY(getpil) 1375 GETIPL(%eax) /* priority level into %eax */ 1376 ret 1377 SET_SIZE(getpil) 1378 1379#elif defined(__i386) 1380 1381 ENTRY(getpil) 1382 GETIPL(%eax) /* priority level into %eax */ 1383 ret 1384 SET_SIZE(getpil) 1385 1386#endif /* __i386 */ 1387#endif /* __lint */ 1388 1389#if defined(__i386) 1390 1391/* 1392 * Read and write the %gs register 1393 */ 1394 1395#if defined(__lint) 1396 1397/*ARGSUSED*/ 1398uint16_t 1399getgs(void) 1400{ return (0); } 1401 1402/*ARGSUSED*/ 1403void 1404setgs(uint16_t sel) 1405{} 1406 1407#else /* __lint */ 1408 1409 ENTRY(getgs) 1410 clr %eax 1411 movw %gs, %ax 1412 ret 1413 SET_SIZE(getgs) 1414 1415 ENTRY(setgs) 1416 movw 4(%esp), %gs 1417 ret 1418 SET_SIZE(setgs) 1419 1420#endif /* __lint */ 1421#endif /* __i386 */ 1422 1423#if defined(__lint) 1424 1425void 1426pc_reset(void) 1427{} 1428 1429#else /* __lint */ 1430 1431 ENTRY(pc_reset) 1432 / 1433 / Try the classic keyboard controller-triggered reset. 1434 / 1435 movw $0x64, %dx 1436 movb $0xfe, %al 1437 outb (%dx) 1438 1439 / 1440 / Try port 0x92 fast reset 1441 / 1442 movw $0x92, %dx 1443 inb (%dx) 1444 cmpb $0xff, %al / If port's not there, we should get back 0xFF 1445 je 1f 1446 testb $1, %al / If bit 0 1447 jz 2f / is clear, jump to perform the reset 1448 andb $0xfe, %al / otherwise, 1449 outb (%dx) / clear bit 0 first, then 14502: 1451 orb $1, %al / Set bit 0 1452 outb (%dx) / and reset the system 14531: 1454 1455 / Try the PCI (soft) reset vector (should work on all modern systems, 1456 / but has been shown to cause problems on 450NX systems, and some newer 1457 / systems (e.g. ATI IXP400-equipped systems)) 1458 / When resetting via this method, 2 writes are required. The first 1459 / targets bit 1 (0=hard reset without power cycle, 1=hard reset with 1460 / power cycle). 1461 / The reset occurs on the second write, during bit 2's transition from 1462 / 0->1. 1463 movw $0xcf9, %dx 1464 movb $0x2, %al / Reset mode = hard, no power cycle 1465 outb (%dx) 1466 movb $0x6, %al 1467 outb (%dx) 1468 1469 / 1470 / port 0xcf9 failed also. Last-ditch effort is to 1471 / triple-fault the CPU. 1472 / 1473#if defined(__amd64) 1474 pushq $0x0 1475 pushq $0x0 / IDT base of 0, limit of 0 + 2 unused bytes 1476 lidt (%rsp) 1477#elif defined(__i386) 1478 pushl $0x0 1479 pushl $0x0 / IDT base of 0, limit of 0 + 2 unused bytes 1480 lidt (%esp) 1481#endif 1482 int $0x0 / Trigger interrupt, generate triple-fault 1483 hlt 1484 /*NOTREACHED*/ 1485 SET_SIZE(pc_reset) 1486 1487#endif /* __lint */ 1488 1489/* 1490 * C callable in and out routines 1491 */ 1492 1493#if defined(__lint) 1494 1495/* ARGSUSED */ 1496void 1497outl(int port_address, uint32_t val) 1498{} 1499 1500#else /* __lint */ 1501 1502#if defined(__amd64) 1503 1504 ENTRY(outl) 1505 movw %di, %dx 1506 movl %esi, %eax 1507 outl (%dx) 1508 ret 1509 SET_SIZE(outl) 1510 1511#elif defined(__i386) 1512 1513 .set PORT, 4 1514 .set VAL, 8 1515 1516 ENTRY(outl) 1517 movw PORT(%esp), %dx 1518 movl VAL(%esp), %eax 1519 outl (%dx) 1520 ret 1521 SET_SIZE(outl) 1522 1523#endif /* __i386 */ 1524#endif /* __lint */ 1525 1526#if defined(__lint) 1527 1528/* ARGSUSED */ 1529void 1530outw(int port_address, uint16_t val) 1531{} 1532 1533#else /* __lint */ 1534 1535#if defined(__amd64) 1536 1537 ENTRY(outw) 1538 movw %di, %dx 1539 movw %si, %ax 1540 D16 outl (%dx) /* XX64 why not outw? */ 1541 ret 1542 SET_SIZE(outw) 1543 1544#elif defined(__i386) 1545 1546 ENTRY(outw) 1547 movw PORT(%esp), %dx 1548 movw VAL(%esp), %ax 1549 D16 outl (%dx) 1550 ret 1551 SET_SIZE(outw) 1552 1553#endif /* __i386 */ 1554#endif /* __lint */ 1555 1556#if defined(__lint) 1557 1558/* ARGSUSED */ 1559void 1560outb(int port_address, uint8_t val) 1561{} 1562 1563#else /* __lint */ 1564 1565#if defined(__amd64) 1566 1567 ENTRY(outb) 1568 movw %di, %dx 1569 movb %sil, %al 1570 outb (%dx) 1571 ret 1572 SET_SIZE(outb) 1573 1574#elif defined(__i386) 1575 1576 ENTRY(outb) 1577 movw PORT(%esp), %dx 1578 movb VAL(%esp), %al 1579 outb (%dx) 1580 ret 1581 SET_SIZE(outb) 1582 1583#endif /* __i386 */ 1584#endif /* __lint */ 1585 1586#if defined(__lint) 1587 1588/* ARGSUSED */ 1589uint32_t 1590inl(int port_address) 1591{ return (0); } 1592 1593#else /* __lint */ 1594 1595#if defined(__amd64) 1596 1597 ENTRY(inl) 1598 xorl %eax, %eax 1599 movw %di, %dx 1600 inl (%dx) 1601 ret 1602 SET_SIZE(inl) 1603 1604#elif defined(__i386) 1605 1606 ENTRY(inl) 1607 movw PORT(%esp), %dx 1608 inl (%dx) 1609 ret 1610 SET_SIZE(inl) 1611 1612#endif /* __i386 */ 1613#endif /* __lint */ 1614 1615#if defined(__lint) 1616 1617/* ARGSUSED */ 1618uint16_t 1619inw(int port_address) 1620{ return (0); } 1621 1622#else /* __lint */ 1623 1624#if defined(__amd64) 1625 1626 ENTRY(inw) 1627 xorl %eax, %eax 1628 movw %di, %dx 1629 D16 inl (%dx) 1630 ret 1631 SET_SIZE(inw) 1632 1633#elif defined(__i386) 1634 1635 ENTRY(inw) 1636 subl %eax, %eax 1637 movw PORT(%esp), %dx 1638 D16 inl (%dx) 1639 ret 1640 SET_SIZE(inw) 1641 1642#endif /* __i386 */ 1643#endif /* __lint */ 1644 1645 1646#if defined(__lint) 1647 1648/* ARGSUSED */ 1649uint8_t 1650inb(int port_address) 1651{ return (0); } 1652 1653#else /* __lint */ 1654 1655#if defined(__amd64) 1656 1657 ENTRY(inb) 1658 xorl %eax, %eax 1659 movw %di, %dx 1660 inb (%dx) 1661 ret 1662 SET_SIZE(inb) 1663 1664#elif defined(__i386) 1665 1666 ENTRY(inb) 1667 subl %eax, %eax 1668 movw PORT(%esp), %dx 1669 inb (%dx) 1670 ret 1671 SET_SIZE(inb) 1672 1673#endif /* __i386 */ 1674#endif /* __lint */ 1675 1676 1677#if defined(__lint) 1678 1679/* ARGSUSED */ 1680void 1681repoutsw(int port, uint16_t *addr, int cnt) 1682{} 1683 1684#else /* __lint */ 1685 1686#if defined(__amd64) 1687 1688 ENTRY(repoutsw) 1689 movl %edx, %ecx 1690 movw %di, %dx 1691 rep 1692 D16 outsl 1693 ret 1694 SET_SIZE(repoutsw) 1695 1696#elif defined(__i386) 1697 1698 /* 1699 * The arguments and saved registers are on the stack in the 1700 * following order: 1701 * | cnt | +16 1702 * | *addr | +12 1703 * | port | +8 1704 * | eip | +4 1705 * | esi | <-- %esp 1706 * If additional values are pushed onto the stack, make sure 1707 * to adjust the following constants accordingly. 1708 */ 1709 .set PORT, 8 1710 .set ADDR, 12 1711 .set COUNT, 16 1712 1713 ENTRY(repoutsw) 1714 pushl %esi 1715 movl PORT(%esp), %edx 1716 movl ADDR(%esp), %esi 1717 movl COUNT(%esp), %ecx 1718 rep 1719 D16 outsl 1720 popl %esi 1721 ret 1722 SET_SIZE(repoutsw) 1723 1724#endif /* __i386 */ 1725#endif /* __lint */ 1726 1727 1728#if defined(__lint) 1729 1730/* ARGSUSED */ 1731void 1732repinsw(int port_addr, uint16_t *addr, int cnt) 1733{} 1734 1735#else /* __lint */ 1736 1737#if defined(__amd64) 1738 1739 ENTRY(repinsw) 1740 movl %edx, %ecx 1741 movw %di, %dx 1742 rep 1743 D16 insl 1744 ret 1745 SET_SIZE(repinsw) 1746 1747#elif defined(__i386) 1748 1749 ENTRY(repinsw) 1750 pushl %edi 1751 movl PORT(%esp), %edx 1752 movl ADDR(%esp), %edi 1753 movl COUNT(%esp), %ecx 1754 rep 1755 D16 insl 1756 popl %edi 1757 ret 1758 SET_SIZE(repinsw) 1759 1760#endif /* __i386 */ 1761#endif /* __lint */ 1762 1763 1764#if defined(__lint) 1765 1766/* ARGSUSED */ 1767void 1768repinsb(int port, uint8_t *addr, int count) 1769{} 1770 1771#else /* __lint */ 1772 1773#if defined(__amd64) 1774 1775 ENTRY(repinsb) 1776 movl %edx, %ecx 1777 movw %di, %dx 1778 movq %rsi, %rdi 1779 rep 1780 insb 1781 ret 1782 SET_SIZE(repinsb) 1783 1784#elif defined(__i386) 1785 1786 /* 1787 * The arguments and saved registers are on the stack in the 1788 * following order: 1789 * | cnt | +16 1790 * | *addr | +12 1791 * | port | +8 1792 * | eip | +4 1793 * | esi | <-- %esp 1794 * If additional values are pushed onto the stack, make sure 1795 * to adjust the following constants accordingly. 1796 */ 1797 .set IO_PORT, 8 1798 .set IO_ADDR, 12 1799 .set IO_COUNT, 16 1800 1801 ENTRY(repinsb) 1802 pushl %edi 1803 movl IO_ADDR(%esp), %edi 1804 movl IO_COUNT(%esp), %ecx 1805 movl IO_PORT(%esp), %edx 1806 rep 1807 insb 1808 popl %edi 1809 ret 1810 SET_SIZE(repinsb) 1811 1812#endif /* __i386 */ 1813#endif /* __lint */ 1814 1815 1816/* 1817 * Input a stream of 32-bit words. 1818 * NOTE: count is a DWORD count. 1819 */ 1820#if defined(__lint) 1821 1822/* ARGSUSED */ 1823void 1824repinsd(int port, uint32_t *addr, int count) 1825{} 1826 1827#else /* __lint */ 1828 1829#if defined(__amd64) 1830 1831 ENTRY(repinsd) 1832 movl %edx, %ecx 1833 movw %di, %dx 1834 movq %rsi, %rdi 1835 rep 1836 insl 1837 ret 1838 SET_SIZE(repinsd) 1839 1840#elif defined(__i386) 1841 1842 ENTRY(repinsd) 1843 pushl %edi 1844 movl IO_ADDR(%esp), %edi 1845 movl IO_COUNT(%esp), %ecx 1846 movl IO_PORT(%esp), %edx 1847 rep 1848 insl 1849 popl %edi 1850 ret 1851 SET_SIZE(repinsd) 1852 1853#endif /* __i386 */ 1854#endif /* __lint */ 1855 1856/* 1857 * Output a stream of bytes 1858 * NOTE: count is a byte count 1859 */ 1860#if defined(__lint) 1861 1862/* ARGSUSED */ 1863void 1864repoutsb(int port, uint8_t *addr, int count) 1865{} 1866 1867#else /* __lint */ 1868 1869#if defined(__amd64) 1870 1871 ENTRY(repoutsb) 1872 movl %edx, %ecx 1873 movw %di, %dx 1874 rep 1875 outsb 1876 ret 1877 SET_SIZE(repoutsb) 1878 1879#elif defined(__i386) 1880 1881 ENTRY(repoutsb) 1882 pushl %esi 1883 movl IO_ADDR(%esp), %esi 1884 movl IO_COUNT(%esp), %ecx 1885 movl IO_PORT(%esp), %edx 1886 rep 1887 outsb 1888 popl %esi 1889 ret 1890 SET_SIZE(repoutsb) 1891 1892#endif /* __i386 */ 1893#endif /* __lint */ 1894 1895/* 1896 * Output a stream of 32-bit words 1897 * NOTE: count is a DWORD count 1898 */ 1899#if defined(__lint) 1900 1901/* ARGSUSED */ 1902void 1903repoutsd(int port, uint32_t *addr, int count) 1904{} 1905 1906#else /* __lint */ 1907 1908#if defined(__amd64) 1909 1910 ENTRY(repoutsd) 1911 movl %edx, %ecx 1912 movw %di, %dx 1913 rep 1914 outsl 1915 ret 1916 SET_SIZE(repoutsd) 1917 1918#elif defined(__i386) 1919 1920 ENTRY(repoutsd) 1921 pushl %esi 1922 movl IO_ADDR(%esp), %esi 1923 movl IO_COUNT(%esp), %ecx 1924 movl IO_PORT(%esp), %edx 1925 rep 1926 outsl 1927 popl %esi 1928 ret 1929 SET_SIZE(repoutsd) 1930 1931#endif /* __i386 */ 1932#endif /* __lint */ 1933 1934/* 1935 * void int20(void) 1936 */ 1937 1938#if defined(__lint) 1939 1940void 1941int20(void) 1942{} 1943 1944#else /* __lint */ 1945 1946 ENTRY(int20) 1947 movl boothowto, %eax 1948 andl $RB_DEBUG, %eax 1949 jz 1f 1950 1951 int $20 19521: 1953 rep; ret /* use 2 byte return instruction when branch target */ 1954 /* AMD Software Optimization Guide - Section 6.2 */ 1955 SET_SIZE(int20) 1956 1957#endif /* __lint */ 1958 1959#if defined(__lint) 1960 1961/* ARGSUSED */ 1962int 1963scanc(size_t size, uchar_t *cp, uchar_t *table, uchar_t mask) 1964{ return (0); } 1965 1966#else /* __lint */ 1967 1968#if defined(__amd64) 1969 1970 ENTRY(scanc) 1971 /* rdi == size */ 1972 /* rsi == cp */ 1973 /* rdx == table */ 1974 /* rcx == mask */ 1975 addq %rsi, %rdi /* end = &cp[size] */ 1976.scanloop: 1977 cmpq %rdi, %rsi /* while (cp < end */ 1978 jnb .scandone 1979 movzbq (%rsi), %r8 /* %r8 = *cp */ 1980 incq %rsi /* cp++ */ 1981 testb %cl, (%r8, %rdx) 1982 jz .scanloop /* && (table[*cp] & mask) == 0) */ 1983 decq %rsi /* (fix post-increment) */ 1984.scandone: 1985 movl %edi, %eax 1986 subl %esi, %eax /* return (end - cp) */ 1987 ret 1988 SET_SIZE(scanc) 1989 1990#elif defined(__i386) 1991 1992 ENTRY(scanc) 1993 pushl %edi 1994 pushl %esi 1995 movb 24(%esp), %cl /* mask = %cl */ 1996 movl 16(%esp), %esi /* cp = %esi */ 1997 movl 20(%esp), %edx /* table = %edx */ 1998 movl %esi, %edi 1999 addl 12(%esp), %edi /* end = &cp[size]; */ 2000.scanloop: 2001 cmpl %edi, %esi /* while (cp < end */ 2002 jnb .scandone 2003 movzbl (%esi), %eax /* %al = *cp */ 2004 incl %esi /* cp++ */ 2005 movb (%edx, %eax), %al /* %al = table[*cp] */ 2006 testb %al, %cl 2007 jz .scanloop /* && (table[*cp] & mask) == 0) */ 2008 dec %esi /* post-incremented */ 2009.scandone: 2010 movl %edi, %eax 2011 subl %esi, %eax /* return (end - cp) */ 2012 popl %esi 2013 popl %edi 2014 ret 2015 SET_SIZE(scanc) 2016 2017#endif /* __i386 */ 2018#endif /* __lint */ 2019 2020/* 2021 * Replacement functions for ones that are normally inlined. 2022 * In addition to the copy in i86.il, they are defined here just in case. 2023 */ 2024 2025#if defined(__lint) 2026 2027int 2028intr_clear(void) 2029{ return 0; } 2030 2031int 2032clear_int_flag(void) 2033{ return 0; } 2034 2035#else /* __lint */ 2036 2037#if defined(__amd64) 2038 2039 ENTRY(intr_clear) 2040 ENTRY(clear_int_flag) 2041 pushfq 2042 cli 2043 popq %rax 2044 ret 2045 SET_SIZE(clear_int_flag) 2046 SET_SIZE(intr_clear) 2047 2048#elif defined(__i386) 2049 2050 ENTRY(intr_clear) 2051 ENTRY(clear_int_flag) 2052 pushfl 2053 cli 2054 popl %eax 2055 ret 2056 SET_SIZE(clear_int_flag) 2057 SET_SIZE(intr_clear) 2058 2059#endif /* __i386 */ 2060#endif /* __lint */ 2061 2062#if defined(__lint) 2063 2064struct cpu * 2065curcpup(void) 2066{ return 0; } 2067 2068#else /* __lint */ 2069 2070#if defined(__amd64) 2071 2072 ENTRY(curcpup) 2073 movq %gs:CPU_SELF, %rax 2074 ret 2075 SET_SIZE(curcpup) 2076 2077#elif defined(__i386) 2078 2079 ENTRY(curcpup) 2080 movl %gs:CPU_SELF, %eax 2081 ret 2082 SET_SIZE(curcpup) 2083 2084#endif /* __i386 */ 2085#endif /* __lint */ 2086 2087#if defined(__lint) 2088 2089/* ARGSUSED */ 2090uint32_t 2091htonl(uint32_t i) 2092{ return (0); } 2093 2094/* ARGSUSED */ 2095uint32_t 2096ntohl(uint32_t i) 2097{ return (0); } 2098 2099#else /* __lint */ 2100 2101#if defined(__amd64) 2102 2103 /* XX64 there must be shorter sequences for this */ 2104 ENTRY(htonl) 2105 ALTENTRY(ntohl) 2106 movl %edi, %eax 2107 bswap %eax 2108 ret 2109 SET_SIZE(ntohl) 2110 SET_SIZE(htonl) 2111 2112#elif defined(__i386) 2113 2114 ENTRY(htonl) 2115 ALTENTRY(ntohl) 2116 movl 4(%esp), %eax 2117 bswap %eax 2118 ret 2119 SET_SIZE(ntohl) 2120 SET_SIZE(htonl) 2121 2122#endif /* __i386 */ 2123#endif /* __lint */ 2124 2125#if defined(__lint) 2126 2127/* ARGSUSED */ 2128uint16_t 2129htons(uint16_t i) 2130{ return (0); } 2131 2132/* ARGSUSED */ 2133uint16_t 2134ntohs(uint16_t i) 2135{ return (0); } 2136 2137 2138#else /* __lint */ 2139 2140#if defined(__amd64) 2141 2142 /* XX64 there must be better sequences for this */ 2143 ENTRY(htons) 2144 ALTENTRY(ntohs) 2145 movl %edi, %eax 2146 bswap %eax 2147 shrl $16, %eax 2148 ret 2149 SET_SIZE(ntohs) 2150 SET_SIZE(htons) 2151 2152#elif defined(__i386) 2153 2154 ENTRY(htons) 2155 ALTENTRY(ntohs) 2156 movl 4(%esp), %eax 2157 bswap %eax 2158 shrl $16, %eax 2159 ret 2160 SET_SIZE(ntohs) 2161 SET_SIZE(htons) 2162 2163#endif /* __i386 */ 2164#endif /* __lint */ 2165 2166 2167#if defined(__lint) 2168 2169/* ARGSUSED */ 2170void 2171intr_restore(uint_t i) 2172{ return; } 2173 2174/* ARGSUSED */ 2175void 2176restore_int_flag(int i) 2177{ return; } 2178 2179#else /* __lint */ 2180 2181#if defined(__amd64) 2182 2183 ENTRY(intr_restore) 2184 ENTRY(restore_int_flag) 2185 pushq %rdi 2186 popfq 2187 ret 2188 SET_SIZE(restore_int_flag) 2189 SET_SIZE(intr_restore) 2190 2191#elif defined(__i386) 2192 2193 ENTRY(intr_restore) 2194 ENTRY(restore_int_flag) 2195 pushl 4(%esp) 2196 popfl 2197 ret 2198 SET_SIZE(restore_int_flag) 2199 SET_SIZE(intr_restore) 2200 2201#endif /* __i386 */ 2202#endif /* __lint */ 2203 2204#if defined(__lint) 2205 2206void 2207sti(void) 2208{} 2209 2210#else /* __lint */ 2211 2212 ENTRY(sti) 2213 sti 2214 ret 2215 SET_SIZE(sti) 2216 2217#endif /* __lint */ 2218 2219#if defined(__lint) 2220 2221dtrace_icookie_t 2222dtrace_interrupt_disable(void) 2223{ return (0); } 2224 2225#else /* __lint */ 2226 2227#if defined(__amd64) 2228 2229 ENTRY(dtrace_interrupt_disable) 2230 pushfq 2231 popq %rax 2232 cli 2233 ret 2234 SET_SIZE(dtrace_interrupt_disable) 2235 2236#elif defined(__i386) 2237 2238 ENTRY(dtrace_interrupt_disable) 2239 pushfl 2240 popl %eax 2241 cli 2242 ret 2243 SET_SIZE(dtrace_interrupt_disable) 2244 2245#endif /* __i386 */ 2246#endif /* __lint */ 2247 2248#if defined(__lint) 2249 2250/*ARGSUSED*/ 2251void 2252dtrace_interrupt_enable(dtrace_icookie_t cookie) 2253{} 2254 2255#else /* __lint */ 2256 2257#if defined(__amd64) 2258 2259 ENTRY(dtrace_interrupt_enable) 2260 pushq %rdi 2261 popfq 2262 ret 2263 SET_SIZE(dtrace_interrupt_enable) 2264 2265#elif defined(__i386) 2266 2267 ENTRY(dtrace_interrupt_enable) 2268 movl 4(%esp), %eax 2269 pushl %eax 2270 popfl 2271 ret 2272 SET_SIZE(dtrace_interrupt_enable) 2273 2274#endif /* __i386 */ 2275#endif /* __lint */ 2276 2277 2278#if defined(lint) 2279 2280void 2281dtrace_membar_producer(void) 2282{} 2283 2284void 2285dtrace_membar_consumer(void) 2286{} 2287 2288#else /* __lint */ 2289 2290 ENTRY(dtrace_membar_producer) 2291 rep; ret /* use 2 byte return instruction when branch target */ 2292 /* AMD Software Optimization Guide - Section 6.2 */ 2293 SET_SIZE(dtrace_membar_producer) 2294 2295 ENTRY(dtrace_membar_consumer) 2296 rep; ret /* use 2 byte return instruction when branch target */ 2297 /* AMD Software Optimization Guide - Section 6.2 */ 2298 SET_SIZE(dtrace_membar_consumer) 2299 2300#endif /* __lint */ 2301 2302#if defined(__lint) 2303 2304kthread_id_t 2305threadp(void) 2306{ return ((kthread_id_t)0); } 2307 2308#else /* __lint */ 2309 2310#if defined(__amd64) 2311 2312 ENTRY(threadp) 2313 movq %gs:CPU_THREAD, %rax 2314 ret 2315 SET_SIZE(threadp) 2316 2317#elif defined(__i386) 2318 2319 ENTRY(threadp) 2320 movl %gs:CPU_THREAD, %eax 2321 ret 2322 SET_SIZE(threadp) 2323 2324#endif /* __i386 */ 2325#endif /* __lint */ 2326 2327/* 2328 * Checksum routine for Internet Protocol Headers 2329 */ 2330 2331#if defined(__lint) 2332 2333/* ARGSUSED */ 2334unsigned int 2335ip_ocsum( 2336 ushort_t *address, /* ptr to 1st message buffer */ 2337 int halfword_count, /* length of data */ 2338 unsigned int sum) /* partial checksum */ 2339{ 2340 int i; 2341 unsigned int psum = 0; /* partial sum */ 2342 2343 for (i = 0; i < halfword_count; i++, address++) { 2344 psum += *address; 2345 } 2346 2347 while ((psum >> 16) != 0) { 2348 psum = (psum & 0xffff) + (psum >> 16); 2349 } 2350 2351 psum += sum; 2352 2353 while ((psum >> 16) != 0) { 2354 psum = (psum & 0xffff) + (psum >> 16); 2355 } 2356 2357 return (psum); 2358} 2359 2360#else /* __lint */ 2361 2362#if defined(__amd64) 2363 2364 ENTRY(ip_ocsum) 2365 pushq %rbp 2366 movq %rsp, %rbp 2367#ifdef DEBUG 2368 movq kernelbase(%rip), %rax 2369 cmpq %rax, %rdi 2370 jnb 1f 2371 xorl %eax, %eax 2372 movq %rdi, %rsi 2373 leaq .ip_ocsum_panic_msg(%rip), %rdi 2374 call panic 2375 /*NOTREACHED*/ 2376.ip_ocsum_panic_msg: 2377 .string "ip_ocsum: address 0x%p below kernelbase\n" 23781: 2379#endif 2380 movl %esi, %ecx /* halfword_count */ 2381 movq %rdi, %rsi /* address */ 2382 /* partial sum in %edx */ 2383 xorl %eax, %eax 2384 testl %ecx, %ecx 2385 jz .ip_ocsum_done 2386 testq $3, %rsi 2387 jnz .ip_csum_notaligned 2388.ip_csum_aligned: /* XX64 opportunities for 8-byte operations? */ 2389.next_iter: 2390 /* XX64 opportunities for prefetch? */ 2391 /* XX64 compute csum with 64 bit quantities? */ 2392 subl $32, %ecx 2393 jl .less_than_32 2394 2395 addl 0(%rsi), %edx 2396.only60: 2397 adcl 4(%rsi), %eax 2398.only56: 2399 adcl 8(%rsi), %edx 2400.only52: 2401 adcl 12(%rsi), %eax 2402.only48: 2403 adcl 16(%rsi), %edx 2404.only44: 2405 adcl 20(%rsi), %eax 2406.only40: 2407 adcl 24(%rsi), %edx 2408.only36: 2409 adcl 28(%rsi), %eax 2410.only32: 2411 adcl 32(%rsi), %edx 2412.only28: 2413 adcl 36(%rsi), %eax 2414.only24: 2415 adcl 40(%rsi), %edx 2416.only20: 2417 adcl 44(%rsi), %eax 2418.only16: 2419 adcl 48(%rsi), %edx 2420.only12: 2421 adcl 52(%rsi), %eax 2422.only8: 2423 adcl 56(%rsi), %edx 2424.only4: 2425 adcl 60(%rsi), %eax /* could be adding -1 and -1 with a carry */ 2426.only0: 2427 adcl $0, %eax /* could be adding -1 in eax with a carry */ 2428 adcl $0, %eax 2429 2430 addq $64, %rsi 2431 testl %ecx, %ecx 2432 jnz .next_iter 2433 2434.ip_ocsum_done: 2435 addl %eax, %edx 2436 adcl $0, %edx 2437 movl %edx, %eax /* form a 16 bit checksum by */ 2438 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2439 addw %dx, %ax 2440 adcw $0, %ax 2441 andl $0xffff, %eax 2442 leave 2443 ret 2444 2445.ip_csum_notaligned: 2446 xorl %edi, %edi 2447 movw (%rsi), %di 2448 addl %edi, %edx 2449 adcl $0, %edx 2450 addq $2, %rsi 2451 decl %ecx 2452 jmp .ip_csum_aligned 2453 2454.less_than_32: 2455 addl $32, %ecx 2456 testl $1, %ecx 2457 jz .size_aligned 2458 andl $0xfe, %ecx 2459 movzwl (%rsi, %rcx, 2), %edi 2460 addl %edi, %edx 2461 adcl $0, %edx 2462.size_aligned: 2463 movl %ecx, %edi 2464 shrl $1, %ecx 2465 shl $1, %edi 2466 subq $64, %rdi 2467 addq %rdi, %rsi 2468 leaq .ip_ocsum_jmptbl(%rip), %rdi 2469 leaq (%rdi, %rcx, 8), %rdi 2470 xorl %ecx, %ecx 2471 clc 2472 jmp *(%rdi) 2473 2474 .align 8 2475.ip_ocsum_jmptbl: 2476 .quad .only0, .only4, .only8, .only12, .only16, .only20 2477 .quad .only24, .only28, .only32, .only36, .only40, .only44 2478 .quad .only48, .only52, .only56, .only60 2479 SET_SIZE(ip_ocsum) 2480 2481#elif defined(__i386) 2482 2483 ENTRY(ip_ocsum) 2484 pushl %ebp 2485 movl %esp, %ebp 2486 pushl %ebx 2487 pushl %esi 2488 pushl %edi 2489 movl 12(%ebp), %ecx /* count of half words */ 2490 movl 16(%ebp), %edx /* partial checksum */ 2491 movl 8(%ebp), %esi 2492 xorl %eax, %eax 2493 testl %ecx, %ecx 2494 jz .ip_ocsum_done 2495 2496 testl $3, %esi 2497 jnz .ip_csum_notaligned 2498.ip_csum_aligned: 2499.next_iter: 2500 subl $32, %ecx 2501 jl .less_than_32 2502 2503 addl 0(%esi), %edx 2504.only60: 2505 adcl 4(%esi), %eax 2506.only56: 2507 adcl 8(%esi), %edx 2508.only52: 2509 adcl 12(%esi), %eax 2510.only48: 2511 adcl 16(%esi), %edx 2512.only44: 2513 adcl 20(%esi), %eax 2514.only40: 2515 adcl 24(%esi), %edx 2516.only36: 2517 adcl 28(%esi), %eax 2518.only32: 2519 adcl 32(%esi), %edx 2520.only28: 2521 adcl 36(%esi), %eax 2522.only24: 2523 adcl 40(%esi), %edx 2524.only20: 2525 adcl 44(%esi), %eax 2526.only16: 2527 adcl 48(%esi), %edx 2528.only12: 2529 adcl 52(%esi), %eax 2530.only8: 2531 adcl 56(%esi), %edx 2532.only4: 2533 adcl 60(%esi), %eax /* We could be adding -1 and -1 with a carry */ 2534.only0: 2535 adcl $0, %eax /* we could be adding -1 in eax with a carry */ 2536 adcl $0, %eax 2537 2538 addl $64, %esi 2539 andl %ecx, %ecx 2540 jnz .next_iter 2541 2542.ip_ocsum_done: 2543 addl %eax, %edx 2544 adcl $0, %edx 2545 movl %edx, %eax /* form a 16 bit checksum by */ 2546 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2547 addw %dx, %ax 2548 adcw $0, %ax 2549 andl $0xffff, %eax 2550 popl %edi /* restore registers */ 2551 popl %esi 2552 popl %ebx 2553 leave 2554 ret 2555 2556.ip_csum_notaligned: 2557 xorl %edi, %edi 2558 movw (%esi), %di 2559 addl %edi, %edx 2560 adcl $0, %edx 2561 addl $2, %esi 2562 decl %ecx 2563 jmp .ip_csum_aligned 2564 2565.less_than_32: 2566 addl $32, %ecx 2567 testl $1, %ecx 2568 jz .size_aligned 2569 andl $0xfe, %ecx 2570 movzwl (%esi, %ecx, 2), %edi 2571 addl %edi, %edx 2572 adcl $0, %edx 2573.size_aligned: 2574 movl %ecx, %edi 2575 shrl $1, %ecx 2576 shl $1, %edi 2577 subl $64, %edi 2578 addl %edi, %esi 2579 movl $.ip_ocsum_jmptbl, %edi 2580 lea (%edi, %ecx, 4), %edi 2581 xorl %ecx, %ecx 2582 clc 2583 jmp *(%edi) 2584 SET_SIZE(ip_ocsum) 2585 2586 .data 2587 .align 4 2588 2589.ip_ocsum_jmptbl: 2590 .long .only0, .only4, .only8, .only12, .only16, .only20 2591 .long .only24, .only28, .only32, .only36, .only40, .only44 2592 .long .only48, .only52, .only56, .only60 2593 2594 2595#endif /* __i386 */ 2596#endif /* __lint */ 2597 2598/* 2599 * multiply two long numbers and yield a u_longlong_t result, callable from C. 2600 * Provided to manipulate hrtime_t values. 2601 */ 2602#if defined(__lint) 2603 2604/* result = a * b; */ 2605 2606/* ARGSUSED */ 2607unsigned long long 2608mul32(uint_t a, uint_t b) 2609{ return (0); } 2610 2611#else /* __lint */ 2612 2613#if defined(__amd64) 2614 2615 ENTRY(mul32) 2616 xorl %edx, %edx /* XX64 joe, paranoia? */ 2617 movl %edi, %eax 2618 mull %esi 2619 shlq $32, %rdx 2620 orq %rdx, %rax 2621 ret 2622 SET_SIZE(mul32) 2623 2624#elif defined(__i386) 2625 2626 ENTRY(mul32) 2627 movl 8(%esp), %eax 2628 movl 4(%esp), %ecx 2629 mull %ecx 2630 ret 2631 SET_SIZE(mul32) 2632 2633#endif /* __i386 */ 2634#endif /* __lint */ 2635 2636#if defined(notused) 2637#if defined(__lint) 2638/* ARGSUSED */ 2639void 2640load_pte64(uint64_t *pte, uint64_t pte_value) 2641{} 2642#else /* __lint */ 2643 .globl load_pte64 2644load_pte64: 2645 movl 4(%esp), %eax 2646 movl 8(%esp), %ecx 2647 movl 12(%esp), %edx 2648 movl %edx, 4(%eax) 2649 movl %ecx, (%eax) 2650 ret 2651#endif /* __lint */ 2652#endif /* notused */ 2653 2654#if defined(__lint) 2655 2656/*ARGSUSED*/ 2657void 2658scan_memory(caddr_t addr, size_t size) 2659{} 2660 2661#else /* __lint */ 2662 2663#if defined(__amd64) 2664 2665 ENTRY(scan_memory) 2666 shrq $3, %rsi /* convert %rsi from byte to quadword count */ 2667 jz .scanm_done 2668 movq %rsi, %rcx /* move count into rep control register */ 2669 movq %rdi, %rsi /* move addr into lodsq control reg. */ 2670 rep lodsq /* scan the memory range */ 2671.scanm_done: 2672 rep; ret /* use 2 byte return instruction when branch target */ 2673 /* AMD Software Optimization Guide - Section 6.2 */ 2674 SET_SIZE(scan_memory) 2675 2676#elif defined(__i386) 2677 2678 ENTRY(scan_memory) 2679 pushl %ecx 2680 pushl %esi 2681 movl 16(%esp), %ecx /* move 2nd arg into rep control register */ 2682 shrl $2, %ecx /* convert from byte count to word count */ 2683 jz .scanm_done 2684 movl 12(%esp), %esi /* move 1st arg into lodsw control register */ 2685 .byte 0xf3 /* rep prefix. lame assembler. sigh. */ 2686 lodsl 2687.scanm_done: 2688 popl %esi 2689 popl %ecx 2690 ret 2691 SET_SIZE(scan_memory) 2692 2693#endif /* __i386 */ 2694#endif /* __lint */ 2695 2696 2697#if defined(__lint) 2698 2699/*ARGSUSED */ 2700int 2701lowbit(ulong_t i) 2702{ return (0); } 2703 2704#else /* __lint */ 2705 2706#if defined(__amd64) 2707 2708 ENTRY(lowbit) 2709 movl $-1, %eax 2710 bsfq %rdi, %rax 2711 incl %eax 2712 ret 2713 SET_SIZE(lowbit) 2714 2715#elif defined(__i386) 2716 2717 ENTRY(lowbit) 2718 movl $-1, %eax 2719 bsfl 4(%esp), %eax 2720 incl %eax 2721 ret 2722 SET_SIZE(lowbit) 2723 2724#endif /* __i386 */ 2725#endif /* __lint */ 2726 2727#if defined(__lint) 2728 2729/*ARGSUSED*/ 2730int 2731highbit(ulong_t i) 2732{ return (0); } 2733 2734#else /* __lint */ 2735 2736#if defined(__amd64) 2737 2738 ENTRY(highbit) 2739 movl $-1, %eax 2740 bsrq %rdi, %rax 2741 incl %eax 2742 ret 2743 SET_SIZE(highbit) 2744 2745#elif defined(__i386) 2746 2747 ENTRY(highbit) 2748 movl $-1, %eax 2749 bsrl 4(%esp), %eax 2750 incl %eax 2751 ret 2752 SET_SIZE(highbit) 2753 2754#endif /* __i386 */ 2755#endif /* __lint */ 2756 2757#if defined(__lint) 2758 2759/*ARGSUSED*/ 2760uint64_t 2761rdmsr(uint_t r) 2762{ return (0); } 2763 2764/*ARGSUSED*/ 2765void 2766wrmsr(uint_t r, const uint64_t val) 2767{} 2768 2769void 2770invalidate_cache(void) 2771{} 2772 2773#else /* __lint */ 2774 2775#if defined(__amd64) 2776 2777 ENTRY(rdmsr) 2778 movl %edi, %ecx 2779 rdmsr 2780 shlq $32, %rdx 2781 orq %rdx, %rax 2782 ret 2783 SET_SIZE(rdmsr) 2784 2785 ENTRY(wrmsr) 2786 movq %rsi, %rdx 2787 shrq $32, %rdx 2788 movl %esi, %eax 2789 movl %edi, %ecx 2790 wrmsr 2791 ret 2792 SET_SIZE(wrmsr) 2793 2794#elif defined(__i386) 2795 2796 ENTRY(rdmsr) 2797 movl 4(%esp), %ecx 2798 rdmsr 2799 ret 2800 SET_SIZE(rdmsr) 2801 2802 ENTRY(wrmsr) 2803 movl 4(%esp), %ecx 2804 movl 8(%esp), %eax 2805 movl 12(%esp), %edx 2806 wrmsr 2807 ret 2808 SET_SIZE(wrmsr) 2809 2810#endif /* __i386 */ 2811 2812 ENTRY(invalidate_cache) 2813 wbinvd 2814 ret 2815 SET_SIZE(invalidate_cache) 2816 2817#endif /* __lint */ 2818 2819#if defined(__lint) 2820 2821/*ARGSUSED*/ 2822void getcregs(struct cregs *crp) 2823{} 2824 2825#else /* __lint */ 2826 2827#if defined(__amd64) 2828 2829#define GETMSR(r, off, d) \ 2830 movl $r, %ecx; \ 2831 rdmsr; \ 2832 movl %eax, off(d); \ 2833 movl %edx, off+4(d) 2834 2835 ENTRY_NP(getcregs) 2836 xorl %eax, %eax 2837 movq %rax, CREG_GDT+8(%rdi) 2838 sgdt CREG_GDT(%rdi) /* 10 bytes */ 2839 movq %rax, CREG_IDT+8(%rdi) 2840 sidt CREG_IDT(%rdi) /* 10 bytes */ 2841 movq %rax, CREG_LDT(%rdi) 2842 sldt CREG_LDT(%rdi) /* 2 bytes */ 2843 movq %rax, CREG_TASKR(%rdi) 2844 str CREG_TASKR(%rdi) /* 2 bytes */ 2845 movq %cr0, %rax 2846 movq %rax, CREG_CR0(%rdi) /* cr0 */ 2847 movq %cr2, %rax 2848 movq %rax, CREG_CR2(%rdi) /* cr2 */ 2849 movq %cr3, %rax 2850 movq %rax, CREG_CR3(%rdi) /* cr3 */ 2851 movq %cr4, %rax 2852 movq %rax, CREG_CR8(%rdi) /* cr4 */ 2853 movq %cr8, %rax 2854 movq %rax, CREG_CR8(%rdi) /* cr8 */ 2855 GETMSR(MSR_AMD_KGSBASE, CREG_KGSBASE, %rdi) 2856 GETMSR(MSR_AMD_EFER, CREG_EFER, %rdi) 2857 SET_SIZE(getcregs) 2858 2859#undef GETMSR 2860 2861#elif defined(__i386) 2862 2863 ENTRY_NP(getcregs) 2864 movl 4(%esp), %edx 2865 movw $0, CREG_GDT+6(%edx) 2866 movw $0, CREG_IDT+6(%edx) 2867 sgdt CREG_GDT(%edx) /* gdt */ 2868 sidt CREG_IDT(%edx) /* idt */ 2869 sldt CREG_LDT(%edx) /* ldt */ 2870 str CREG_TASKR(%edx) /* task */ 2871 movl %cr0, %eax 2872 movl %eax, CREG_CR0(%edx) /* cr0 */ 2873 movl %cr2, %eax 2874 movl %eax, CREG_CR2(%edx) /* cr2 */ 2875 movl %cr3, %eax 2876 movl %eax, CREG_CR3(%edx) /* cr3 */ 2877 testl $X86_LARGEPAGE, x86_feature 2878 jz .nocr4 2879 movl %cr4, %eax 2880 movl %eax, CREG_CR4(%edx) /* cr4 */ 2881 jmp .skip 2882.nocr4: 2883 movl $0, CREG_CR4(%edx) 2884.skip: 2885 rep; ret /* use 2 byte return instruction when branch target */ 2886 /* AMD Software Optimization Guide - Section 6.2 */ 2887 SET_SIZE(getcregs) 2888 2889#endif /* __i386 */ 2890#endif /* __lint */ 2891 2892 2893/* 2894 * A panic trigger is a word which is updated atomically and can only be set 2895 * once. We atomically store 0xDEFACEDD and load the old value. If the 2896 * previous value was 0, we succeed and return 1; otherwise return 0. 2897 * This allows a partially corrupt trigger to still trigger correctly. DTrace 2898 * has its own version of this function to allow it to panic correctly from 2899 * probe context. 2900 */ 2901#if defined(__lint) 2902 2903/*ARGSUSED*/ 2904int 2905panic_trigger(int *tp) 2906{ return (0); } 2907 2908/*ARGSUSED*/ 2909int 2910dtrace_panic_trigger(int *tp) 2911{ return (0); } 2912 2913#else /* __lint */ 2914 2915#if defined(__amd64) 2916 2917 ENTRY_NP(panic_trigger) 2918 xorl %eax, %eax 2919 movl $0xdefacedd, %edx 2920 lock 2921 xchgl %edx, (%rdi) 2922 cmpl $0, %edx 2923 je 0f 2924 movl $0, %eax 2925 ret 29260: movl $1, %eax 2927 ret 2928 SET_SIZE(panic_trigger) 2929 2930 ENTRY_NP(dtrace_panic_trigger) 2931 xorl %eax, %eax 2932 movl $0xdefacedd, %edx 2933 lock 2934 xchgl %edx, (%rdi) 2935 cmpl $0, %edx 2936 je 0f 2937 movl $0, %eax 2938 ret 29390: movl $1, %eax 2940 ret 2941 SET_SIZE(dtrace_panic_trigger) 2942 2943#elif defined(__i386) 2944 2945 ENTRY_NP(panic_trigger) 2946 movl 4(%esp), %edx / %edx = address of trigger 2947 movl $0xdefacedd, %eax / %eax = 0xdefacedd 2948 lock / assert lock 2949 xchgl %eax, (%edx) / exchange %eax and the trigger 2950 cmpl $0, %eax / if (%eax == 0x0) 2951 je 0f / return (1); 2952 movl $0, %eax / else 2953 ret / return (0); 29540: movl $1, %eax 2955 ret 2956 SET_SIZE(panic_trigger) 2957 2958 ENTRY_NP(dtrace_panic_trigger) 2959 movl 4(%esp), %edx / %edx = address of trigger 2960 movl $0xdefacedd, %eax / %eax = 0xdefacedd 2961 lock / assert lock 2962 xchgl %eax, (%edx) / exchange %eax and the trigger 2963 cmpl $0, %eax / if (%eax == 0x0) 2964 je 0f / return (1); 2965 movl $0, %eax / else 2966 ret / return (0); 29670: movl $1, %eax 2968 ret 2969 SET_SIZE(dtrace_panic_trigger) 2970 2971#endif /* __i386 */ 2972#endif /* __lint */ 2973 2974/* 2975 * The panic() and cmn_err() functions invoke vpanic() as a common entry point 2976 * into the panic code implemented in panicsys(). vpanic() is responsible 2977 * for passing through the format string and arguments, and constructing a 2978 * regs structure on the stack into which it saves the current register 2979 * values. If we are not dying due to a fatal trap, these registers will 2980 * then be preserved in panicbuf as the current processor state. Before 2981 * invoking panicsys(), vpanic() activates the first panic trigger (see 2982 * common/os/panic.c) and switches to the panic_stack if successful. Note that 2983 * DTrace takes a slightly different panic path if it must panic from probe 2984 * context. Instead of calling panic, it calls into dtrace_vpanic(), which 2985 * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and 2986 * branches back into vpanic(). 2987 */ 2988#if defined(__lint) 2989 2990/*ARGSUSED*/ 2991void 2992vpanic(const char *format, va_list alist) 2993{} 2994 2995/*ARGSUSED*/ 2996void 2997dtrace_vpanic(const char *format, va_list alist) 2998{} 2999 3000#else /* __lint */ 3001 3002#if defined(__amd64) 3003 3004 ENTRY_NP(vpanic) /* Initial stack layout: */ 3005 3006 pushq %rbp /* | %rip | 0x60 */ 3007 movq %rsp, %rbp /* | %rbp | 0x58 */ 3008 pushfq /* | rfl | 0x50 */ 3009 pushq %r11 /* | %r11 | 0x48 */ 3010 pushq %r10 /* | %r10 | 0x40 */ 3011 pushq %rbx /* | %rbx | 0x38 */ 3012 pushq %rax /* | %rax | 0x30 */ 3013 pushq %r9 /* | %r9 | 0x28 */ 3014 pushq %r8 /* | %r8 | 0x20 */ 3015 pushq %rcx /* | %rcx | 0x18 */ 3016 pushq %rdx /* | %rdx | 0x10 */ 3017 pushq %rsi /* | %rsi | 0x8 alist */ 3018 pushq %rdi /* | %rdi | 0x0 format */ 3019 3020 movq %rsp, %rbx /* %rbx = current %rsp */ 3021 3022 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 3023 call panic_trigger /* %eax = panic_trigger() */ 3024 3025vpanic_common: 3026 cmpl $0, %eax 3027 je 0f 3028 3029 /* 3030 * If panic_trigger() was successful, we are the first to initiate a 3031 * panic: we now switch to the reserved panic_stack before continuing. 3032 */ 3033 leaq panic_stack(%rip), %rsp 3034 addq $PANICSTKSIZE, %rsp 30350: subq $REGSIZE, %rsp 3036 /* 3037 * Now that we've got everything set up, store the register values as 3038 * they were when we entered vpanic() to the designated location in 3039 * the regs structure we allocated on the stack. 3040 */ 3041 movq 0x0(%rbx), %rcx 3042 movq %rcx, REGOFF_RDI(%rsp) 3043 movq 0x8(%rbx), %rcx 3044 movq %rcx, REGOFF_RSI(%rsp) 3045 movq 0x10(%rbx), %rcx 3046 movq %rcx, REGOFF_RDX(%rsp) 3047 movq 0x18(%rbx), %rcx 3048 movq %rcx, REGOFF_RCX(%rsp) 3049 movq 0x20(%rbx), %rcx 3050 3051 movq %rcx, REGOFF_R8(%rsp) 3052 movq 0x28(%rbx), %rcx 3053 movq %rcx, REGOFF_R9(%rsp) 3054 movq 0x30(%rbx), %rcx 3055 movq %rcx, REGOFF_RAX(%rsp) 3056 movq 0x38(%rbx), %rcx 3057 movq %rbx, REGOFF_RBX(%rsp) 3058 movq 0x58(%rbx), %rcx 3059 3060 movq %rcx, REGOFF_RBP(%rsp) 3061 movq 0x40(%rbx), %rcx 3062 movq %rcx, REGOFF_R10(%rsp) 3063 movq 0x48(%rbx), %rcx 3064 movq %rcx, REGOFF_R11(%rsp) 3065 movq %r12, REGOFF_R12(%rsp) 3066 3067 movq %r13, REGOFF_R13(%rsp) 3068 movq %r14, REGOFF_R14(%rsp) 3069 movq %r15, REGOFF_R15(%rsp) 3070 3071 movl $MSR_AMD_FSBASE, %ecx 3072 rdmsr 3073 movl %eax, REGOFF_FSBASE(%rsp) 3074 movl %edx, REGOFF_FSBASE+4(%rsp) 3075 3076 movl $MSR_AMD_GSBASE, %ecx 3077 rdmsr 3078 movl %eax, REGOFF_GSBASE(%rsp) 3079 movl %edx, REGOFF_GSBASE+4(%rsp) 3080 3081 xorl %ecx, %ecx 3082 movw %ds, %cx 3083 movq %rcx, REGOFF_DS(%rsp) 3084 movw %es, %cx 3085 movq %rcx, REGOFF_ES(%rsp) 3086 movw %fs, %cx 3087 movq %rcx, REGOFF_FS(%rsp) 3088 movw %gs, %cx 3089 movq %rcx, REGOFF_GS(%rsp) 3090 3091 movq $0, REGOFF_TRAPNO(%rsp) 3092 3093 movq $0, REGOFF_ERR(%rsp) 3094 leaq vpanic(%rip), %rcx 3095 movq %rcx, REGOFF_RIP(%rsp) 3096 movw %cs, %cx 3097 movzwq %cx, %rcx 3098 movq %rcx, REGOFF_CS(%rsp) 3099 movq 0x50(%rbx), %rcx 3100 movq %rcx, REGOFF_RFL(%rsp) 3101 movq %rbx, %rcx 3102 addq $0x60, %rcx 3103 movq %rcx, REGOFF_RSP(%rsp) 3104 movw %ss, %cx 3105 movzwq %cx, %rcx 3106 movq %rcx, REGOFF_SS(%rsp) 3107 3108 /* 3109 * panicsys(format, alist, rp, on_panic_stack) 3110 */ 3111 movq REGOFF_RDI(%rsp), %rdi /* format */ 3112 movq REGOFF_RSI(%rsp), %rsi /* alist */ 3113 movq %rsp, %rdx /* struct regs */ 3114 movl %eax, %ecx /* on_panic_stack */ 3115 call panicsys 3116 addq $REGSIZE, %rsp 3117 popq %rdi 3118 popq %rsi 3119 popq %rdx 3120 popq %rcx 3121 popq %r8 3122 popq %r9 3123 popq %rax 3124 popq %rbx 3125 popq %r10 3126 popq %r11 3127 popfq 3128 leave 3129 ret 3130 SET_SIZE(vpanic) 3131 3132 ENTRY_NP(dtrace_vpanic) /* Initial stack layout: */ 3133 3134 pushq %rbp /* | %rip | 0x60 */ 3135 movq %rsp, %rbp /* | %rbp | 0x58 */ 3136 pushfq /* | rfl | 0x50 */ 3137 pushq %r11 /* | %r11 | 0x48 */ 3138 pushq %r10 /* | %r10 | 0x40 */ 3139 pushq %rbx /* | %rbx | 0x38 */ 3140 pushq %rax /* | %rax | 0x30 */ 3141 pushq %r9 /* | %r9 | 0x28 */ 3142 pushq %r8 /* | %r8 | 0x20 */ 3143 pushq %rcx /* | %rcx | 0x18 */ 3144 pushq %rdx /* | %rdx | 0x10 */ 3145 pushq %rsi /* | %rsi | 0x8 alist */ 3146 pushq %rdi /* | %rdi | 0x0 format */ 3147 3148 movq %rsp, %rbx /* %rbx = current %rsp */ 3149 3150 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 3151 call dtrace_panic_trigger /* %eax = dtrace_panic_trigger() */ 3152 jmp vpanic_common 3153 3154 SET_SIZE(dtrace_vpanic) 3155 3156#elif defined(__i386) 3157 3158 ENTRY_NP(vpanic) / Initial stack layout: 3159 3160 pushl %ebp / | %eip | 20 3161 movl %esp, %ebp / | %ebp | 16 3162 pushl %eax / | %eax | 12 3163 pushl %ebx / | %ebx | 8 3164 pushl %ecx / | %ecx | 4 3165 pushl %edx / | %edx | 0 3166 3167 movl %esp, %ebx / %ebx = current stack pointer 3168 3169 lea panic_quiesce, %eax / %eax = &panic_quiesce 3170 pushl %eax / push &panic_quiesce 3171 call panic_trigger / %eax = panic_trigger() 3172 addl $4, %esp / reset stack pointer 3173 3174vpanic_common: 3175 cmpl $0, %eax / if (%eax == 0) 3176 je 0f / goto 0f; 3177 3178 /* 3179 * If panic_trigger() was successful, we are the first to initiate a 3180 * panic: we now switch to the reserved panic_stack before continuing. 3181 */ 3182 lea panic_stack, %esp / %esp = panic_stack 3183 addl $PANICSTKSIZE, %esp / %esp += PANICSTKSIZE 3184 31850: subl $REGSIZE, %esp / allocate struct regs 3186 3187 /* 3188 * Now that we've got everything set up, store the register values as 3189 * they were when we entered vpanic() to the designated location in 3190 * the regs structure we allocated on the stack. 3191 */ 3192#if !defined(__GNUC_AS__) 3193 movw %gs, %edx 3194 movl %edx, REGOFF_GS(%esp) 3195 movw %fs, %edx 3196 movl %edx, REGOFF_FS(%esp) 3197 movw %es, %edx 3198 movl %edx, REGOFF_ES(%esp) 3199 movw %ds, %edx 3200 movl %edx, REGOFF_DS(%esp) 3201#else /* __GNUC_AS__ */ 3202 mov %gs, %edx 3203 mov %edx, REGOFF_GS(%esp) 3204 mov %fs, %edx 3205 mov %edx, REGOFF_FS(%esp) 3206 mov %es, %edx 3207 mov %edx, REGOFF_ES(%esp) 3208 mov %ds, %edx 3209 mov %edx, REGOFF_DS(%esp) 3210#endif /* __GNUC_AS__ */ 3211 movl %edi, REGOFF_EDI(%esp) 3212 movl %esi, REGOFF_ESI(%esp) 3213 movl 16(%ebx), %ecx 3214 movl %ecx, REGOFF_EBP(%esp) 3215 movl %ebx, %ecx 3216 addl $20, %ecx 3217 movl %ecx, REGOFF_ESP(%esp) 3218 movl 8(%ebx), %ecx 3219 movl %ecx, REGOFF_EBX(%esp) 3220 movl 0(%ebx), %ecx 3221 movl %ecx, REGOFF_EDX(%esp) 3222 movl 4(%ebx), %ecx 3223 movl %ecx, REGOFF_ECX(%esp) 3224 movl 12(%ebx), %ecx 3225 movl %ecx, REGOFF_EAX(%esp) 3226 movl $0, REGOFF_TRAPNO(%esp) 3227 movl $0, REGOFF_ERR(%esp) 3228 lea vpanic, %ecx 3229 movl %ecx, REGOFF_EIP(%esp) 3230#if !defined(__GNUC_AS__) 3231 movw %cs, %edx 3232#else /* __GNUC_AS__ */ 3233 mov %cs, %edx 3234#endif /* __GNUC_AS__ */ 3235 movl %edx, REGOFF_CS(%esp) 3236 pushfl 3237 popl %ecx 3238 movl %ecx, REGOFF_EFL(%esp) 3239 movl $0, REGOFF_UESP(%esp) 3240#if !defined(__GNUC_AS__) 3241 movw %ss, %edx 3242#else /* __GNUC_AS__ */ 3243 mov %ss, %edx 3244#endif /* __GNUC_AS__ */ 3245 movl %edx, REGOFF_SS(%esp) 3246 3247 movl %esp, %ecx / %ecx = ®s 3248 pushl %eax / push on_panic_stack 3249 pushl %ecx / push ®s 3250 movl 12(%ebp), %ecx / %ecx = alist 3251 pushl %ecx / push alist 3252 movl 8(%ebp), %ecx / %ecx = format 3253 pushl %ecx / push format 3254 call panicsys / panicsys(); 3255 addl $16, %esp / pop arguments 3256 3257 addl $REGSIZE, %esp 3258 popl %edx 3259 popl %ecx 3260 popl %ebx 3261 popl %eax 3262 leave 3263 ret 3264 SET_SIZE(vpanic) 3265 3266 ENTRY_NP(dtrace_vpanic) / Initial stack layout: 3267 3268 pushl %ebp / | %eip | 20 3269 movl %esp, %ebp / | %ebp | 16 3270 pushl %eax / | %eax | 12 3271 pushl %ebx / | %ebx | 8 3272 pushl %ecx / | %ecx | 4 3273 pushl %edx / | %edx | 0 3274 3275 movl %esp, %ebx / %ebx = current stack pointer 3276 3277 lea panic_quiesce, %eax / %eax = &panic_quiesce 3278 pushl %eax / push &panic_quiesce 3279 call dtrace_panic_trigger / %eax = dtrace_panic_trigger() 3280 addl $4, %esp / reset stack pointer 3281 jmp vpanic_common / jump back to common code 3282 3283 SET_SIZE(dtrace_vpanic) 3284 3285#endif /* __i386 */ 3286#endif /* __lint */ 3287 3288#if defined(__lint) 3289 3290void 3291hres_tick(void) 3292{} 3293 3294int64_t timedelta; 3295hrtime_t hres_last_tick; 3296timestruc_t hrestime; 3297int64_t hrestime_adj; 3298volatile int hres_lock; 3299uint_t nsec_scale; 3300hrtime_t hrtime_base; 3301 3302#else /* __lint */ 3303 3304 DGDEF3(hrestime, _MUL(2, CLONGSIZE), 8) 3305 .NWORD 0, 0 3306 3307 DGDEF3(hrestime_adj, 8, 8) 3308 .long 0, 0 3309 3310 DGDEF3(hres_last_tick, 8, 8) 3311 .long 0, 0 3312 3313 DGDEF3(timedelta, 8, 8) 3314 .long 0, 0 3315 3316 DGDEF3(hres_lock, 4, 8) 3317 .long 0 3318 3319 /* 3320 * initialized to a non zero value to make pc_gethrtime() 3321 * work correctly even before clock is initialized 3322 */ 3323 DGDEF3(hrtime_base, 8, 8) 3324 .long _MUL(NSEC_PER_CLOCK_TICK, 6), 0 3325 3326 DGDEF3(adj_shift, 4, 4) 3327 .long ADJ_SHIFT 3328 3329#if defined(__amd64) 3330 3331 ENTRY_NP(hres_tick) 3332 pushq %rbp 3333 movq %rsp, %rbp 3334 3335 /* 3336 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3337 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3338 * At worst, performing this now instead of under CLOCK_LOCK may 3339 * introduce some jitter in pc_gethrestime(). 3340 */ 3341 call *gethrtimef(%rip) 3342 movq %rax, %r8 3343 3344 leaq hres_lock(%rip), %rax 3345 movb $-1, %dl 3346.CL1: 3347 xchgb %dl, (%rax) 3348 testb %dl, %dl 3349 jz .CL3 /* got it */ 3350.CL2: 3351 cmpb $0, (%rax) /* possible to get lock? */ 3352 pause 3353 jne .CL2 3354 jmp .CL1 /* yes, try again */ 3355.CL3: 3356 /* 3357 * compute the interval since last time hres_tick was called 3358 * and adjust hrtime_base and hrestime accordingly 3359 * hrtime_base is an 8 byte value (in nsec), hrestime is 3360 * a timestruc_t (sec, nsec) 3361 */ 3362 leaq hres_last_tick(%rip), %rax 3363 movq %r8, %r11 3364 subq (%rax), %r8 3365 addq %r8, hrtime_base(%rip) /* add interval to hrtime_base */ 3366 addq %r8, hrestime+8(%rip) /* add interval to hrestime.tv_nsec */ 3367 /* 3368 * Now that we have CLOCK_LOCK, we can update hres_last_tick 3369 */ 3370 movq %r11, (%rax) 3371 3372 call __adj_hrestime 3373 3374 /* 3375 * release the hres_lock 3376 */ 3377 incl hres_lock(%rip) 3378 leave 3379 ret 3380 SET_SIZE(hres_tick) 3381 3382#elif defined(__i386) 3383 3384 ENTRY_NP(hres_tick) 3385 pushl %ebp 3386 movl %esp, %ebp 3387 pushl %esi 3388 pushl %ebx 3389 3390 /* 3391 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3392 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3393 * At worst, performing this now instead of under CLOCK_LOCK may 3394 * introduce some jitter in pc_gethrestime(). 3395 */ 3396 call *gethrtimef 3397 movl %eax, %ebx 3398 movl %edx, %esi 3399 3400 movl $hres_lock, %eax 3401 movl $-1, %edx 3402.CL1: 3403 xchgb %dl, (%eax) 3404 testb %dl, %dl 3405 jz .CL3 / got it 3406.CL2: 3407 cmpb $0, (%eax) / possible to get lock? 3408 pause 3409 jne .CL2 3410 jmp .CL1 / yes, try again 3411.CL3: 3412 /* 3413 * compute the interval since last time hres_tick was called 3414 * and adjust hrtime_base and hrestime accordingly 3415 * hrtime_base is an 8 byte value (in nsec), hrestime is 3416 * timestruc_t (sec, nsec) 3417 */ 3418 3419 lea hres_last_tick, %eax 3420 3421 movl %ebx, %edx 3422 movl %esi, %ecx 3423 3424 subl (%eax), %edx 3425 sbbl 4(%eax), %ecx 3426 3427 addl %edx, hrtime_base / add interval to hrtime_base 3428 adcl %ecx, hrtime_base+4 3429 3430 addl %edx, hrestime+4 / add interval to hrestime.tv_nsec 3431 3432 / 3433 / Now that we have CLOCK_LOCK, we can update hres_last_tick. 3434 / 3435 movl %ebx, (%eax) 3436 movl %esi, 4(%eax) 3437 3438 / get hrestime at this moment. used as base for pc_gethrestime 3439 / 3440 / Apply adjustment, if any 3441 / 3442 / #define HRES_ADJ (NSEC_PER_CLOCK_TICK >> ADJ_SHIFT) 3443 / (max_hres_adj) 3444 / 3445 / void 3446 / adj_hrestime() 3447 / { 3448 / long long adj; 3449 / 3450 / if (hrestime_adj == 0) 3451 / adj = 0; 3452 / else if (hrestime_adj > 0) { 3453 / if (hrestime_adj < HRES_ADJ) 3454 / adj = hrestime_adj; 3455 / else 3456 / adj = HRES_ADJ; 3457 / } 3458 / else { 3459 / if (hrestime_adj < -(HRES_ADJ)) 3460 / adj = -(HRES_ADJ); 3461 / else 3462 / adj = hrestime_adj; 3463 / } 3464 / 3465 / timedelta -= adj; 3466 / hrestime_adj = timedelta; 3467 / hrestime.tv_nsec += adj; 3468 / 3469 / while (hrestime.tv_nsec >= NANOSEC) { 3470 / one_sec++; 3471 / hrestime.tv_sec++; 3472 / hrestime.tv_nsec -= NANOSEC; 3473 / } 3474 / } 3475__adj_hrestime: 3476 movl hrestime_adj, %esi / if (hrestime_adj == 0) 3477 movl hrestime_adj+4, %edx 3478 andl %esi, %esi 3479 jne .CL4 / no 3480 andl %edx, %edx 3481 jne .CL4 / no 3482 subl %ecx, %ecx / yes, adj = 0; 3483 subl %edx, %edx 3484 jmp .CL5 3485.CL4: 3486 subl %ecx, %ecx 3487 subl %eax, %eax 3488 subl %esi, %ecx 3489 sbbl %edx, %eax 3490 andl %eax, %eax / if (hrestime_adj > 0) 3491 jge .CL6 3492 3493 / In the following comments, HRES_ADJ is used, while in the code 3494 / max_hres_adj is used. 3495 / 3496 / The test for "hrestime_adj < HRES_ADJ" is complicated because 3497 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3498 / on the logical equivalence of: 3499 / 3500 / !(hrestime_adj < HRES_ADJ) 3501 / 3502 / and the two step sequence: 3503 / 3504 / (HRES_ADJ - lsw(hrestime_adj)) generates a Borrow/Carry 3505 / 3506 / which computes whether or not the least significant 32-bits 3507 / of hrestime_adj is greater than HRES_ADJ, followed by: 3508 / 3509 / Previous Borrow/Carry + -1 + msw(hrestime_adj) generates a Carry 3510 / 3511 / which generates a carry whenever step 1 is true or the most 3512 / significant long of the longlong hrestime_adj is non-zero. 3513 3514 movl max_hres_adj, %ecx / hrestime_adj is positive 3515 subl %esi, %ecx 3516 movl %edx, %eax 3517 adcl $-1, %eax 3518 jnc .CL7 3519 movl max_hres_adj, %ecx / adj = HRES_ADJ; 3520 subl %edx, %edx 3521 jmp .CL5 3522 3523 / The following computation is similar to the one above. 3524 / 3525 / The test for "hrestime_adj < -(HRES_ADJ)" is complicated because 3526 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3527 / on the logical equivalence of: 3528 / 3529 / (hrestime_adj > -HRES_ADJ) 3530 / 3531 / and the two step sequence: 3532 / 3533 / (HRES_ADJ + lsw(hrestime_adj)) generates a Carry 3534 / 3535 / which means the least significant 32-bits of hrestime_adj is 3536 / greater than -HRES_ADJ, followed by: 3537 / 3538 / Previous Carry + 0 + msw(hrestime_adj) generates a Carry 3539 / 3540 / which generates a carry only when step 1 is true and the most 3541 / significant long of the longlong hrestime_adj is -1. 3542 3543.CL6: / hrestime_adj is negative 3544 movl %esi, %ecx 3545 addl max_hres_adj, %ecx 3546 movl %edx, %eax 3547 adcl $0, %eax 3548 jc .CL7 3549 xor %ecx, %ecx 3550 subl max_hres_adj, %ecx / adj = -(HRES_ADJ); 3551 movl $-1, %edx 3552 jmp .CL5 3553.CL7: 3554 movl %esi, %ecx / adj = hrestime_adj; 3555.CL5: 3556 movl timedelta, %esi 3557 subl %ecx, %esi 3558 movl timedelta+4, %eax 3559 sbbl %edx, %eax 3560 movl %esi, timedelta 3561 movl %eax, timedelta+4 / timedelta -= adj; 3562 movl %esi, hrestime_adj 3563 movl %eax, hrestime_adj+4 / hrestime_adj = timedelta; 3564 addl hrestime+4, %ecx 3565 3566 movl %ecx, %eax / eax = tv_nsec 35671: 3568 cmpl $NANOSEC, %eax / if ((unsigned long)tv_nsec >= NANOSEC) 3569 jb .CL8 / no 3570 incl one_sec / yes, one_sec++; 3571 incl hrestime / hrestime.tv_sec++; 3572 addl $-NANOSEC, %eax / tv_nsec -= NANOSEC 3573 jmp 1b / check for more seconds 3574 3575.CL8: 3576 movl %eax, hrestime+4 / store final into hrestime.tv_nsec 3577 incl hres_lock / release the hres_lock 3578 3579 popl %ebx 3580 popl %esi 3581 leave 3582 ret 3583 SET_SIZE(hres_tick) 3584 3585#endif /* __i386 */ 3586#endif /* __lint */ 3587 3588/* 3589 * void prefetch_smap_w(void *) 3590 * 3591 * Prefetch ahead within a linear list of smap structures. 3592 * Not implemented for ia32. Stub for compatibility. 3593 */ 3594 3595#if defined(__lint) 3596 3597/*ARGSUSED*/ 3598void prefetch_smap_w(void *smp) 3599{} 3600 3601#else /* __lint */ 3602 3603 ENTRY(prefetch_smap_w) 3604 rep; ret /* use 2 byte return instruction when branch target */ 3605 /* AMD Software Optimization Guide - Section 6.2 */ 3606 SET_SIZE(prefetch_smap_w) 3607 3608#endif /* __lint */ 3609 3610/* 3611 * prefetch_page_r(page_t *) 3612 * issue prefetch instructions for a page_t 3613 */ 3614#if defined(__lint) 3615 3616/*ARGSUSED*/ 3617void 3618prefetch_page_r(void *pp) 3619{} 3620 3621#else /* __lint */ 3622 3623 ENTRY(prefetch_page_r) 3624 rep; ret /* use 2 byte return instruction when branch target */ 3625 /* AMD Software Optimization Guide - Section 6.2 */ 3626 SET_SIZE(prefetch_page_r) 3627 3628#endif /* __lint */ 3629 3630#if defined(__lint) 3631 3632/*ARGSUSED*/ 3633int 3634bcmp(const void *s1, const void *s2, size_t count) 3635{ return (0); } 3636 3637#else /* __lint */ 3638 3639#if defined(__amd64) 3640 3641 ENTRY(bcmp) 3642 pushq %rbp 3643 movq %rsp, %rbp 3644#ifdef DEBUG 3645 movq kernelbase(%rip), %r11 3646 cmpq %r11, %rdi 3647 jb 0f 3648 cmpq %r11, %rsi 3649 jnb 1f 36500: leaq .bcmp_panic_msg(%rip), %rdi 3651 xorl %eax, %eax 3652 call panic 36531: 3654#endif /* DEBUG */ 3655 call memcmp 3656 testl %eax, %eax 3657 setne %dl 3658 leave 3659 movzbl %dl, %eax 3660 ret 3661 SET_SIZE(bcmp) 3662 3663#elif defined(__i386) 3664 3665#define ARG_S1 8 3666#define ARG_S2 12 3667#define ARG_LENGTH 16 3668 3669 ENTRY(bcmp) 3670#ifdef DEBUG 3671 pushl %ebp 3672 movl %esp, %ebp 3673 movl kernelbase, %eax 3674 cmpl %eax, ARG_S1(%ebp) 3675 jb 0f 3676 cmpl %eax, ARG_S2(%ebp) 3677 jnb 1f 36780: pushl $.bcmp_panic_msg 3679 call panic 36801: popl %ebp 3681#endif /* DEBUG */ 3682 3683 pushl %edi / save register variable 3684 movl ARG_S1(%esp), %eax / %eax = address of string 1 3685 movl ARG_S2(%esp), %ecx / %ecx = address of string 2 3686 cmpl %eax, %ecx / if the same string 3687 je .equal / goto .equal 3688 movl ARG_LENGTH(%esp), %edi / %edi = length in bytes 3689 cmpl $4, %edi / if %edi < 4 3690 jb .byte_check / goto .byte_check 3691 .align 4 3692.word_loop: 3693 movl (%ecx), %edx / move 1 word from (%ecx) to %edx 3694 leal -4(%edi), %edi / %edi -= 4 3695 cmpl (%eax), %edx / compare 1 word from (%eax) with %edx 3696 jne .word_not_equal / if not equal, goto .word_not_equal 3697 leal 4(%ecx), %ecx / %ecx += 4 (next word) 3698 leal 4(%eax), %eax / %eax += 4 (next word) 3699 cmpl $4, %edi / if %edi >= 4 3700 jae .word_loop / goto .word_loop 3701.byte_check: 3702 cmpl $0, %edi / if %edi == 0 3703 je .equal / goto .equal 3704 jmp .byte_loop / goto .byte_loop (checks in bytes) 3705.word_not_equal: 3706 leal 4(%edi), %edi / %edi += 4 (post-decremented) 3707 .align 4 3708.byte_loop: 3709 movb (%ecx), %dl / move 1 byte from (%ecx) to %dl 3710 cmpb %dl, (%eax) / compare %dl with 1 byte from (%eax) 3711 jne .not_equal / if not equal, goto .not_equal 3712 incl %ecx / %ecx++ (next byte) 3713 incl %eax / %eax++ (next byte) 3714 decl %edi / %edi-- 3715 jnz .byte_loop / if not zero, goto .byte_loop 3716.equal: 3717 xorl %eax, %eax / %eax = 0 3718 popl %edi / restore register variable 3719 ret / return (NULL) 3720 .align 4 3721.not_equal: 3722 movl $1, %eax / return 1 3723 popl %edi / restore register variable 3724 ret / return (NULL) 3725 SET_SIZE(bcmp) 3726 3727#endif /* __i386 */ 3728 3729#ifdef DEBUG 3730 .text 3731.bcmp_panic_msg: 3732 .string "bcmp: arguments below kernelbase" 3733#endif /* DEBUG */ 3734 3735#endif /* __lint */ 3736