xref: /titanic_50/usr/src/uts/intel/amd64/sys/privregs.h (revision 080575042aba2197b425ebfd52061dea061a9aa1)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_AMD64_SYS_PRIVREGS_H
28 #define	_AMD64_SYS_PRIVREGS_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * This file describes the cpu's privileged register set, and
38  * how the machine state is saved on the stack when a trap occurs.
39  */
40 
41 #if !defined(__amd64)
42 #error	"non-amd64 code depends on amd64 privileged header!"
43 #endif
44 
45 #ifndef _ASM
46 
47 /*
48  * This is NOT the structure to use for general purpose debugging;
49  * see /proc for that.  This is NOT the structure to use to decode
50  * the ucontext or grovel about in a core file; see <sys/regset.h>.
51  */
52 
53 struct regs {
54 	/*
55 	 * Extra frame for mdb to follow through high level interrupts and
56 	 * system traps.  Set them to 0 to terminate stacktrace.
57 	 */
58 	greg_t	r_savfp;	/* a copy of %rbp */
59 	greg_t	r_savpc;	/* a copy of %rip */
60 
61 	greg_t	r_rdi;		/* 1st arg to function */
62 	greg_t	r_rsi;		/* 2nd arg to function */
63 	greg_t	r_rdx;		/* 3rd arg to function, 2nd return register */
64 	greg_t	r_rcx;		/* 4th arg to function */
65 
66 	greg_t	r_r8;		/* 5th arg to function */
67 	greg_t	r_r9;		/* 6th arg to function */
68 	greg_t	r_rax;		/* 1st return register, # SSE registers */
69 	greg_t	r_rbx;		/* callee-saved, optional base pointer */
70 
71 	greg_t	r_rbp;		/* callee-saved, optional frame pointer */
72 	greg_t	r_r10;		/* temporary register, static chain pointer */
73 	greg_t	r_r11;		/* temporary register */
74 	greg_t	r_r12;		/* callee-saved */
75 
76 	greg_t	r_r13;		/* callee-saved */
77 	greg_t	r_r14;		/* callee-saved */
78 	greg_t	r_r15;		/* callee-saved */
79 
80 	/*
81 	 * XX64
82 	 * We used to sample fsbase and gsbase on every exception
83 	 * with expensive rdmsr's. Yet this was only useful at
84 	 * best for debugging during amd64 bringup. We should take
85 	 * these away but for now simply rename them to avoid any
86 	 * flag days.
87 	 */
88 	greg_t	__r_fsbase;	/* XX64 no longer used by the kernel */
89 	greg_t	__r_gsbase;	/* XX64 no longer used by the kernel */
90 	greg_t	r_ds;
91 	greg_t	r_es;
92 	greg_t	r_fs;		/* %fs is *never* used by the kernel */
93 	greg_t	r_gs;
94 
95 	greg_t	r_trapno;
96 
97 	/*
98 	 * (the rest of these are defined by the hardware)
99 	 */
100 	greg_t	r_err;
101 	greg_t	r_rip;
102 	greg_t	r_cs;
103 	greg_t	r_rfl;
104 	greg_t	r_rsp;
105 	greg_t	r_ss;
106 };
107 
108 #define	r_r0	r_rax	/* r0 for portability */
109 #define	r_r1	r_rdx	/* r1 for portability */
110 #define	r_fp	r_rbp	/* kernel frame pointer */
111 #define	r_sp	r_rsp	/* user stack pointer */
112 #define	r_pc	r_rip	/* user's instruction pointer */
113 #define	r_ps	r_rfl	/* user's RFLAGS */
114 
115 #ifdef _KERNEL
116 #define	lwptoregs(lwp)	((struct regs *)((lwp)->lwp_regs))
117 #endif /* _KERNEL */
118 
119 #else	/* !_ASM */
120 
121 #if defined(_MACHDEP)
122 
123 #include <sys/machprivregs.h>
124 #include <sys/pcb.h>
125 
126 /*
127  * Create a struct regs on the stack suitable for an
128  * interrupt trap.
129  *
130  * Assumes that the trap handler has already pushed an
131  * appropriate r_err and r_trapno
132  */
133 #define	__SAVE_REGS				\
134 	movq	%r15, REGOFF_R15(%rsp);		\
135 	movq	%r14, REGOFF_R14(%rsp);		\
136 	movq	%r13, REGOFF_R13(%rsp);		\
137 	movq	%r12, REGOFF_R12(%rsp);		\
138 	movq	%r11, REGOFF_R11(%rsp);		\
139 	movq	%r10, REGOFF_R10(%rsp);		\
140 	movq	%rbp, REGOFF_RBP(%rsp);		\
141 	movq	%rbx, REGOFF_RBX(%rsp);		\
142 	movq	%rax, REGOFF_RAX(%rsp);		\
143 	movq	%r9, REGOFF_R9(%rsp);		\
144 	movq	%r8, REGOFF_R8(%rsp);		\
145 	movq	%rcx, REGOFF_RCX(%rsp);		\
146 	movq	%rdx, REGOFF_RDX(%rsp);		\
147 	movq	%rsi, REGOFF_RSI(%rsp);		\
148 	movq	%rdi, REGOFF_RDI(%rsp);		\
149 	movq	%rbp, REGOFF_SAVFP(%rsp);	\
150 	movq	REGOFF_RIP(%rsp), %rcx;		\
151 	movq	%rcx, REGOFF_SAVPC(%rsp);	\
152 	xorl	%ecx, %ecx;			\
153 	movw	%gs, %cx;			\
154 	movq	%rcx, REGOFF_GS(%rsp);		\
155 	movw	%fs, %cx;			\
156 	movq	%rcx, REGOFF_FS(%rsp);		\
157 	movw	%es, %cx;			\
158 	movq	%rcx, REGOFF_ES(%rsp);		\
159 	movw	%ds, %cx;			\
160 	movq	%rcx, REGOFF_DS(%rsp)
161 
162 #define	__RESTORE_REGS				\
163 	movq	REGOFF_RDI(%rsp),	%rdi;	\
164 	movq	REGOFF_RSI(%rsp),	%rsi;	\
165 	movq	REGOFF_RDX(%rsp),	%rdx;	\
166 	movq	REGOFF_RCX(%rsp),	%rcx;	\
167 	movq	REGOFF_R8(%rsp),	%r8;	\
168 	movq	REGOFF_R9(%rsp),	%r9;	\
169 	movq	REGOFF_RAX(%rsp),	%rax;	\
170 	movq	REGOFF_RBX(%rsp),	%rbx;	\
171 	movq	REGOFF_RBP(%rsp),	%rbp;	\
172 	movq	REGOFF_R10(%rsp),	%r10;	\
173 	movq	REGOFF_R11(%rsp),	%r11;	\
174 	movq	REGOFF_R12(%rsp),	%r12;	\
175 	movq	REGOFF_R13(%rsp),	%r13;	\
176 	movq	REGOFF_R14(%rsp),	%r14;	\
177 	movq	REGOFF_R15(%rsp),	%r15
178 
179 /*
180  * Push register state onto the stack. If we've
181  * interrupted userland, do a swapgs as well.
182  */
183 #define	INTR_PUSH				\
184 	subq	$REGOFF_TRAPNO, %rsp;		\
185 	__SAVE_REGS;				\
186 	cmpw	$KCS_SEL, REGOFF_CS(%rsp);	\
187 	je	6f;				\
188 	movq	$0, REGOFF_SAVFP(%rsp);		\
189 	SWAPGS;					\
190 6:	CLEAN_CS
191 
192 #define	INTR_POP			\
193 	leaq	sys_lcall32(%rip), %r11;\
194 	cmpq	%r11, REGOFF_RIP(%rsp);	\
195 	__RESTORE_REGS;			\
196 	je	5f;			\
197 	cmpw	$KCS_SEL, REGOFF_CS(%rsp);\
198 	je	8f;			\
199 5:	SWAPGS;				\
200 8:	addq	$REGOFF_RIP, %rsp
201 
202 #define	USER_POP			\
203 	__RESTORE_REGS;			\
204 	SWAPGS;				\
205 	addq	$REGOFF_RIP, %rsp	/* Adjust %rsp to prepare for iretq */
206 
207 #define	USER32_POP			\
208 	movl	REGOFF_RDI(%rsp), %edi;	\
209 	movl	REGOFF_RSI(%rsp), %esi;	\
210 	movl	REGOFF_RDX(%rsp), %edx;	\
211 	movl	REGOFF_RCX(%rsp), %ecx;	\
212 	movl	REGOFF_RAX(%rsp), %eax;	\
213 	movl	REGOFF_RBX(%rsp), %ebx;	\
214 	movl	REGOFF_RBP(%rsp), %ebp;	\
215 	SWAPGS;				\
216 	addq	$REGOFF_RIP, %rsp	/* Adjust %rsp to prepare for iretq */
217 
218 #define	DFTRAP_PUSH				\
219 	subq	$REGOFF_TRAPNO, %rsp;		\
220 	__SAVE_REGS
221 
222 #endif	/* _MACHDEP */
223 
224 /*
225  * Used to set rflags to known values at the head of an
226  * interrupt gate handler, i.e. interrupts are -already- disabled.
227  */
228 #define	INTGATE_INIT_KERNEL_FLAGS	\
229 	pushq	$F_OFF;			\
230 	popfq
231 
232 #endif	/* !_ASM */
233 
234 #include <sys/controlregs.h>
235 
236 #if defined(_KERNEL) && !defined(_ASM)
237 #if !defined(__lint) && defined(__GNUC__)
238 
239 extern __inline__ ulong_t getcr8(void)
240 {
241 	uint64_t value;
242 
243 	__asm__ __volatile__(
244 		"movq %%cr8, %0"
245 		: "=r" (value));
246 	return (value);
247 }
248 
249 extern __inline__ void setcr8(ulong_t value)
250 {
251 	__asm__ __volatile__(
252 		"movq %0, %%cr8"
253 		: /* no output */
254 		: "r" (value));
255 }
256 
257 #else
258 
259 extern ulong_t getcr8(void);
260 extern void setcr8(ulong_t);
261 
262 #endif	/* !defined(__lint) && defined(__GNUC__) */
263 #endif	/* _KERNEL && !_ASM */
264 
265 /* Control register layout for panic dump */
266 
267 #define	CREGSZ		0x68
268 #define	CREG_GDT	0
269 #define	CREG_IDT	0x10
270 #define	CREG_LDT	0x20
271 #define	CREG_TASKR	0x28
272 #define	CREG_CR0	0x30
273 #define	CREG_CR2	0x38
274 #define	CREG_CR3	0x40
275 #define	CREG_CR4	0x48
276 #define	CREG_CR8	0x50
277 #define	CREG_KGSBASE	0x58
278 #define	CREG_EFER	0x60
279 
280 #if !defined(_ASM) && defined(_INT64_TYPE)
281 
282 typedef	uint64_t	creg64_t;
283 typedef	upad128_t	creg128_t;
284 
285 struct cregs {
286 	creg128_t	cr_gdt;
287 	creg128_t	cr_idt;
288 	creg64_t	cr_ldt;
289 	creg64_t	cr_task;
290 	creg64_t	cr_cr0;
291 	creg64_t	cr_cr2;
292 	creg64_t	cr_cr3;
293 	creg64_t	cr_cr4;
294 	creg64_t	cr_cr8;
295 	creg64_t	cr_kgsbase;
296 	creg64_t	cr_efer;
297 };
298 
299 #if defined(_KERNEL)
300 extern void getcregs(struct cregs *);
301 #endif	/* _KERNEL */
302 
303 #endif	/* !_ASM && _INT64_TYPE */
304 
305 #ifdef __cplusplus
306 }
307 #endif
308 
309 #endif	/* !_AMD64_SYS_PRIVREGS_H */
310